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[/] [or1k/] [trunk/] [or1ksim/] [testbench/] [cache.ld] - Blame information for rev 956

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MEMORY
        {
        except : ORIGIN = 0x00000000, LENGTH = 0x00002000
        ram    : ORIGIN = 0x00002000, LENGTH = 0x00200000-0x2000
        }
 
SECTIONS
{
      .except :
        {
        *(.except)
        } > except
      .text :
        {
        *(.text)
        *(.rodata)
         _src_beg = .;
        } > ram
      .data :
        {
        *(.data)
        _dst_beg = .;
        _dst_end = .;
        } > ram
      .bss :
        {
        *(.bss)
        } > ram
      .stack  ALIGN(0x10) (NOLOAD):
        {
        *(.stack)
        _ram_end = .;
        } > ram
}

Line No.	Rev	Author	Line
1	622	simons	`MEMORY`
2			`{`
3			`except : ORIGIN = 0x00000000, LENGTH = 0x00002000`
4			`ram : ORIGIN = 0x00002000, LENGTH = 0x00200000-0x2000`
5			`}`
6
7			`SECTIONS`
8			`{`
9			`.except :`
10			`{`
11			`*(.except)`
12			`} > except`
13			`.text :`
14			`{`
15			`*(.text)`
16	956	simons	`*(.rodata)`
17	622	simons	`_src_beg = .;`
18			`} > ram`
19			`.data :`
20			`{`
21			`*(.data)`
22			`_dst_beg = .;`
23			`_dst_end = .;`
24			`} > ram`
25			`.bss :`
26			`{`
27			`*(.bss)`
28			`} > ram`
29			`.stack ALIGN(0x10) (NOLOAD):`
30			`{`
31			`*(.stack)`
32			`_ram_end = .;`
33			`} > ram`
34			`}`

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[/] [or1k/] [trunk/] [or1ksim/] [testbench/] [cache.ld] - Blame information for rev 956