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/* Support file for c based tests */
 
#include "spr_defs.h"
#include "board.h"
 
#define reset _main
 
#define MC_CSR          (0x00)
#define MC_POC          (0x04)
#define MC_BA_MASK      (0x08)
#define MC_CSC(i)       (0x10 + (i) * 8)
#define MC_TMS(i)       (0x14 + (i) * 8)
 
        .global _except_basic
        .global _lo_dmmu_en
        .global _lo_immu_en
        .global _call
        .global _call_with_int
        .global _load_acc_32
        .global _load_acc_16
        .global _store_acc_32
        .global _store_acc_16
        .global _load_b_acc_32
        .global _trap
        .global _b_trap
        .global _range
        .global _b_range
        .global _int_trigger
        .global _int_loop
        .global _jump_back
 
        .section .stack
        .space 0x1000
_stack:
 
        .extern _reset_support
        .extern _c_reset
        .extern _excpt_buserr
        .extern _excpt_dpfault
        .extern _excpt_ipfault
        .extern _excpt_tick
        .extern _excpt_align
        .extern _excpt_illinsn
        .extern _excpt_int
        .extern _excpt_dtlbmiss
        .extern _excpt_itlbmiss
        .extern _excpt_range
        .extern _excpt_syscall
        .extern _excpt_break
        .extern _excpt_trap
 
  .section .except, "ax"
 
_buserr_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_buserr)
        l.ori   r10,r10,lo(_excpt_buserr)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_dpfault_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_dpfault)
        l.ori   r10,r10,lo(_excpt_dpfault)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_ipfault_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_ipfault)
        l.ori   r10,r10,lo(_excpt_ipfault)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_tick_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_tick)
        l.ori   r10,r10,lo(_excpt_tick)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_align_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_align)
        l.ori   r10,r10,lo(_excpt_align)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_illinsn_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_illinsn)
        l.ori   r10,r10,lo(_excpt_illinsn)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_int_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_int)
        l.ori   r10,r10,lo(_excpt_int)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_dtlbmiss_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_dtlbmiss)
        l.ori   r10,r10,lo(_excpt_dtlbmiss)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_itlbmiss_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_itlbmiss)
        l.ori   r10,r10,lo(_excpt_itlbmiss)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_range_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_range)
        l.ori   r10,r10,lo(_excpt_range)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_syscall_vector:
        l.addi  r3,r3,4
 
        l.mfspr r4,r0,SPR_SR
        l.andi  r4,r4,7
        l.add   r6,r0,r4
 
        l.mfspr r4,r0,SPR_EPCR_BASE
        l.movhi r5,hi(_sys1)
        l.ori r5,r5,lo(_sys1)
        l.sub r5,r4,r5
 
        l.mfspr r4,r0,SPR_ESR_BASE  /* ESR - set supvisor mode */
        l.ori r4,r4,SPR_SR_SM
        l.mtspr r0,r4,SPR_ESR_BASE
 
        l.movhi r4,hi(_sys2)
        l.ori r4,r4,lo(_sys2)
        l.mtspr r0,r4,SPR_EPCR_BASE
 
        l.rfe
        l.addi  r3,r3,8
 
_break_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_break)
        l.ori   r10,r10,lo(_excpt_break)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
_trap_vector:
        l.addi  r1,r1,-120
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.movhi r9,hi(store_regs)
        l.ori   r9,r9,lo(store_regs)
        l.movhi r10,hi(_excpt_trap)
        l.ori   r10,r10,lo(_excpt_trap)
        l.jr    r9
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        .section .text
 
        .org    0x100
_reset_vector:
        l.nop
        l.nop
        l.addi  r2,r0,0x0
        l.addi  r3,r0,0x0
        l.addi  r4,r0,0x0
        l.addi  r5,r0,0x0
        l.addi  r6,r0,0x0
        l.addi  r7,r0,0x0
        l.addi  r8,r0,0x0
        l.addi  r9,r0,0x0
        l.addi  r10,r0,0x0
        l.addi  r11,r0,0x0
        l.addi  r12,r0,0x0
        l.addi  r13,r0,0x0
        l.addi  r14,r0,0x0
        l.addi  r15,r0,0x0
        l.addi  r16,r0,0x0
        l.addi  r17,r0,0x0
        l.addi  r18,r0,0x0
        l.addi  r19,r0,0x0
        l.addi  r20,r0,0x0
        l.addi  r21,r0,0x0
        l.addi  r22,r0,0x0
        l.addi  r23,r0,0x0
        l.addi  r24,r0,0x0
        l.addi  r25,r0,0x0
        l.addi  r26,r0,0x0
        l.addi  r27,r0,0x0
        l.addi  r28,r0,0x0
        l.addi  r29,r0,0x0
        l.addi  r30,r0,0x0
        l.addi  r31,r0,0x0
 
        l.movhi r3,hi(start)
        l.ori   r3,r3,lo(start)
        l.jr    r3
        l.nop
start:
        l.jal   _init_mc
        l.nop
 
        l.movhi r1,hi(_stack)
        l.ori   r1,r1,lo(_stack)
 
        /* Setup exception wrappers */
        l.movhi r3,hi(_src_beg)
        l.ori   r3,r3,lo(_src_beg)
        l.addi  r7,r0,0x100
 
1:      l.addi  r7,r7,0x100
        l.sfeqi r7,0xf00
        l.bf    1f
        l.nop
        l.addi  r4,r7,0
        l.addi  r5,r0,0
2:
        l.lwz   r6,0(r3)
        l.sw    0(r4),r6
        l.addi  r3,r3,4
        l.addi  r4,r4,4
        l.addi  r5,r5,1
        l.sfeqi r5,16
        l.bf    1b
        l.nop
        l.j     2b
        l.nop
1:
        /* Copy data section */
        l.movhi r4,hi(_dst_beg)
        l.ori   r4,r4,lo(_dst_beg)
        l.movhi r5,hi(_dst_end)
        l.ori   r5,r5,lo(_dst_end)
        l.sub   r5,r5,r4
        l.sfeqi r5,0
        l.bf    2f
        l.nop
1:      l.lwz   r6,0(r3)
        l.sw    0(r4),r6
        l.addi  r3,r3,4
        l.addi  r4,r4,4
        l.addi  r5,r5,-4
        l.sfgtsi r5,0
        l.bf    1b
        l.nop
 
2:
 
        l.movhi r2,hi(reset)
        l.ori   r2,r2,lo(reset)
        l.jr    r2
        l.nop
 
_init_mc:
 
        l.movhi r3,hi(MC_BASE_ADDR)
        l.ori   r3,r3,lo(MC_BASE_ADDR)
 
        l.addi  r4,r3,MC_CSC(0)
        l.movhi r5,hi(FLASH_BASE_ADDR)
        l.srai  r5,r5,6
        l.ori   r5,r5,0x0025
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_TMS(0)
        l.movhi r5,hi(FLASH_TMS_VAL)
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_BA_MASK
        l.addi  r5,r0,MC_MASK_VAL
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_CSR
        l.movhi r5,hi(MC_CSR_VAL)
        l.ori   r5,r5,lo(MC_CSR_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_TMS(1)
        l.movhi r5,hi(SDRAM_TMS_VAL)
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_CSC(1)
        l.movhi r5,hi(SDRAM_BASE_ADDR)
        l.srai  r5,r5,6
        l.ori   r5,r5,0x0411
        l.sw    0(r4),r5
 
        l.jr    r9
        l.nop
 
store_regs:
        l.sw    0x00(r1),r2
        l.sw    0x04(r1),r3
        l.sw    0x08(r1),r4
        l.sw    0x0c(r1),r5
        l.sw    0x10(r1),r6
        l.sw    0x14(r1),r7
        l.sw    0x18(r1),r8
        l.sw    0x24(r1),r11
        l.sw    0x28(r1),r12
        l.sw    0x2c(r1),r13
        l.sw    0x30(r1),r14
        l.sw    0x34(r1),r15
        l.sw    0x38(r1),r16
        l.sw    0x3c(r1),r17
        l.sw    0x40(r1),r18
        l.sw    0x44(r1),r19
        l.sw    0x48(r1),r20
        l.sw    0x4c(r1),r21
        l.sw    0x50(r1),r22
        l.sw    0x54(r1),r23
        l.sw    0x58(r1),r24
        l.sw    0x5c(r1),r25
        l.sw    0x60(r1),r26
        l.sw    0x64(r1),r27
        l.sw    0x68(r1),r28
        l.sw    0x6c(r1),r29
        l.sw    0x70(r1),r30
        l.sw    0x74(r1),r31
 
        l.mfspr r3,r0,SPR_EPCR_BASE
        l.movhi r4,hi(_except_pc)
        l.ori   r4,r4,lo(_except_pc)
        l.sw    0(r4),r3
 
        l.mfspr r3,r0,SPR_EEAR_BASE
        l.movhi r4,hi(_except_ea)
        l.ori   r4,r4,lo(_except_ea)
        l.sw    0(r4),r3
 
        l.movhi r9,hi(end_except)
        l.ori   r9,r9,lo(end_except)
 
        l.lwz   r10,0(r10)
        l.jr    r10
        l.nop
 
end_except:
        l.lwz   r2,0x00(r1)
        l.lwz   r3,0x04(r1)
        l.lwz   r4,0x08(r1)
        l.lwz   r5,0x0c(r1)
        l.lwz   r6,0x10(r1)
        l.lwz   r7,0x14(r1)
        l.lwz   r8,0x18(r1)
        l.lwz   r9,0x1c(r1)
        l.lwz   r10,0x20(r1)
        l.lwz   r11,0x24(r1)
        l.lwz   r12,0x28(r1)
        l.lwz   r13,0x2c(r1)
        l.lwz   r14,0x30(r1)
        l.lwz   r15,0x34(r1)
        l.lwz   r16,0x38(r1)
        l.lwz   r17,0x3c(r1)
        l.lwz   r18,0x40(r1)
        l.lwz   r19,0x44(r1)
        l.lwz   r20,0x48(r1)
        l.lwz   r21,0x4c(r1)
        l.lwz   r22,0x50(r1)
        l.lwz   r23,0x54(r1)
        l.lwz   r24,0x58(r1)
        l.lwz   r25,0x5c(r1)
        l.lwz   r26,0x60(r1)
        l.lwz   r27,0x64(r1)
        l.lwz   r28,0x68(r1)
        l.lwz   r29,0x6c(r1)
        l.lwz   r30,0x70(r1)
        l.lwz   r31,0x74(r1)
        l.addi  r1,r1,120
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
  .section .text
 
_except_basic:
_sys1:
        l.addi  r3,r0,-2  /* Enable exceptiom recognition and external interrupt,set user mode */
        l.mfspr r4,r0,SPR_SR
        l.and   r4,r4,r3
        l.ori   r4,r4,(SPR_SR_IEE|SPR_SR_TEE)
        l.mtspr r0,r4,SPR_SR
 
        l.addi  r3,r0,0
        l.sys   1
        l.addi  r3,r3,2
 
_sys2:
        l.addi  r11,r0,0
 
        l.mfspr r4,r0,SPR_SR  /* Check SR */
        l.andi  r4,r4,(SPR_SR_IEE|SPR_SR_TEE|SPR_SR_SM)
        l.sfeqi r4,(SPR_SR_IEE|SPR_SR_TEE|SPR_SR_SM)
        l.bf    1f
        l.nop
        l.addi  r11,r11,1
1:
        l.sfeqi r3,4          /* Check if l.sys or l.rfe has delay slot */
        l.bf    1f
        l.nop
        l.addi  r11,r11,2
1:
        l.sfeqi r5,0x1c       /* Check the EPCR */
        l.bf    1f
        l.nop
        l.addi  r11,r11,4
1:
        l.sfeqi r6,SPR_SR_SM  /* Check the SR when exception is taken */
        l.bf    1f
        l.nop
        l.addi  r11,r11,8
1:
        l.jr    r9
        l.nop
 
_lo_dmmu_en:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_DME
        l.mtspr r0,r3,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
_lo_immu_en:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_IME
        l.mtspr r0,r3,SPR_ESR_BASE
        l.mtspr r0,r9,SPR_EPCR_BASE
        l.rfe
        l.nop
 
_call:
        l.addi  r11,r0,0
        l.jr    r3
        l.nop
 
_call_with_int:
        l.mfspr r8,r0,SPR_SR
        l.ori   r8,r8,SPR_SR_TEE
        l.mtspr r0,r8,SPR_ESR_BASE
        l.mtspr r0,r3,SPR_EPCR_BASE
        l.rfe
 
_load_acc_32:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.lwz   r11,0(r4)
        l.jr    r9
        l.nop
 
_load_acc_16:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.lhz   r11,0(r4)
        l.jr    r9
        l.nop
 
_store_acc_32:
        l.movhi r3,hi(0x12345678)
        l.ori   r3,r3,lo(0x12345678)
        l.sw    0(r4),r3
        l.jr    r9
        l.nop
 
_store_acc_16:
        l.movhi r3,hi(0x12345678)
        l.ori   r3,r3,lo(0x12345678)
        l.sh    0(r4),r3
        l.jr    r9
        l.nop
 
_load_b_acc_32:
        l.movhi r11,hi(0x12345678)
        l.ori   r11,r11,lo(0x12345678)
        l.jr    r9
        l.lwz   r11,0(r4)
 
_b_trap:
        l.jr    r9
_trap:
        l.trap  1
        l.jr    r9
        l.nop
 
_b_range:
        l.jr    r9
_range:
        l.addi  r3,r0,-1
        l.jr    r9
        l.nop
 
_int_trigger:
        l.addi  r11,r0,0
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_TEE
        l.mtspr r0,r3,SPR_SR
        l.addi  r11,r11,1
 
_int_loop:
        l.j     _int_loop
        l.lwz   r5,0(r4);
 
_jump_back:
        l.addi  r11,r0,0
        l.jr    r9
        l.addi  r11,r11,1
 

Line No.	Rev	Author	Line
1	519	simons	`/* Support file for c based tests */`
2
3			`#include "spr_defs.h"`
4	970	simons	`#include "board.h"`
5	519	simons
6			`#define reset _main`
7
8	970	simons	`#define MC_CSR (0x00)`
9			`#define MC_POC (0x04)`
10			`#define MC_BA_MASK (0x08)`
11			`#define MC_CSC(i) (0x10 + (i) * 8)`
12			`#define MC_TMS(i) (0x14 + (i) * 8)`
13
14	519	simons	`.global _except_basic`
15			`.global _lo_dmmu_en`
16			`.global _lo_immu_en`
17			`.global _call`
18			`.global _call_with_int`
19			`.global _load_acc_32`
20			`.global _load_acc_16`
21			`.global _store_acc_32`
22			`.global _store_acc_16`
23			`.global _load_b_acc_32`
24			`.global _trap`
25			`.global _b_trap`
26			`.global _range`
27			`.global _b_range`
28			`.global _int_trigger`
29			`.global _int_loop`
30			`.global _jump_back`
31
32			`.section .stack`
33			`.space 0x1000`
34			`_stack:`
35
36			`.extern _reset_support`
37			`.extern _c_reset`
38			`.extern _excpt_buserr`
39			`.extern _excpt_dpfault`
40			`.extern _excpt_ipfault`
41	600	simons	`.extern _excpt_tick`
42	519	simons	`.extern _excpt_align`
43			`.extern _excpt_illinsn`
44	600	simons	`.extern _excpt_int`
45	519	simons	`.extern _excpt_dtlbmiss`
46			`.extern _excpt_itlbmiss`
47			`.extern _excpt_range`
48			`.extern _excpt_syscall`
49			`.extern _excpt_break`
50			`.extern _excpt_trap`
51
52	970	simons	`.section .except, "ax"`
53	519	simons
54	970	simons	`_buserr_vector:`
55			`l.addi r1,r1,-120`
56			`l.sw 0x1c(r1),r9`
57			`l.sw 0x20(r1),r10`
58			`l.movhi r9,hi(store_regs)`
59			`l.ori r9,r9,lo(store_regs)`
60			`l.movhi r10,hi(_excpt_buserr)`
61			`l.ori r10,r10,lo(_excpt_buserr)`
62			`l.jr r9`
63	519	simons	`l.nop`
64			`l.nop`
65			`l.nop`
66			`l.nop`
67			`l.nop`
68			`l.nop`
69			`l.nop`
70			`l.nop`
71
72			`_dpfault_vector:`
73	970	simons	`l.addi r1,r1,-120`
74			`l.sw 0x1c(r1),r9`
75			`l.sw 0x20(r1),r10`
76			`l.movhi r9,hi(store_regs)`
77			`l.ori r9,r9,lo(store_regs)`
78	519	simons	`l.movhi r10,hi(_excpt_dpfault)`
79			`l.ori r10,r10,lo(_excpt_dpfault)`
80	970	simons	`l.jr r9`
81	519	simons	`l.nop`
82	970	simons	`l.nop`
83			`l.nop`
84			`l.nop`
85			`l.nop`
86			`l.nop`
87			`l.nop`
88			`l.nop`
89	519	simons
90			`_ipfault_vector:`
91	970	simons	`l.addi r1,r1,-120`
92			`l.sw 0x1c(r1),r9`
93			`l.sw 0x20(r1),r10`
94			`l.movhi r9,hi(store_regs)`
95			`l.ori r9,r9,lo(store_regs)`
96	519	simons	`l.movhi r10,hi(_excpt_ipfault)`
97			`l.ori r10,r10,lo(_excpt_ipfault)`
98	970	simons	`l.jr r9`
99	519	simons	`l.nop`
100	970	simons	`l.nop`
101			`l.nop`
102			`l.nop`
103			`l.nop`
104			`l.nop`
105			`l.nop`
106			`l.nop`
107	519	simons
108	600	simons	`_tick_vector:`
109	970	simons	`l.addi r1,r1,-120`
110			`l.sw 0x1c(r1),r9`
111			`l.sw 0x20(r1),r10`
112			`l.movhi r9,hi(store_regs)`
113			`l.ori r9,r9,lo(store_regs)`
114	600	simons	`l.movhi r10,hi(_excpt_tick)`
115			`l.ori r10,r10,lo(_excpt_tick)`
116	970	simons	`l.jr r9`
117	519	simons	`l.nop`
118	970	simons	`l.nop`
119			`l.nop`
120			`l.nop`
121			`l.nop`
122			`l.nop`
123			`l.nop`
124			`l.nop`
125	519	simons
126			`_align_vector:`
127	970	simons	`l.addi r1,r1,-120`
128			`l.sw 0x1c(r1),r9`
129			`l.sw 0x20(r1),r10`
130			`l.movhi r9,hi(store_regs)`
131			`l.ori r9,r9,lo(store_regs)`
132	519	simons	`l.movhi r10,hi(_excpt_align)`
133			`l.ori r10,r10,lo(_excpt_align)`
134	970	simons	`l.jr r9`
135	519	simons	`l.nop`
136	970	simons	`l.nop`
137			`l.nop`
138			`l.nop`
139			`l.nop`
140			`l.nop`
141			`l.nop`
142			`l.nop`
143	519	simons
144			`_illinsn_vector:`
145	970	simons	`l.addi r1,r1,-120`
146			`l.sw 0x1c(r1),r9`
147			`l.sw 0x20(r1),r10`
148			`l.movhi r9,hi(store_regs)`
149			`l.ori r9,r9,lo(store_regs)`
150	519	simons	`l.movhi r10,hi(_excpt_illinsn)`
151			`l.ori r10,r10,lo(_excpt_illinsn)`
152	970	simons	`l.jr r9`
153	519	simons	`l.nop`
154	970	simons	`l.nop`
155			`l.nop`
156			`l.nop`
157			`l.nop`
158			`l.nop`
159			`l.nop`
160			`l.nop`
161	519	simons
162	600	simons	`_int_vector:`
163	970	simons	`l.addi r1,r1,-120`
164			`l.sw 0x1c(r1),r9`
165			`l.sw 0x20(r1),r10`
166			`l.movhi r9,hi(store_regs)`
167			`l.ori r9,r9,lo(store_regs)`
168	600	simons	`l.movhi r10,hi(_excpt_int)`
169			`l.ori r10,r10,lo(_excpt_int)`
170	970	simons	`l.jr r9`
171	519	simons	`l.nop`
172	970	simons	`l.nop`
173			`l.nop`
174			`l.nop`
175			`l.nop`
176			`l.nop`
177			`l.nop`
178			`l.nop`
179	519	simons
180			`_dtlbmiss_vector:`
181	970	simons	`l.addi r1,r1,-120`
182			`l.sw 0x1c(r1),r9`
183			`l.sw 0x20(r1),r10`
184			`l.movhi r9,hi(store_regs)`
185			`l.ori r9,r9,lo(store_regs)`
186	519	simons	`l.movhi r10,hi(_excpt_dtlbmiss)`
187			`l.ori r10,r10,lo(_excpt_dtlbmiss)`
188	970	simons	`l.jr r9`
189	519	simons	`l.nop`
190	970	simons	`l.nop`
191			`l.nop`
192			`l.nop`
193			`l.nop`
194			`l.nop`
195			`l.nop`
196			`l.nop`
197	519	simons
198			`_itlbmiss_vector:`
199	970	simons	`l.addi r1,r1,-120`
200			`l.sw 0x1c(r1),r9`
201			`l.sw 0x20(r1),r10`
202			`l.movhi r9,hi(store_regs)`
203			`l.ori r9,r9,lo(store_regs)`
204	519	simons	`l.movhi r10,hi(_excpt_itlbmiss)`
205			`l.ori r10,r10,lo(_excpt_itlbmiss)`
206	970	simons	`l.jr r9`
207	519	simons	`l.nop`
208	970	simons	`l.nop`
209			`l.nop`
210			`l.nop`
211			`l.nop`
212			`l.nop`
213			`l.nop`
214			`l.nop`
215	519	simons
216			`_range_vector:`
217	970	simons	`l.addi r1,r1,-120`
218			`l.sw 0x1c(r1),r9`
219			`l.sw 0x20(r1),r10`
220			`l.movhi r9,hi(store_regs)`
221			`l.ori r9,r9,lo(store_regs)`
222	519	simons	`l.movhi r10,hi(_excpt_range)`
223			`l.ori r10,r10,lo(_excpt_range)`
224	970	simons	`l.jr r9`
225	519	simons	`l.nop`
226	970	simons	`l.nop`
227			`l.nop`
228			`l.nop`
229			`l.nop`
230			`l.nop`
231			`l.nop`
232			`l.nop`
233	519	simons
234			`_syscall_vector:`
235			`l.addi r3,r3,4`
236
237			`l.mfspr r4,r0,SPR_SR`
238			`l.andi r4,r4,7`
239			`l.add r6,r0,r4`
240
241			`l.mfspr r4,r0,SPR_EPCR_BASE`
242			`l.movhi r5,hi(_sys1)`
243			`l.ori r5,r5,lo(_sys1)`
244			`l.sub r5,r4,r5`
245
246			`l.mfspr r4,r0,SPR_ESR_BASE /* ESR - set supvisor mode */`
247	600	simons	`l.ori r4,r4,SPR_SR_SM`
248	519	simons	`l.mtspr r0,r4,SPR_ESR_BASE`
249
250			`l.movhi r4,hi(_sys2)`
251			`l.ori r4,r4,lo(_sys2)`
252			`l.mtspr r0,r4,SPR_EPCR_BASE`
253
254			`l.rfe`
255			`l.addi r3,r3,8`
256
257			`_break_vector:`
258	970	simons	`l.addi r1,r1,-120`
259			`l.sw 0x1c(r1),r9`
260			`l.sw 0x20(r1),r10`
261			`l.movhi r9,hi(store_regs)`
262			`l.ori r9,r9,lo(store_regs)`
263			`l.movhi r10,hi(_excpt_break)`
264			`l.ori r10,r10,lo(_excpt_break)`
265			`l.jr r9`
266	519	simons	`l.nop`
267	970	simons	`l.nop`
268			`l.nop`
269			`l.nop`
270			`l.nop`
271			`l.nop`
272			`l.nop`
273			`l.nop`
274	519	simons
275	970	simons	`_trap_vector:`
276			`l.addi r1,r1,-120`
277			`l.sw 0x1c(r1),r9`
278			`l.sw 0x20(r1),r10`
279			`l.movhi r9,hi(store_regs)`
280			`l.ori r9,r9,lo(store_regs)`
281			`l.movhi r10,hi(_excpt_trap)`
282			`l.ori r10,r10,lo(_excpt_trap)`
283			`l.jr r9`
284			`l.nop`
285			`l.nop`
286			`l.nop`
287			`l.nop`
288			`l.nop`
289			`l.nop`
290			`l.nop`
291			`l.nop`
292	519	simons
293	970	simons	`.section .text`
294	519	simons
295	970	simons	`.org 0x100`
296			`_reset_vector:`
297	519	simons	`l.nop`
298	970	simons	`l.nop`
299			`l.addi r2,r0,0x0`
300			`l.addi r3,r0,0x0`
301			`l.addi r4,r0,0x0`
302			`l.addi r5,r0,0x0`
303			`l.addi r6,r0,0x0`
304			`l.addi r7,r0,0x0`
305			`l.addi r8,r0,0x0`
306			`l.addi r9,r0,0x0`
307			`l.addi r10,r0,0x0`
308			`l.addi r11,r0,0x0`
309			`l.addi r12,r0,0x0`
310			`l.addi r13,r0,0x0`
311			`l.addi r14,r0,0x0`
312			`l.addi r15,r0,0x0`
313			`l.addi r16,r0,0x0`
314			`l.addi r17,r0,0x0`
315			`l.addi r18,r0,0x0`
316			`l.addi r19,r0,0x0`
317			`l.addi r20,r0,0x0`
318			`l.addi r21,r0,0x0`
319			`l.addi r22,r0,0x0`
320			`l.addi r23,r0,0x0`
321			`l.addi r24,r0,0x0`
322			`l.addi r25,r0,0x0`
323			`l.addi r26,r0,0x0`
324			`l.addi r27,r0,0x0`
325			`l.addi r28,r0,0x0`
326			`l.addi r29,r0,0x0`
327			`l.addi r30,r0,0x0`
328			`l.addi r31,r0,0x0`
329	519	simons
330	970	simons	`l.movhi r3,hi(start)`
331			`l.ori r3,r3,lo(start)`
332			`l.jr r3`
333	519	simons	`l.nop`
334	970	simons	`start:`
335			`l.jal _init_mc`
336			`l.nop`
337	519	simons
338	970	simons	`l.movhi r1,hi(_stack)`
339			`l.ori r1,r1,lo(_stack)`
340
341			`/* Setup exception wrappers */`
342			`l.movhi r3,hi(_src_beg)`
343			`l.ori r3,r3,lo(_src_beg)`
344			`l.addi r7,r0,0x100`
345
346			`1: l.addi r7,r7,0x100`
347			`l.sfeqi r7,0xf00`
348			`l.bf 1f`
349			`l.nop`
350			`l.addi r4,r7,0`
351			`l.addi r5,r0,0`
352			`2:`
353			`l.lwz r6,0(r3)`
354			`l.sw 0(r4),r6`
355			`l.addi r3,r3,4`
356			`l.addi r4,r4,4`
357			`l.addi r5,r5,1`
358			`l.sfeqi r5,16`
359			`l.bf 1b`
360			`l.nop`
361			`l.j 2b`
362			`l.nop`
363			`1:`
364			`/* Copy data section */`
365			`l.movhi r4,hi(_dst_beg)`
366			`l.ori r4,r4,lo(_dst_beg)`
367			`l.movhi r5,hi(_dst_end)`
368			`l.ori r5,r5,lo(_dst_end)`
369			`l.sub r5,r5,r4`
370			`l.sfeqi r5,0`
371			`l.bf 2f`
372			`l.nop`
373			`1: l.lwz r6,0(r3)`
374			`l.sw 0(r4),r6`
375			`l.addi r3,r3,4`
376			`l.addi r4,r4,4`
377			`l.addi r5,r5,-4`
378			`l.sfgtsi r5,0`
379			`l.bf 1b`
380			`l.nop`
381
382			`2:`
383
384			`l.movhi r2,hi(reset)`
385			`l.ori r2,r2,lo(reset)`
386			`l.jr r2`
387			`l.nop`
388
389			`_init_mc:`
390
391			`l.movhi r3,hi(MC_BASE_ADDR)`
392			`l.ori r3,r3,lo(MC_BASE_ADDR)`
393
394			`l.addi r4,r3,MC_CSC(0)`
395			`l.movhi r5,hi(FLASH_BASE_ADDR)`
396			`l.srai r5,r5,6`
397			`l.ori r5,r5,0x0025`
398			`l.sw 0(r4),r5`
399
400			`l.addi r4,r3,MC_TMS(0)`
401			`l.movhi r5,hi(FLASH_TMS_VAL)`
402			`l.ori r5,r5,lo(FLASH_TMS_VAL)`
403			`l.sw 0(r4),r5`
404
405			`l.addi r4,r3,MC_BA_MASK`
406			`l.addi r5,r0,MC_MASK_VAL`
407			`l.sw 0(r4),r5`
408
409			`l.addi r4,r3,MC_CSR`
410			`l.movhi r5,hi(MC_CSR_VAL)`
411			`l.ori r5,r5,lo(MC_CSR_VAL)`
412			`l.sw 0(r4),r5`
413
414			`l.addi r4,r3,MC_TMS(1)`
415			`l.movhi r5,hi(SDRAM_TMS_VAL)`
416			`l.ori r5,r5,lo(SDRAM_TMS_VAL)`
417			`l.sw 0(r4),r5`
418
419			`l.addi r4,r3,MC_CSC(1)`
420			`l.movhi r5,hi(SDRAM_BASE_ADDR)`
421			`l.srai r5,r5,6`
422			`l.ori r5,r5,0x0411`
423			`l.sw 0(r4),r5`
424
425			`l.jr r9`
426			`l.nop`
427
428			`store_regs:`
429			`l.sw 0x00(r1),r2`
430			`l.sw 0x04(r1),r3`
431			`l.sw 0x08(r1),r4`
432			`l.sw 0x0c(r1),r5`
433			`l.sw 0x10(r1),r6`
434			`l.sw 0x14(r1),r7`
435			`l.sw 0x18(r1),r8`
436			`l.sw 0x24(r1),r11`
437			`l.sw 0x28(r1),r12`
438			`l.sw 0x2c(r1),r13`
439			`l.sw 0x30(r1),r14`
440			`l.sw 0x34(r1),r15`
441			`l.sw 0x38(r1),r16`
442			`l.sw 0x3c(r1),r17`
443			`l.sw 0x40(r1),r18`
444			`l.sw 0x44(r1),r19`
445			`l.sw 0x48(r1),r20`
446			`l.sw 0x4c(r1),r21`
447			`l.sw 0x50(r1),r22`
448			`l.sw 0x54(r1),r23`
449			`l.sw 0x58(r1),r24`
450			`l.sw 0x5c(r1),r25`
451			`l.sw 0x60(r1),r26`
452			`l.sw 0x64(r1),r27`
453			`l.sw 0x68(r1),r28`
454			`l.sw 0x6c(r1),r29`
455			`l.sw 0x70(r1),r30`
456			`l.sw 0x74(r1),r31`
457
458	519	simons	`l.mfspr r3,r0,SPR_EPCR_BASE`
459			`l.movhi r4,hi(_except_pc)`
460			`l.ori r4,r4,lo(_except_pc)`
461			`l.sw 0(r4),r3`
462
463			`l.mfspr r3,r0,SPR_EEAR_BASE`
464			`l.movhi r4,hi(_except_ea)`
465			`l.ori r4,r4,lo(_except_ea)`
466			`l.sw 0(r4),r3`
467
468			`l.movhi r9,hi(end_except)`
469			`l.ori r9,r9,lo(end_except)`
470	970	simons
471	519	simons	`l.lwz r10,0(r10)`
472			`l.jr r10`
473			`l.nop`
474
475			`end_except:`
476	970	simons	`l.lwz r2,0x00(r1)`
477			`l.lwz r3,0x04(r1)`
478			`l.lwz r4,0x08(r1)`
479			`l.lwz r5,0x0c(r1)`
480			`l.lwz r6,0x10(r1)`
481			`l.lwz r7,0x14(r1)`
482			`l.lwz r8,0x18(r1)`
483			`l.lwz r9,0x1c(r1)`
484			`l.lwz r10,0x20(r1)`
485			`l.lwz r11,0x24(r1)`
486			`l.lwz r12,0x28(r1)`
487			`l.lwz r13,0x2c(r1)`
488			`l.lwz r14,0x30(r1)`
489			`l.lwz r15,0x34(r1)`
490			`l.lwz r16,0x38(r1)`
491			`l.lwz r17,0x3c(r1)`
492			`l.lwz r18,0x40(r1)`
493			`l.lwz r19,0x44(r1)`
494			`l.lwz r20,0x48(r1)`
495			`l.lwz r21,0x4c(r1)`
496			`l.lwz r22,0x50(r1)`
497			`l.lwz r23,0x54(r1)`
498			`l.lwz r24,0x58(r1)`
499			`l.lwz r25,0x5c(r1)`
500			`l.lwz r26,0x60(r1)`

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