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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [bench/] [verilog/] [sram_init.v] - Blame information for rev 1782

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1 779 lampret
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  MP3 demo SRAM init                                          ////
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////                                                              ////
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////  This file is part of the MP3 demo application               ////
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////  http://www.opencores.org/cores/or1k/mp3/                    ////
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////                                                              ////
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////  Description                                                 ////
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////  Optional SRAM content initialization (for debugging         ////
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////  purposes)                                                   ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - nothing really                                           ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1  2001/11/04 18:51:07  lampret
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// First import.
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//
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//
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`ifdef SRAM_INIT
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module sram_init;
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reg [7:0] mem [135005:0];
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reg [31:0] tmp;
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task init_sram;
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integer i;
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begin
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        #1;
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        $display("Initializing SRAM ...");
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        $readmemh("../src/flash.in", mem);
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        for (i=0; i < 135000; i=i+4) begin
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                xess_top.Sram_r1.mem_array[i/4] = mem[i];
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                xess_top.Sram_r0.mem_array[i/4] = mem[i+1];
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                xess_top.Sram_l1.mem_array[i/4] = mem[i+2];
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                xess_top.Sram_l0.mem_array[i/4] = mem[i+3];
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        end
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`ifdef UNUSED
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        for (i=0; i < 135000; i=i+4) begin
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                tmp[31:24] = xess_top.Sram_r1.temp_array[i/4];
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                tmp[23:16] = xess_top.Sram_r0.temp_array[i/4];
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                tmp[15:8] = xess_top.Sram_l1.temp_array[i/4];
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                tmp[7:0] = xess_top.Sram_l0.temp_array[i/4];
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                $display("%h %h", i, tmp);
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                tmp[31:24] = xess_top.Sram_r1.mem_array[i/4];
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                tmp[23:16] = xess_top.Sram_r0.mem_array[i/4];
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                tmp[15:8] = xess_top.Sram_l1.mem_array[i/4];
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                tmp[7:0] = xess_top.Sram_l0.mem_array[i/4];
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                $display("%h %h", i, tmp);
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        end
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`endif
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end
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endtask
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endmodule
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`endif

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