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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [audio/] [audio_codec_if.v] - Blame information for rev 1765

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Line No. Rev Author Line
1 746 lampret
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  MP3 demo Audio CODEC interface                              ////
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////                                                              ////
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////  This file is part of the MP3 demo application               ////
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////  http://www.opencores.org/cores/or1k/mp3/                    ////
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////                                                              ////
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////  Description                                                 ////
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////  Connects Audio block to XSV board AK4520 codec chip.        ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - nothing really                                           ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Lior Shtram, lior.shtram@flextronicssemi.com          ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1.1.1  2001/11/04 19:00:08  lampret
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// First import.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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module audio_codec_if (
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  rstn,
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  clk,
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  fifo_clk,
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  fifo_data,
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  fifo_rd_en,
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  sclk,
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  mclk,
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  lrclk,
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  sdout,
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  sdin
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);
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parameter fifo_width = 16;
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parameter count_bits = 11;
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input   rstn;
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input   clk;
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output  fifo_clk;
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input [fifo_width-1:0]  fifo_data;
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output    fifo_rd_en;
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output    sclk;
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output    mclk;
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output    lrclk;
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input   sdout;
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output    sdin;
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reg [count_bits-1:0]  counter;
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reg [16:0]  shift_reg;
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reg     f_rd_en;
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reg     sd_sig;
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always @(posedge clk or negedge rstn)
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begin
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  if(!rstn)
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    counter <= 0;
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  else
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    counter <= #1 counter + 1;
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end
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assign fifo_clk = clk ;
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assign fifo_rd_en = f_rd_en ;
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assign mclk = counter[0]; // mclk = clk/2 = 256fs
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assign sclk = counter[2]; // sclk = mclk/4 = 64fs
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assign lrclk = counter[8]; //lrclk = sclk/64
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always @(posedge clk or negedge rstn)
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begin
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  if(!rstn)
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    begin
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      sd_sig <= 1'b0;
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      shift_reg <= 0;
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    end
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  else
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    begin
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      if(counter[7:3] < 5'd16)
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        begin
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          if( counter[2:0] == 3'b101)
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            shift_reg[fifo_width:1] <= #1 shift_reg[fifo_width-1:0];
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          else
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            shift_reg <= #1 shift_reg;
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          sd_sig <= #1 shift_reg[16];
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        end
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      else
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        begin
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          sd_sig <= #1 1'b0;
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          if(counter[7:0] == 8'h80)
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            shift_reg[16:0] <= { fifo_data[fifo_width-1:0], 1'b0 };
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        end
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    end
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end
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// To je nase. Sve ostalo je garbidz.
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always @(posedge clk or negedge rstn)
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begin
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  if(!rstn)
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    f_rd_en <= 1'b0;
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  else
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  if(counter[9:0] == 10'h200)
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    f_rd_en <= #1 1'b1;
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  else
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    f_rd_en <= #1 1'b0;
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end
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assign sdin = sd_sig;
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endmodule

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