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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [audio/] [audio_codec_if.v] - Blame information for rev 1765

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  MP3 demo Audio CODEC interface                              ////
////                                                              ////
////  This file is part of the MP3 demo application               ////
////  http://www.opencores.org/cores/or1k/mp3/                    ////
////                                                              ////
////  Description                                                 ////
////  Connects Audio block to XSV board AK4520 codec chip.        ////
////                                                              ////
////  To Do:                                                      ////
////   - nothing really                                           ////
////                                                              ////
////  Author(s):                                                  ////
////      - Lior Shtram, lior.shtram@flextronicssemi.com          ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2001/11/04 19:00:08  lampret
// First import.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module audio_codec_if (
  rstn,
  clk,
  fifo_clk,
  fifo_data,
  fifo_rd_en,
 
  sclk,
  mclk,
  lrclk,
  sdout,
  sdin
);
 
parameter fifo_width = 16;
parameter count_bits = 11;
 
input   rstn;
input   clk;
output  fifo_clk;
input [fifo_width-1:0]  fifo_data;
output    fifo_rd_en;
 
output    sclk;
output    mclk;
output    lrclk;
input   sdout;
output    sdin;
 
 
reg [count_bits-1:0]  counter;
reg [16:0]  shift_reg;
reg     f_rd_en;
reg     sd_sig;
 
always @(posedge clk or negedge rstn)
begin
  if(!rstn)
    counter <= 0;
  else
    counter <= #1 counter + 1;
end
 
assign fifo_clk = clk ;
assign fifo_rd_en = f_rd_en ;
assign mclk = counter[0]; // mclk = clk/2 = 256fs
assign sclk = counter[2]; // sclk = mclk/4 = 64fs
assign lrclk = counter[8]; //lrclk = sclk/64
 
always @(posedge clk or negedge rstn)
begin
  if(!rstn)
    begin
      sd_sig <= 1'b0;
      shift_reg <= 0;
    end
  else
    begin
      if(counter[7:3] < 5'd16)
        begin
          if( counter[2:0] == 3'b101)
            shift_reg[fifo_width:1] <= #1 shift_reg[fifo_width-1:0];
          else
            shift_reg <= #1 shift_reg;
          sd_sig <= #1 shift_reg[16];
        end
      else
        begin
          sd_sig <= #1 1'b0;
          if(counter[7:0] == 8'h80)
            shift_reg[16:0] <= { fifo_data[fifo_width-1:0], 1'b0 };
        end
    end
end
 
// To je nase. Sve ostalo je garbidz.
always @(posedge clk or negedge rstn)
begin
  if(!rstn)
    f_rd_en <= 1'b0;
  else
  if(counter[9:0] == 10'h200)
    f_rd_en <= #1 1'b1;
  else
    f_rd_en <= #1 1'b0;
end
 
 
assign sdin = sd_sig;
 
 
endmodule

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// MP3 demo Audio CODEC interface ////`
4			`//// ////`
5			`//// This file is part of the MP3 demo application ////`
6			`//// http://www.opencores.org/cores/or1k/mp3/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Connects Audio block to XSV board AK4520 codec chip. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - nothing really ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Lior Shtram, lior.shtram@flextronicssemi.com ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2001 Authors ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1.1.1 2001/11/04 19:00:08 lampret`
48			`// First import.`
49			`//`
50			`//`
51
52			`// synopsys translate_off`
53			`include "timescale.v"
54			`// synopsys translate_on`
55
56			`module audio_codec_if (`
57			`rstn,`
58			`clk,`
59			`fifo_clk,`
60			`fifo_data,`
61			`fifo_rd_en,`
62
63			`sclk,`
64			`mclk,`
65			`lrclk,`
66			`sdout,`
67			`sdin`
68			`);`
69
70			`parameter fifo_width = 16;`
71			`parameter count_bits = 11;`
72
73			`input rstn;`
74			`input clk;`
75			`output fifo_clk;`
76			`input [fifo_width-1:0] fifo_data;`
77			`output fifo_rd_en;`
78
79			`output sclk;`
80			`output mclk;`
81			`output lrclk;`
82			`input sdout;`
83			`output sdin;`
84
85
86			`reg [count_bits-1:0] counter;`
87			`reg [16:0] shift_reg;`
88			`reg f_rd_en;`
89			`reg sd_sig;`
90
91			`always @(posedge clk or negedge rstn)`
92			`begin`
93			`if(!rstn)`
94			`counter <= 0;`
95			`else`
96			`counter <= #1 counter + 1;`
97			`end`
98
99			`assign fifo_clk = clk ;`
100			`assign fifo_rd_en = f_rd_en ;`
101			`assign mclk = counter[0]; // mclk = clk/2 = 256fs`
102			`assign sclk = counter[2]; // sclk = mclk/4 = 64fs`
103			`assign lrclk = counter[8]; //lrclk = sclk/64`
104
105			`always @(posedge clk or negedge rstn)`
106			`begin`
107			`if(!rstn)`
108			`begin`
109			`sd_sig <= 1'b0;`
110			`shift_reg <= 0;`
111			`end`
112			`else`
113			`begin`
114			`if(counter[7:3] < 5'd16)`
115			`begin`
116			`if( counter[2:0] == 3'b101)`
117			`shift_reg[fifo_width:1] <= #1 shift_reg[fifo_width-1:0];`
118			`else`
119			`shift_reg <= #1 shift_reg;`
120			`sd_sig <= #1 shift_reg[16];`
121			`end`
122			`else`
123			`begin`
124			`sd_sig <= #1 1'b0;`
125			`if(counter[7:0] == 8'h80)`
126			`shift_reg[16:0] <= { fifo_data[fifo_width-1:0], 1'b0 };`
127			`end`
128			`end`
129			`end`
130
131			`// To je nase. Sve ostalo je garbidz.`
132			`always @(posedge clk or negedge rstn)`
133			`begin`
134			`if(!rstn)`
135			`f_rd_en <= 1'b0;`
136			`else`
137			`if(counter[9:0] == 10'h200)`
138			`f_rd_en <= #1 1'b1;`
139			`else`
140			`f_rd_en <= #1 1'b0;`
141			`end`
142
143
144			`assign sdin = sd_sig;`
145
146
147			`endmodule`

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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [audio/] [audio_codec_if.v] - Blame information for rev 1765