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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [dbg_interface/] [timescale.v] - Blame information for rev 1765

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  timescale.v                                                 ////
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////                                                              ////
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////                                                              ////
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////  This file is part of the SoC/OpenRISC Development Interface ////
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////  http://www.opencores.org/cores/DebugInterface/              ////
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////                                                              ////
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////                                                              ////
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////  Author(s):                                                  ////
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////       Igor Mohor                                             ////
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////       igorm@opencores.org                                    ////
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////                                                              ////
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////                                                              ////
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////  All additional information is avaliable in the README.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000,2001 Authors                              ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1  2001/10/19 11:40:01  mohor
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// dbg_timescale.v changed to timescale.v This is done for the simulation of
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// few different cores in a single project.
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//
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// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
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// Initial official release.
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//
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//
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//
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//
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//
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`timescale 1ns / 1ns

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