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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [ethernet.old/] [eth_registers.v] - Blame information for rev 1765

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_registers.v                                             ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
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////  http://www.opencores.org/projects/ethmac/                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
40
//
41
// CVS Revision History
42
//
43
// $Log: not supported by cvs2svn $
44
// Revision 1.13  2002/02/26 16:18:09  mohor
45
// Reset values are passed to registers through parameters
46
//
47
// Revision 1.12  2002/02/17 13:23:42  mohor
48
// Define missmatch fixed.
49
//
50
// Revision 1.11  2002/02/16 14:03:44  mohor
51
// Registered trimmed. Unused registers removed.
52
//
53
// Revision 1.10  2002/02/15 11:08:25  mohor
54
// File format fixed a bit.
55
//
56
// Revision 1.9  2002/02/14 20:19:41  billditt
57
// Modified for Address Checking,
58
// addition of eth_addrcheck.v
59
//
60
// Revision 1.8  2002/02/12 17:01:19  mohor
61
// HASH0 and HASH1 registers added. 
62
 
63
// Revision 1.7  2002/01/23 10:28:16  mohor
64
// Link in the header changed.
65
//
66
// Revision 1.6  2001/12/05 15:00:16  mohor
67
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
68
// instead of the number of RX descriptors).
69
//
70
// Revision 1.5  2001/12/05 10:22:19  mohor
71
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
72
//
73
// Revision 1.4  2001/10/19 08:43:51  mohor
74
// eth_timescale.v changed to timescale.v This is done because of the
75
// simulation of the few cores in a one joined project.
76
//
77
// Revision 1.3  2001/10/18 12:07:11  mohor
78
// Status signals changed, Adress decoding changed, interrupt controller
79
// added.
80
//
81
// Revision 1.2  2001/09/24 15:02:56  mohor
82
// Defines changed (All precede with ETH_). Small changes because some
83
// tools generate warnings when two operands are together. Synchronization
84
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
85
// demands).
86
//
87
// Revision 1.1  2001/08/06 14:44:29  mohor
88
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
89
// Include files fixed to contain no path.
90
// File names and module names changed ta have a eth_ prologue in the name.
91
// File eth_timescale.v is used to define timescale
92
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
93
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
94
// and Mdo_OE. The bidirectional signal must be created on the top level. This
95
// is done due to the ASIC tools.
96
//
97
// Revision 1.2  2001/08/02 09:25:31  mohor
98
// Unconnected signals are now connected.
99
//
100
// Revision 1.1  2001/07/30 21:23:42  mohor
101
// Directory structure changed. Files checked and joind together.
102
//
103
//
104
//
105
//
106
//
107
//
108
 
109
`include "eth_defines.v"
110
`include "timescale.v"
111
 
112
 
113
module eth_registers( DataIn, Address, Rw, Cs, Clk, Reset, DataOut,
114
                      r_RecSmall, r_Pad, r_HugEn, r_CrcEn, r_DlyCrcEn,
115
                      r_Rst, r_FullD, r_ExDfrEn, r_NoBckof, r_LoopBck, r_IFG,
116
                      r_Pro, r_Iam, r_Bro, r_NoPre, r_TxEn, r_RxEn,
117
                      TxB_IRQ, TxE_IRQ, RxB_IRQ, RxE_IRQ, Busy_IRQ, TxC_IRQ, RxC_IRQ,
118
                      r_IPGT, r_IPGR1, r_IPGR2, r_MinFL, r_MaxFL, r_MaxRet,
119
                      r_CollValid, r_TxFlow, r_RxFlow, r_PassAll,
120
                      r_MiiMRst, r_MiiNoPre, r_ClkDiv, r_WCtrlData, r_RStat, r_ScanStat,
121
                      r_RGAD, r_FIAD, r_CtrlData, NValid_stat, Busy_stat,
122
                      LinkFail, r_MAC, WCtrlDataStart, RStatStart,
123
                      UpdateMIIRX_DATAReg, Prsd, r_TxBDNum, TX_BD_NUM_Wr, int_o,
124
                      r_HASH0, r_HASH1
125
                    );
126
 
127
parameter Tp = 1;
128
 
129
input [31:0] DataIn;
130
input [7:0] Address;
131
 
132
input Rw;
133
input Cs;
134
input Clk;
135
input Reset;
136
 
137
input WCtrlDataStart;
138
input RStatStart;
139
 
140
input UpdateMIIRX_DATAReg;
141
input [15:0] Prsd;
142
 
143
output [31:0] DataOut;
144
reg    [31:0] DataOut;
145
 
146
output r_RecSmall;
147
output r_Pad;
148
output r_HugEn;
149
output r_CrcEn;
150
output r_DlyCrcEn;
151
output r_Rst;
152
output r_FullD;
153
output r_ExDfrEn;
154
output r_NoBckof;
155
output r_LoopBck;
156
output r_IFG;
157
output r_Pro;
158
output r_Iam;
159
output r_Bro;
160
output r_NoPre;
161
output r_TxEn;
162
output r_RxEn;
163
output [31:0] r_HASH0;
164
output [31:0] r_HASH1;
165
 
166
input TxB_IRQ;
167
input TxE_IRQ;
168
input RxB_IRQ;
169
input RxE_IRQ;
170
input Busy_IRQ;
171
input TxC_IRQ;
172
input RxC_IRQ;
173
 
174
output [6:0] r_IPGT;
175
 
176
output [6:0] r_IPGR1;
177
 
178
output [6:0] r_IPGR2;
179
 
180
output [15:0] r_MinFL;
181
output [15:0] r_MaxFL;
182
 
183
output [3:0] r_MaxRet;
184
output [5:0] r_CollValid;
185
 
186
output r_TxFlow;
187
output r_RxFlow;
188
output r_PassAll;
189
 
190
output r_MiiMRst;
191
output r_MiiNoPre;
192
output [7:0] r_ClkDiv;
193
 
194
output r_WCtrlData;
195
output r_RStat;
196
output r_ScanStat;
197
 
198
output [4:0] r_RGAD;
199
output [4:0] r_FIAD;
200
 
201
output [15:0]r_CtrlData;
202
 
203
 
204
input NValid_stat;
205
input Busy_stat;
206
input LinkFail;
207
 
208
output [47:0]r_MAC;
209
output [7:0] r_TxBDNum;
210
output       TX_BD_NUM_Wr;
211
output       int_o;
212
 
213
reg          irq_txb;
214
reg          irq_txe;
215
reg          irq_rxb;
216
reg          irq_rxe;
217
reg          irq_busy;
218
reg          irq_txc;
219
reg          irq_rxc;
220
 
221
wire Write = Cs &  Rw;
222
wire Read  = Cs & ~Rw;
223
 
224
wire MODER_Wr       = (Address == `ETH_MODER_ADR       )  & Write;
225
wire INT_SOURCE_Wr  = (Address == `ETH_INT_SOURCE_ADR  )  & Write;
226
wire INT_MASK_Wr    = (Address == `ETH_INT_MASK_ADR    )  & Write;
227
wire IPGT_Wr        = (Address == `ETH_IPGT_ADR        )  & Write;
228
wire IPGR1_Wr       = (Address == `ETH_IPGR1_ADR       )  & Write;
229
wire IPGR2_Wr       = (Address == `ETH_IPGR2_ADR       )  & Write;
230
wire PACKETLEN_Wr   = (Address == `ETH_PACKETLEN_ADR   )  & Write;
231
wire COLLCONF_Wr    = (Address == `ETH_COLLCONF_ADR    )  & Write;
232
 
233
wire CTRLMODER_Wr   = (Address == `ETH_CTRLMODER_ADR   )  & Write;
234
wire MIIMODER_Wr    = (Address == `ETH_MIIMODER_ADR    )  & Write;
235
wire MIICOMMAND_Wr  = (Address == `ETH_MIICOMMAND_ADR  )  & Write;
236
wire MIIADDRESS_Wr  = (Address == `ETH_MIIADDRESS_ADR  )  & Write;
237
wire MIITX_DATA_Wr  = (Address == `ETH_MIITX_DATA_ADR  )  & Write;
238
wire MIIRX_DATA_Wr  = UpdateMIIRX_DATAReg;
239
wire MIISTATUS_Wr   = (Address == `ETH_MIISTATUS_ADR   )  & Write;
240
wire MAC_ADDR0_Wr   = (Address == `ETH_MAC_ADDR0_ADR   )  & Write;
241
wire MAC_ADDR1_Wr   = (Address == `ETH_MAC_ADDR1_ADR   )  & Write;
242
wire HASH0_Wr       = (Address == `ETH_HASH0_ADR   )  & Write;
243
wire HASH1_Wr       = (Address == `ETH_HASH1_ADR   )  & Write;
244
assign TX_BD_NUM_Wr = (Address == `ETH_TX_BD_NUM_ADR   )  & Write;
245
 
246
 
247
 
248
wire [31:0] MODEROut;
249
wire [31:0] INT_SOURCEOut;
250
wire [31:0] INT_MASKOut;
251
wire [31:0] IPGTOut;
252
wire [31:0] IPGR1Out;
253
wire [31:0] IPGR2Out;
254
wire [31:0] PACKETLENOut;
255
wire [31:0] COLLCONFOut;
256
wire [31:0] CTRLMODEROut;
257
wire [31:0] MIIMODEROut;
258
wire [31:0] MIICOMMANDOut;
259
wire [31:0] MIIADDRESSOut;
260
wire [31:0] MIITX_DATAOut;
261
wire [31:0] MIIRX_DATAOut;
262
wire [31:0] MIISTATUSOut;
263
wire [31:0] MAC_ADDR0Out;
264
wire [31:0] MAC_ADDR1Out;
265
wire [31:0] TX_BD_NUMOut;
266
wire [31:0] HASH0Out;
267
wire [31:0] HASH1Out;
268
 
269
 
270
eth_register #(17, `ETH_MODER_DEF)      MODER        (.DataIn(DataIn[16:0]), .DataOut(MODEROut[16:0]),     .Write(MODER_Wr),      .Clk(Clk), .Reset(Reset));
271
assign MODEROut[31:17] = 0;
272
 
273
eth_register #(7, `ETH_INT_MASK_DEF)     INT_MASK    (.DataIn(DataIn[6:0]),  .DataOut(INT_MASKOut[6:0]),   .Write(INT_MASK_Wr),   .Clk(Clk), .Reset(Reset));
274
assign INT_MASKOut[31:7] = 0;
275
 
276
eth_register #(7, `ETH_IPGT_DEF)         IPGT        (.DataIn(DataIn[6:0]),  .DataOut(IPGTOut[6:0]),       .Write(IPGT_Wr),       .Clk(Clk), .Reset(Reset));
277
assign IPGTOut[31:7] = 0;
278
 
279
eth_register #(7, `ETH_IPGR1_DEF)        IPGR1       (.DataIn(DataIn[6:0]),  .DataOut(IPGR1Out[6:0]),      .Write(IPGR1_Wr),      .Clk(Clk), .Reset(Reset));
280
assign IPGR1Out[31:7] = 0;
281
 
282
eth_register #(7, `ETH_IPGR2_DEF)        IPGR2       (.DataIn(DataIn[6:0]),  .DataOut(IPGR2Out[6:0]),      .Write(IPGR2_Wr),      .Clk(Clk), .Reset(Reset));
283
assign IPGR2Out[31:7] = 0;
284
 
285
eth_register #(32, `ETH_PACKETLEN_DEF)   PACKETLEN   (.DataIn(DataIn),       .DataOut(PACKETLENOut),       .Write(PACKETLEN_Wr),  .Clk(Clk), .Reset(Reset));
286
 
287
eth_register #(6, `ETH_COLLCONF0_DEF)    COLLCONF0   (.DataIn(DataIn[5:0]),  .DataOut(COLLCONFOut[5:0]),   .Write(COLLCONF_Wr),   .Clk(Clk), .Reset(Reset));
288
eth_register #(4, `ETH_COLLCONF1_DEF)    COLLCONF1   (.DataIn(DataIn[19:16]),.DataOut(COLLCONFOut[19:16]), .Write(COLLCONF_Wr),   .Clk(Clk), .Reset(Reset));
289
assign COLLCONFOut[15:6] = 0;
290
assign COLLCONFOut[31:20] = 0;
291
 
292
eth_register #(8, `ETH_TX_BD_NUM_DEF)    TX_BD_NUM   (.DataIn(DataIn[7:0]),  .DataOut(TX_BD_NUMOut[7:0]), .Write(TX_BD_NUM_Wr),  .Clk(Clk), .Reset(Reset));
293
assign TX_BD_NUMOut[31:8] = 24'h0;
294
 
295
eth_register #(3, `ETH_CTRLMODER_DEF)    CTRLMODER2  (.DataIn(DataIn[2:0]),  .DataOut(CTRLMODEROut[2:0]),  .Write(CTRLMODER_Wr),  .Clk(Clk), .Reset(Reset));
296
assign CTRLMODEROut[31:3] = 29'h0;
297
 
298
eth_register #(11, `ETH_MIIMODER_DEF)    MIIMODER    (.DataIn(DataIn[10:0]), .DataOut(MIIMODEROut[10:0]),  .Write(MIIMODER_Wr),   .Clk(Clk), .Reset(Reset));
299
assign MIIMODEROut[31:11] = 0;
300
 
301
eth_register #(1, 0)                     MIICOMMAND2 (.DataIn(DataIn[2]),    .DataOut(MIICOMMANDOut[2]),   .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | WCtrlDataStart));
302
eth_register #(1, 0)                     MIICOMMAND1 (.DataIn(DataIn[1]),    .DataOut(MIICOMMANDOut[1]),   .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | RStatStart));
303
eth_register #(1, 0)                     MIICOMMAND0 (.DataIn(DataIn[0]),    .DataOut(MIICOMMANDOut[0]),   .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset));
304
assign MIICOMMANDOut[31:3] = 29'h0;
305
 
306
eth_register #(5, `ETH_MIIADDRESS0_DEF)  MIIADDRESS0 (.DataIn(DataIn[4:0]),  .DataOut(MIIADDRESSOut[4:0]), .Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset));
307
eth_register #(5, `ETH_MIIADDRESS1_DEF)  MIIADDRESS1 (.DataIn(DataIn[12:8]), .DataOut(MIIADDRESSOut[12:8]),.Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset));
308
assign MIIADDRESSOut[7:5] = 0;
309
assign MIIADDRESSOut[31:13] = 0;
310
 
311
eth_register #(16, `ETH_MIITX_DATA_DEF)  MIITX_DATA  (.DataIn(DataIn[15:0]), .DataOut(MIITX_DATAOut[15:0]),.Write(MIITX_DATA_Wr), .Clk(Clk), .Reset(Reset));
312
assign MIITX_DATAOut[31:16] = 0;
313
 
314
eth_register #(16, `ETH_MIIRX_DATA_DEF)  MIIRX_DATA  (.DataIn(Prsd[15:0]),   .DataOut(MIIRX_DATAOut[15:0]),.Write(MIIRX_DATA_Wr), .Clk(Clk), .Reset(Reset));
315
assign MIIRX_DATAOut[31:16] = 0;
316
 
317
eth_register #(32, `ETH_MAC_ADDR0_DEF)   MAC_ADDR0   (.DataIn(DataIn),       .DataOut(MAC_ADDR0Out),       .Write(MAC_ADDR0_Wr),  .Clk(Clk), .Reset(Reset));
318
eth_register #(16, `ETH_MAC_ADDR1_DEF)   MAC_ADDR1   (.DataIn(DataIn[15:0]), .DataOut(MAC_ADDR1Out[15:0]), .Write(MAC_ADDR1_Wr),  .Clk(Clk), .Reset(Reset));
319
assign MAC_ADDR1Out[31:16] = 0;
320
 
321
 
322
eth_register #(32, `ETH_HASH0_DEF)       RXHASH0     (.DataIn(DataIn),       .DataOut(HASH0Out),           .Write(HASH0_Wr),      .Clk(Clk), .Reset(Reset));
323
eth_register #(32, `ETH_HASH1_DEF)       RXHASH1     (.DataIn(DataIn),       .DataOut(HASH1Out),           .Write(HASH1_Wr),      .Clk(Clk), .Reset(Reset));
324
 
325
 
326
reg LinkFailRegister;
327
wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read;
328
reg ResetLinkFailRegister_q1;
329
reg ResetLinkFailRegister_q2;
330
 
331
always @ (posedge Clk or posedge Reset)
332
begin
333
  if(Reset)
334
    begin
335
      LinkFailRegister <= #Tp 0;
336
      ResetLinkFailRegister_q1 <= #Tp 0;
337
      ResetLinkFailRegister_q2 <= #Tp 0;
338
    end
339
  else
340
    begin
341
      ResetLinkFailRegister_q1 <= #Tp ResetLinkFailRegister;
342
      ResetLinkFailRegister_q2 <= #Tp ResetLinkFailRegister_q1;
343
      if(LinkFail)
344
        LinkFailRegister <= #Tp 1;
345
      if(~ResetLinkFailRegister_q1 & ResetLinkFailRegister_q2)
346
        LinkFailRegister <= #Tp 0;
347
    end
348
end
349
 
350
 
351
always @ (Address or Read or MODEROut or INT_SOURCEOut or INT_MASKOut or IPGTOut or
352
          IPGR1Out or IPGR2Out or PACKETLENOut or COLLCONFOut or CTRLMODEROut or
353
          MIIMODEROut or MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or
354
          MIIRX_DATAOut or MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or
355
          TX_BD_NUMOut or HASH0Out or HASH1Out)
356
begin
357
  if(Read)  // read
358
    begin
359
      case(Address)
360
        `ETH_MODER_ADR        :  DataOut<=MODEROut;
361
        `ETH_INT_SOURCE_ADR   :  DataOut<=INT_SOURCEOut;
362
        `ETH_INT_MASK_ADR     :  DataOut<=INT_MASKOut;
363
        `ETH_IPGT_ADR         :  DataOut<=IPGTOut;
364
        `ETH_IPGR1_ADR        :  DataOut<=IPGR1Out;
365
        `ETH_IPGR2_ADR        :  DataOut<=IPGR2Out;
366
        `ETH_PACKETLEN_ADR    :  DataOut<=PACKETLENOut;
367
        `ETH_COLLCONF_ADR     :  DataOut<=COLLCONFOut;
368
        `ETH_CTRLMODER_ADR    :  DataOut<=CTRLMODEROut;
369
        `ETH_MIIMODER_ADR     :  DataOut<=MIIMODEROut;
370
        `ETH_MIICOMMAND_ADR   :  DataOut<=MIICOMMANDOut;
371
        `ETH_MIIADDRESS_ADR   :  DataOut<=MIIADDRESSOut;
372
        `ETH_MIITX_DATA_ADR   :  DataOut<=MIITX_DATAOut;
373
        `ETH_MIIRX_DATA_ADR   :  DataOut<=MIIRX_DATAOut;
374
        `ETH_MIISTATUS_ADR    :  DataOut<=MIISTATUSOut;
375
        `ETH_MAC_ADDR0_ADR    :  DataOut<=MAC_ADDR0Out;
376
        `ETH_MAC_ADDR1_ADR    :  DataOut<=MAC_ADDR1Out;
377
        `ETH_TX_BD_NUM_ADR    :  DataOut<=TX_BD_NUMOut;
378
        `ETH_HASH0_ADR        :  DataOut<=HASH0Out;
379
        `ETH_HASH1_ADR        :  DataOut<=HASH1Out;
380
        default:             DataOut<=32'h0;
381
      endcase
382
    end
383
  else
384
    DataOut<=32'h0;
385
end
386
 
387
 
388
assign r_RecSmall         = MODEROut[16];
389
assign r_Pad              = MODEROut[15];
390
assign r_HugEn            = MODEROut[14];
391
assign r_CrcEn            = MODEROut[13];
392
assign r_DlyCrcEn         = MODEROut[12];
393
assign r_Rst              = MODEROut[11];
394
assign r_FullD            = MODEROut[10];
395
assign r_ExDfrEn          = MODEROut[9];
396
assign r_NoBckof          = MODEROut[8];
397
assign r_LoopBck          = MODEROut[7];
398
assign r_IFG              = MODEROut[6];
399
assign r_Pro              = MODEROut[5];
400
assign r_Iam              = MODEROut[4];
401
assign r_Bro              = MODEROut[3];
402
assign r_NoPre            = MODEROut[2];
403
assign r_TxEn             = MODEROut[1];
404
assign r_RxEn             = MODEROut[0];
405
 
406
assign r_IPGT[6:0]        = IPGTOut[6:0];
407
 
408
assign r_IPGR1[6:0]       = IPGR1Out[6:0];
409
 
410
assign r_IPGR2[6:0]       = IPGR2Out[6:0];
411
 
412
assign r_MinFL[15:0]      = PACKETLENOut[31:16];
413
assign r_MaxFL[15:0]      = PACKETLENOut[15:0];
414
 
415
assign r_MaxRet[3:0]      = COLLCONFOut[19:16];
416
assign r_CollValid[5:0]   = COLLCONFOut[5:0];
417
 
418
assign r_TxFlow           = CTRLMODEROut[2];
419
assign r_RxFlow           = CTRLMODEROut[1];
420
assign r_PassAll          = CTRLMODEROut[0];
421
 
422
assign r_MiiMRst          = MIIMODEROut[10];
423
assign r_MiiNoPre         = MIIMODEROut[8];
424
assign r_ClkDiv[7:0]      = MIIMODEROut[7:0];
425
 
426
assign r_WCtrlData        = MIICOMMANDOut[2];
427
assign r_RStat            = MIICOMMANDOut[1];
428
assign r_ScanStat         = MIICOMMANDOut[0];
429
 
430
assign r_RGAD[4:0]        = MIIADDRESSOut[12:8];
431
assign r_FIAD[4:0]        = MIIADDRESSOut[4:0];
432
 
433
assign r_CtrlData[15:0]   = MIITX_DATAOut[15:0];
434
 
435
assign MIISTATUSOut[31:10] = 22'h0           ;
436
assign MIISTATUSOut[9]  = NValid_stat        ;
437
assign MIISTATUSOut[8]  = Busy_stat          ;
438
assign MIISTATUSOut[7:1]= 7'h0               ;
439
assign MIISTATUSOut[0]  = LinkFailRegister   ;
440
 
441
assign r_MAC[31:0]        = MAC_ADDR0Out[31:0];
442
assign r_MAC[47:32]       = MAC_ADDR1Out[15:0];
443
assign r_HASH1[31:0]      = HASH1Out;
444
assign r_HASH0[31:0]      = HASH0Out;
445
 
446
assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
447
 
448
 
449
// Interrupt generation
450
 
451
always @ (posedge Clk or posedge Reset)
452
begin
453
  if(Reset)
454
    irq_txb <= 1'b0;
455
  else
456
  if(TxB_IRQ & INT_MASKOut[0])
457
    irq_txb <= #Tp 1'b1;
458
  else
459
  if(INT_SOURCE_Wr & DataIn[0])
460
    irq_txb <= #Tp 1'b0;
461
end
462
 
463
always @ (posedge Clk or posedge Reset)
464
begin
465
  if(Reset)
466
    irq_txe <= 1'b0;
467
  else
468
  if(TxE_IRQ & INT_MASKOut[1])
469
    irq_txe <= #Tp 1'b1;
470
  else
471
  if(INT_SOURCE_Wr & DataIn[1])
472
    irq_txe <= #Tp 1'b0;
473
end
474
 
475
always @ (posedge Clk or posedge Reset)
476
begin
477
  if(Reset)
478
    irq_rxb <= 1'b0;
479
  else
480
  if(RxB_IRQ & INT_MASKOut[2])
481
    irq_rxb <= #Tp 1'b1;
482
  else
483
  if(INT_SOURCE_Wr & DataIn[2])
484
    irq_rxb <= #Tp 1'b0;
485
end
486
 
487
always @ (posedge Clk or posedge Reset)
488
begin
489
  if(Reset)
490
    irq_rxe <= 1'b0;
491
  else
492
  if(RxE_IRQ & INT_MASKOut[3])
493
    irq_rxe <= #Tp 1'b1;
494
  else
495
  if(INT_SOURCE_Wr & DataIn[3])
496
    irq_rxe <= #Tp 1'b0;
497
end
498
 
499
always @ (posedge Clk or posedge Reset)
500
begin
501
  if(Reset)
502
    irq_busy <= 1'b0;
503
  else
504
  if(Busy_IRQ & INT_MASKOut[4])
505
    irq_busy <= #Tp 1'b1;
506
  else
507
  if(INT_SOURCE_Wr & DataIn[4])
508
    irq_busy <= #Tp 1'b0;
509
end
510
 
511
always @ (posedge Clk or posedge Reset)
512
begin
513
  if(Reset)
514
    irq_txc <= 1'b0;
515
  else
516
  if(TxC_IRQ & INT_MASKOut[5])
517
    irq_txc <= #Tp 1'b1;
518
  else
519
  if(INT_SOURCE_Wr & DataIn[5])
520
    irq_txc <= #Tp 1'b0;
521
end
522
 
523
always @ (posedge Clk or posedge Reset)
524
begin
525
  if(Reset)
526
    irq_rxc <= 1'b0;
527
  else
528
  if(RxC_IRQ & INT_MASKOut[6])
529
    irq_rxc <= #Tp 1'b1;
530
  else
531
  if(INT_SOURCE_Wr & DataIn[6])
532
    irq_rxc <= #Tp 1'b0;
533
end
534
 
535
// Generating interrupt signal
536
assign int_o = irq_txb | irq_txe | irq_rxb | irq_rxe | irq_busy | irq_txc | irq_rxc;
537
 
538
// For reading interrupt status
539
assign INT_SOURCEOut = {26'h0, irq_rxc, irq_txc, irq_busy, irq_rxe, irq_rxb, irq_txe, irq_txb};
540
 
541
 
542
 
543
endmodule

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