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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_sync_clk1_clk2.v                                        ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects/ethmac/                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2002/01/23 10:28:16  mohor
// Link in the header changed.
//
// Revision 1.2  2001/10/19 08:43:51  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.1  2001/09/24 15:02:56  mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
//
//
//
// 
 
`include "timescale.v"
 
// FF in clock domain 1 is being set by a signal from the clock domain 2
module eth_sync_clk1_clk2 (clk1, clk2, reset1, reset2, set2, sync_out);
 
parameter   Tp = 1;
 
input   clk1;
input   clk2;
input   reset1;
input   reset2;
input   set2;
 
output  sync_out;
 
reg     set2_q;
reg     set2_q2;
reg     set1_q;
reg     set1_q2;
reg     clear2_q;
reg     clear2_q2;
reg     sync_out;
 
wire    z;
 
assign z = set2 | set2_q & ~clear2_q2;
 
 
// Latching and synchronizing "set" to clk2
always @ (posedge clk2 or posedge reset2)
begin
  if(reset2)
    set2_q <=#Tp 1'b0;
  else
    set2_q <=#Tp z;
end
 
 
always @ (posedge clk2 or posedge reset2)
begin
  if(reset2)
    set2_q2 <=#Tp 1'b0;
  else
    set2_q2 <=#Tp set2_q;
end
 
 
// Synchronizing "set" to clk1
always @ (posedge clk1 or posedge reset1)
begin
  if(reset1)
    set1_q <=#Tp 1'b0;
  else
    set1_q <=#Tp set2_q2;
end
 
 
always @ (posedge clk1 or posedge reset1)
begin
  if(reset1)
    set1_q2 <=#Tp 1'b0;
  else
    set1_q2 <=#Tp set1_q;
end
 
 
// Synchronizing "clear" to clk2
always @ (posedge clk2 or posedge reset2)
begin
  if(reset2)
    clear2_q <=#Tp 1'b0;
  else
    clear2_q <=#Tp set1_q2;
end
 
 
always @ (posedge clk2 or posedge reset2)
begin
  if(reset2)
    clear2_q2 <=#Tp 1'b0;
  else
    clear2_q2 <=#Tp clear2_q;
end
 
 
always @ (posedge clk1 or posedge reset1)
begin
  if(reset1)
    sync_out <=#Tp 1'b0;
  else
    sync_out <=#Tp set1_q2;
end
 
endmodule

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_sync_clk1_clk2.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6			`//// http://www.opencores.org/projects/ethmac/ ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is avaliable in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43			`// $Log: not supported by cvs2svn $`
44			`// Revision 1.3 2002/01/23 10:28:16 mohor`
45			`// Link in the header changed.`
46			`//`
47			`// Revision 1.2 2001/10/19 08:43:51 mohor`
48			`// eth_timescale.v changed to timescale.v This is done because of the`
49			`// simulation of the few cores in a one joined project.`
50			`//`
51			`// Revision 1.1 2001/09/24 15:02:56 mohor`
52			`// Defines changed (All precede with ETH_). Small changes because some`
53			`// tools generate warnings when two operands are together. Synchronization`
54			`// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC`
55			`// demands).`
56			`//`
57			`//`
58			`//`
59			`//`
60			`//`
61
62			`include "timescale.v"
63
64			`// FF in clock domain 1 is being set by a signal from the clock domain 2`
65			`module eth_sync_clk1_clk2 (clk1, clk2, reset1, reset2, set2, sync_out);`
66
67			`parameter Tp = 1;`
68
69			`input clk1;`
70			`input clk2;`
71			`input reset1;`
72			`input reset2;`
73			`input set2;`
74
75			`output sync_out;`
76
77			`reg set2_q;`
78			`reg set2_q2;`
79			`reg set1_q;`
80			`reg set1_q2;`
81			`reg clear2_q;`
82			`reg clear2_q2;`
83			`reg sync_out;`
84
85			`wire z;`
86
87			`assign z = set2 \| set2_q & ~clear2_q2;`
88
89
90			`// Latching and synchronizing "set" to clk2`
91			`always @ (posedge clk2 or posedge reset2)`
92			`begin`
93			`if(reset2)`
94			`set2_q <=#Tp 1'b0;`
95			`else`
96			`set2_q <=#Tp z;`
97			`end`
98
99
100			`always @ (posedge clk2 or posedge reset2)`
101			`begin`
102			`if(reset2)`
103			`set2_q2 <=#Tp 1'b0;`
104			`else`
105			`set2_q2 <=#Tp set2_q;`
106			`end`
107
108
109			`// Synchronizing "set" to clk1`
110			`always @ (posedge clk1 or posedge reset1)`
111			`begin`
112			`if(reset1)`
113			`set1_q <=#Tp 1'b0;`
114			`else`
115			`set1_q <=#Tp set2_q2;`
116			`end`
117
118
119			`always @ (posedge clk1 or posedge reset1)`
120			`begin`
121			`if(reset1)`
122			`set1_q2 <=#Tp 1'b0;`
123			`else`
124			`set1_q2 <=#Tp set1_q;`
125			`end`
126
127
128			`// Synchronizing "clear" to clk2`
129			`always @ (posedge clk2 or posedge reset2)`
130			`begin`
131			`if(reset2)`
132			`clear2_q <=#Tp 1'b0;`
133			`else`
134			`clear2_q <=#Tp set1_q2;`
135			`end`
136
137
138			`always @ (posedge clk2 or posedge reset2)`
139			`begin`
140			`if(reset2)`
141			`clear2_q2 <=#Tp 1'b0;`
142			`else`
143			`clear2_q2 <=#Tp clear2_q;`
144			`end`
145
146
147			`always @ (posedge clk1 or posedge reset1)`
148			`begin`
149			`if(reset1)`
150			`sync_out <=#Tp 1'b0;`
151			`else`
152			`sync_out <=#Tp set1_q2;`
153			`end`
154
155			`endmodule`

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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [ethernet.old/] [eth_sync_clk1_clk2.v] - Blame information for rev 1765