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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [mem_if/] [flash_top.v] - Blame information for rev 1765

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  XESS Flash interface                                        ////
////                                                              ////
////  This file is part of the OR1K test application              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Connects the SoC to the Flash found on XSV board. It also   ////
////  implements a generic flash model for simulations.           ////
////                                                              ////
////  To Do:                                                      ////
////   - nothing really                                           ////
////                                                              ////
////  Author(s):                                                  ////
////      - Lior Shtram, lior.shtram@flextronicssemi.com          ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2002/08/14 06:24:43  lampret
// Fixed size of generic flash/sram to exactly 2MB
//
// Revision 1.2  2002/08/12 05:33:50  lampret
// Changed logic when FLASH_GENERIC_REGISTERED
//
// Revision 1.1.1.1  2002/03/21 16:55:44  lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.4  2002/02/11 04:41:01  lampret
// Allow flash writes. Ugly workaround for something else...
//
// Revision 1.3  2002/01/23 07:50:44  lampret
// Added wb_err_o to flash and sram i/f for testing the buserr exception.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1.1.1  2001/11/04 19:00:09  lampret
// First import.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
//`include "bench_define.v"
 
`ifdef FLASH_GENERIC
 
module flash_top (
  wb_clk_i, wb_rst_i,
 
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
  wb_stb_i, wb_ack_o, wb_err_o,
 
  flash_rstn, cen, oen, wen, rdy, d, a, a_oe
);
 
//
// I/O Ports
//
 
//
// Common WB signals
//
input                   wb_clk_i;
input                   wb_rst_i;
 
//
// WB slave i/f
//
input   [31:0]           wb_dat_i;
output  [31:0]           wb_dat_o;
input   [31:0]           wb_adr_i;
input   [3:0]            wb_sel_i;
input                   wb_we_i;
input                   wb_cyc_i;
input                   wb_stb_i;
output                  wb_ack_o;
output                  wb_err_o;
 
//
// Flash i/f
//
output                  flash_rstn;
output                  oen;
output                  cen;
output                  wen;
input                   rdy;
inout   [7:0]            d;
output  [20:0]           a;
output                  a_oe;
 
//
// Internal wires and regs
//
reg     [7:0]            mem [2097151:0];
wire    [31:0]           adr;
`ifdef FLASH_GENERIC_REGISTERED
reg                     wb_err_o;
reg     [31:0]           prev_adr;
reg     [1:0]            delay;
`else
wire    [1:0]            delay;
`endif
wire                    wb_err;
 
//
// Aliases and simple assignments
//
assign flash_rstn = 1'b1;
assign oen = 1'b1;
assign cen = 1'b1;
assign wen = 1'b1;
assign a = 21'b0;
assign a_oe = 1'b1;
assign wb_err = wb_cyc_i & wb_stb_i & (delay == 2'd0) & (|wb_adr_i[23:21]);     // If Access to > 2MB (8-bit leading prefix ignored)
assign adr = {8'h00, wb_adr_i[23:2], 2'b00};
 
//
// For simulation only
//
initial $readmemh("../src/flash.in", mem, 0);
 
//
// Reading from flash model
//
assign wb_dat_o[7:0] = wb_adr_i[23:0] < 65535 ? mem[adr+3] : 8'h00;
assign wb_dat_o[15:8] = wb_adr_i[23:0] < 65535 ? mem[adr+2] : 8'h00;
assign wb_dat_o[23:16] = wb_adr_i[23:0] < 65535 ? mem[adr+1] : 8'h00;
assign wb_dat_o[31:24] = wb_adr_i[23:0] < 65535 ? mem[adr+0] : 8'h00;
 
 
`ifdef FLASH_GENERIC_REGISTERED
//
// WB Acknowledge
//
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i) begin
                delay <= #1 2'd3;
                prev_adr <= #1 32'h0000_0000;
        end
        else if (delay && (wb_adr_i == prev_adr) && wb_cyc_i && wb_stb_i)
                delay <= #1 delay - 2'd1;
        else if (wb_ack_o || wb_err_o || (wb_adr_i != prev_adr) || ~wb_stb_i) begin
                delay <= #1 2'd0;       // delay ... can range from 3 to 0
                prev_adr <= #1 wb_adr_i;
        end
`else
assign delay = 2'd0;
`endif
 
assign wb_ack_o = wb_cyc_i & wb_stb_i & ~wb_err & (delay == 2'd0)
`ifdef FLASH_GENERIC_REGISTERED
        & (wb_adr_i == prev_adr)
`endif
        ;
 
`ifdef FLASH_GENERIC_REGISTERED
//
// WB Error
//
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_err_o <= #1 1'b0;
        else
                wb_err_o <= #1 wb_err & !wb_err_o;
`else
assign wb_err_o = wb_err;
`endif
 
//
// Flash i/f monitor
//
// synopsys translate_off
integer fflash;
initial fflash = $fopen("flash.log");
always @(posedge wb_clk_i)
        if (wb_cyc_i)
                if (wb_stb_i & wb_we_i) begin
//                      $fdisplay(fflash, "%t Trying to write into flash at %h (%b)", $time, wb_adr_i, wb_we_i);
//                      #100 $finish;
                        if (wb_sel_i[3])
                                mem[{wb_adr_i[23:2], 2'b00}+0] = wb_dat_i[31:24];
                        if (wb_sel_i[2])
                                mem[{wb_adr_i[23:2], 2'b00}+1] = wb_dat_i[23:16];
                        if (wb_sel_i[1])
                                mem[{wb_adr_i[23:2], 2'b00}+2] = wb_dat_i[15:8];
                        if (wb_sel_i[0])
                                mem[{wb_adr_i[23:2], 2'b00}+3] = wb_dat_i[7:0];
                        $fdisplay(fflash, "%t [%h] <- write %h, byte sel %b", $time, wb_adr_i, wb_dat_i, wb_sel_i);
                end else if (wb_ack_o)
                        $fdisplay(fflash, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o);
// synopsys translate_on
 
endmodule
 
`else
 
module flash_top (
  wb_clk_i, wb_rst_i,
 
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
  wb_stb_i, wb_ack_o, wb_err_o,
 
  flash_rstn, cen, oen, wen, rdy, d, a, a_oe
);
 
//
// I/O Ports
//
 
//
// Common WB signals
//
input                   wb_clk_i;
input                   wb_rst_i;
 
//
// WB slave i/f
//
input   [31:0]           wb_dat_i;
output  [31:0]           wb_dat_o;
input   [31:0]           wb_adr_i;
input   [3:0]            wb_sel_i;
input                   wb_we_i;
input                   wb_cyc_i;
input                   wb_stb_i;
output                  wb_ack_o;
output                  wb_err_o;
 
//
// Flash i/f
//
output                  flash_rstn;
output                  oen;
output                  cen;
output                  wen;
input                   rdy;
inout   [7:0]            d;
output  [20:0]           a;
output                  a_oe;
 
//
// Internal wires and regs
//
reg                     ack;
reg     [3:0]            middle_tphqv;
reg     [31:0]           wb_dat_o;
reg     [4:0]            counter;
 
//
// Aliases and simple assignments
//
assign wb_ack_o = ~wb_err_o & ack;
assign wb_err_o = 1'b0;
assign flash_rstn = ~wb_rst_i;
assign a = { ~wb_adr_i[20], wb_adr_i[19:2], counter[3:2] };     // Lower 1MB is used by FPGA design conf.
assign a_oe = (wb_cyc_i &! (|middle_tphqv));
assign oen = |middle_tphqv;
assign wen = 1'b1;
assign cen = ~wb_cyc_i | ~wb_stb_i | (|middle_tphqv) | (counter[1:0] == 2'b00);
 
//
// Flash access time counter
//
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    counter <= #1 5'h0;
  else
  if (!wb_cyc_i | (counter == 5'h10) | (|middle_tphqv))
    counter <= #1 5'h0;
  else
    counter <= #1 counter + 1;
end
 
//
// Acknowledge
//
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    ack <= #1 1'h0;
  else
  if (counter == 5'h0f && !(|middle_tphqv))
    ack <= #1 1'h1;
  else
    ack <= #1 1'h0;
end
 
//
// Flash i/f monitor
//
// synopsys translate_off
integer fflash;
initial fflash = $fopen("flash.log");
 
always @(posedge wb_clk_i)
begin
  if (wb_cyc_i & !(|middle_tphqv)) begin
    if (wb_stb_i & wb_we_i) begin
      $fdisplay(fflash, "%t Trying to write into flash at %h", $time, wb_adr_i);
//    #100 $finish;
    end
    else if (ack)
      $fdisplay(fflash, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o);
  end
end
// synopsys translate_on
 
always @(posedge wb_clk_i or posedge wb_rst_i)
  if (wb_rst_i)
    middle_tphqv <= #1 4'hf;
  else if (middle_tphqv)
    middle_tphqv <= #1 middle_tphqv - 1;
 
//
// Flash 8-bit data expand into 32-bit WB data
//
always @(posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    wb_dat_o <= #1 32'h0000_0000;
  else
  if (counter[1:0] == 2'h3)
    begin
      case (counter[3:2])
        2'h0 : wb_dat_o[31:24] <= #1 d;
        2'h1 : wb_dat_o[23:16] <= #1 d;
        2'h2 : wb_dat_o[15:8]  <= #1 d;
        2'h3 : wb_dat_o[7:0]   <= #1 d;
      endcase
    end
end
 
endmodule
 
`endif

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// XESS Flash interface ////`
4			`//// ////`
5			`//// This file is part of the OR1K test application ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Connects the SoC to the Flash found on XSV board. It also ////`
10			`//// implements a generic flash model for simulations. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - nothing really ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Lior Shtram, lior.shtram@flextronicssemi.com ////`
17			`//// - Damjan Lampret, lampret@opencores.org ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20			`//// ////`
21			`//// Copyright (C) 2001 Authors ////`
22			`//// ////`
23			`//// This source file may be used and distributed without ////`
24			`//// restriction provided that this copyright statement is not ////`
25			`//// removed from the file and that any derivative work contains ////`
26			`//// the original copyright notice and the associated disclaimer. ////`
27			`//// ////`
28			`//// This source file is free software; you can redistribute it ////`
29			`//// and/or modify it under the terms of the GNU Lesser General ////`
30			`//// Public License as published by the Free Software Foundation; ////`
31			`//// either version 2.1 of the License, or (at your option) any ////`
32			`//// later version. ////`
33			`//// ////`
34			`//// This source is distributed in the hope that it will be ////`
35			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
36			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
37			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
38			`//// details. ////`
39			`//// ////`
40			`//// You should have received a copy of the GNU Lesser General ////`
41			`//// Public License along with this source; if not, download it ////`
42			`//// from http://www.opencores.org/lgpl.shtml ////`
43			`//// ////`
44			`//////////////////////////////////////////////////////////////////////`
45			`//`
46			`// CVS Revision History`
47			`//`
48			`// $Log: not supported by cvs2svn $`
49	1052	lampret	`// Revision 1.3 2002/08/14 06:24:43 lampret`
50			`// Fixed size of generic flash/sram to exactly 2MB`
51			`//`
52	959	lampret	`// Revision 1.2 2002/08/12 05:33:50 lampret`
53			`// Changed logic when FLASH_GENERIC_REGISTERED`
54			`//`
55	945	lampret	`// Revision 1.1.1.1 2002/03/21 16:55:44 lampret`
56			`// First import of the "new" XESS XSV environment.`
57			`//`
58			`//`
59	746	lampret	`// Revision 1.4 2002/02/11 04:41:01 lampret`
60			`// Allow flash writes. Ugly workaround for something else...`
61			`//`
62			`// Revision 1.3 2002/01/23 07:50:44 lampret`
63			`// Added wb_err_o to flash and sram i/f for testing the buserr exception.`
64			`//`
65			`// Revision 1.2 2002/01/14 06:18:22 lampret`
66			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
67			`//`
68			`// Revision 1.1.1.1 2001/11/04 19:00:09 lampret`
69			`// First import.`
70			`//`
71			`//`
72
73			`// synopsys translate_off`
74			`include "timescale.v"
75			`// synopsys translate_on`
76			//`include "bench_define.v"
77
78			`ifdef FLASH_GENERIC
79
80			`module flash_top (`
81			`wb_clk_i, wb_rst_i,`
82
83			`wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,`
84			`wb_stb_i, wb_ack_o, wb_err_o,`
85
86			`flash_rstn, cen, oen, wen, rdy, d, a, a_oe`
87			`);`
88
89			`//`
90			`// I/O Ports`
91			`//`
92
93			`//`
94			`// Common WB signals`
95			`//`
96			`input wb_clk_i;`
97			`input wb_rst_i;`
98
99			`//`
100			`// WB slave i/f`
101			`//`
102			`input [31:0] wb_dat_i;`
103			`output [31:0] wb_dat_o;`
104			`input [31:0] wb_adr_i;`
105			`input [3:0] wb_sel_i;`
106			`input wb_we_i;`
107			`input wb_cyc_i;`
108			`input wb_stb_i;`
109			`output wb_ack_o;`
110			`output wb_err_o;`
111
112			`//`
113			`// Flash i/f`
114			`//`
115			`output flash_rstn;`
116			`output oen;`
117			`output cen;`
118			`output wen;`
119			`input rdy;`
120			`inout [7:0] d;`
121			`output [20:0] a;`
122			`output a_oe;`
123
124			`//`
125			`// Internal wires and regs`
126			`//`
127	959	lampret	`reg [7:0] mem [2097151:0];`
128	746	lampret	`wire [31:0] adr;`
129			`ifdef FLASH_GENERIC_REGISTERED
130			`reg wb_err_o;`
131	945	lampret	`reg [31:0] prev_adr;`
132			`reg [1:0] delay;`
133			`else
134			`wire [1:0] delay;`
135	746	lampret	`endif
136			`wire wb_err;`
137
138			`//`
139			`// Aliases and simple assignments`
140			`//`
141			`assign flash_rstn = 1'b1;`
142			`assign oen = 1'b1;`
143			`assign cen = 1'b1;`
144			`assign wen = 1'b1;`
145			`assign a = 21'b0;`
146			`assign a_oe = 1'b1;`
147	1052	lampret	`assign wb_err = wb_cyc_i & wb_stb_i & (delay == 2'd0) & (\|wb_adr_i[23:21]); // If Access to > 2MB (8-bit leading prefix ignored)`
148	945	lampret	`assign adr = {8'h00, wb_adr_i[23:2], 2'b00};`
149	746	lampret
150			`//`
151			`// For simulation only`
152			`//`
153			`initial $readmemh("../src/flash.in", mem, 0);`
154	1052	lampret
155	746	lampret	`//`
156			`// Reading from flash model`
157			`//`
158	945	lampret	`assign wb_dat_o[7:0] = wb_adr_i[23:0] < 65535 ? mem[adr+3] : 8'h00;`
159			`assign wb_dat_o[15:8] = wb_adr_i[23:0] < 65535 ? mem[adr+2] : 8'h00;`
160			`assign wb_dat_o[23:16] = wb_adr_i[23:0] < 65535 ? mem[adr+1] : 8'h00;`
161			`assign wb_dat_o[31:24] = wb_adr_i[23:0] < 65535 ? mem[adr+0] : 8'h00;`
162	746	lampret
163	945	lampret
164	746	lampret	`ifdef FLASH_GENERIC_REGISTERED
165			`//`
166			`// WB Acknowledge`
167			`//`
168			`always @(posedge wb_clk_i or posedge wb_rst_i)`
169	945	lampret	`if (wb_rst_i) begin`
170			`delay <= #1 2'd3;`
171			`prev_adr <= #1 32'h0000_0000;`
172			`end`
173			`else if (delay && (wb_adr_i == prev_adr) && wb_cyc_i && wb_stb_i)`
174			`delay <= #1 delay - 2'd1;`
175	1052	lampret	`else if (wb_ack_o \|\| wb_err_o \|\| (wb_adr_i != prev_adr) \|\| ~wb_stb_i) begin`
176	945	lampret	`delay <= #1 2'd0; // delay ... can range from 3 to 0`
177			`prev_adr <= #1 wb_adr_i;`
178			`end`
179	746	lampret	`else
180	945	lampret	`assign delay = 2'd0;`
181	746	lampret	`endif
182
183	1052	lampret	`assign wb_ack_o = wb_cyc_i & wb_stb_i & ~wb_err & (delay == 2'd0)`
184	746	lampret	`ifdef FLASH_GENERIC_REGISTERED
185	945	lampret	`& (wb_adr_i == prev_adr)`
186			`endif
187			`;`
188
189			`ifdef FLASH_GENERIC_REGISTERED
190	746	lampret	`//`
191			`// WB Error`
192			`//`
193			`always @(posedge wb_clk_i or posedge wb_rst_i)`
194			`if (wb_rst_i)`
195			`wb_err_o <= #1 1'b0;`
196			`else`
197			`wb_err_o <= #1 wb_err & !wb_err_o;`
198			`else
199			`assign wb_err_o = wb_err;`
200			`endif
201
202			`//`
203			`// Flash i/f monitor`
204			`//`
205			`// synopsys translate_off`
206			`integer fflash;`
207			`initial fflash = $fopen("flash.log");`
208			`always @(posedge wb_clk_i)`
209			`if (wb_cyc_i)`
210			`if (wb_stb_i & wb_we_i) begin`
211			`// $fdisplay(fflash, "%t Trying to write into flash at %h (%b)", $time, wb_adr_i, wb_we_i);`
212			`// #100 $finish;`
213			`if (wb_sel_i[3])`
214	945	lampret	`mem[{wb_adr_i[23:2], 2'b00}+0] = wb_dat_i[31:24];`
215	746	lampret	`if (wb_sel_i[2])`
216	945	lampret	`mem[{wb_adr_i[23:2], 2'b00}+1] = wb_dat_i[23:16];`
217	746	lampret	`if (wb_sel_i[1])`
218	945	lampret	`mem[{wb_adr_i[23:2], 2'b00}+2] = wb_dat_i[15:8];`
219	746	lampret	`if (wb_sel_i[0])`
220	945	lampret	`mem[{wb_adr_i[23:2], 2'b00}+3] = wb_dat_i[7:0];`
221	746	lampret	`$fdisplay(fflash, "%t [%h] <- write %h, byte sel %b", $time, wb_adr_i, wb_dat_i, wb_sel_i);`
222			`end else if (wb_ack_o)`
223			`$fdisplay(fflash, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o);`
224			`// synopsys translate_on`
225
226			`endmodule`
227
228			`else
229
230			`module flash_top (`
231			`wb_clk_i, wb_rst_i,`
232
233			`wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,`
234			`wb_stb_i, wb_ack_o, wb_err_o,`
235
236			`flash_rstn, cen, oen, wen, rdy, d, a, a_oe`
237			`);`
238
239			`//`
240			`// I/O Ports`
241			`//`
242
243			`//`
244			`// Common WB signals`
245			`//`
246			`input wb_clk_i;`
247			`input wb_rst_i;`
248
249			`//`
250			`// WB slave i/f`
251			`//`
252			`input [31:0] wb_dat_i;`
253			`output [31:0] wb_dat_o;`
254			`input [31:0] wb_adr_i;`
255			`input [3:0] wb_sel_i;`
256			`input wb_we_i;`
257			`input wb_cyc_i;`
258			`input wb_stb_i;`
259			`output wb_ack_o;`
260			`output wb_err_o;`
261
262			`//`
263			`// Flash i/f`
264			`//`
265			`output flash_rstn;`
266			`output oen;`
267			`output cen;`
268			`output wen;`
269			`input rdy;`
270			`inout [7:0] d;`
271			`output [20:0] a;`
272			`output a_oe;`
273
274			`//`
275			`// Internal wires and regs`
276			`//`
277			`reg ack;`
278			`reg [3:0] middle_tphqv;`
279			`reg [31:0] wb_dat_o;`
280			`reg [4:0] counter;`
281
282			`//`
283			`// Aliases and simple assignments`
284			`//`
285	1052	lampret	`assign wb_ack_o = ~wb_err_o & ack;`
286	746	lampret	`assign wb_err_o = 1'b0;`
287			`assign flash_rstn = ~wb_rst_i;`
288			`assign a = { ~wb_adr_i[20], wb_adr_i[19:2], counter[3:2] }; // Lower 1MB is used by FPGA design conf.`
289			`assign a_oe = (wb_cyc_i &! (\|middle_tphqv));`
290			`assign oen = \|middle_tphqv;`
291			`assign wen = 1'b1;`
292			`assign cen = ~wb_cyc_i \| ~wb_stb_i \| (\|middle_tphqv) \| (counter[1:0] == 2'b00);`
293
294			`//`
295			`// Flash access time counter`
296			`//`
297			`always @(posedge wb_clk_i or posedge wb_rst_i)`
298			`begin`
299			`if (wb_rst_i)`
300			`counter <= #1 5'h0;`
301			`else`
302			`if (!wb_cyc_i \| (counter == 5'h10) \| (\|middle_tphqv))`
303			`counter <= #1 5'h0;`
304			`else`
305			`counter <= #1 counter + 1;`
306			`end`
307
308			`//`
309			`// Acknowledge`
310			`//`
311			`always @(posedge wb_clk_i or posedge wb_rst_i)`
312			`begin`
313			`if (wb_rst_i)`
314			`ack <= #1 1'h0;`
315			`else`
316			`if (counter == 5'h0f && !(\|middle_tphqv))`
317			`ack <= #1 1'h1;`
318			`else`
319			`ack <= #1 1'h0;`
320			`end`
321
322			`//`
323			`// Flash i/f monitor`
324			`//`
325			`// synopsys translate_off`
326			`integer fflash;`
327			`initial fflash = $fopen("flash.log");`
328
329			`always @(posedge wb_clk_i)`
330			`begin`
331			`if (wb_cyc_i & !(\|middle_tphqv)) begin`
332			`if (wb_stb_i & wb_we_i) begin`
333			`$fdisplay(fflash, "%t Trying to write into flash at %h", $time, wb_adr_i);`
334			`// #100 $finish;`
335			`end`
336			`else if (ack)`
337			`$fdisplay(fflash, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o);`
338			`end`
339			`end`
340			`// synopsys translate_on`
341
342			`always @(posedge wb_clk_i or posedge wb_rst_i)`
343			`if (wb_rst_i)`
344			`middle_tphqv <= #1 4'hf;`
345			`else if (middle_tphqv)`
346			`middle_tphqv <= #1 middle_tphqv - 1;`
347
348			`//`
349			`// Flash 8-bit data expand into 32-bit WB data`
350			`//`
351			`always @(posedge wb_clk_i or posedge wb_rst_i)`
352			`begin`
353			`if (wb_rst_i)`
354			`wb_dat_o <= #1 32'h0000_0000;`
355			`else`
356			`if (counter[1:0] == 2'h3)`
357			`begin`
358			`case (counter[3:2])`
359			`2'h0 : wb_dat_o[31:24] <= #1 d;`
360			`2'h1 : wb_dat_o[23:16] <= #1 d;`
361			`2'h2 : wb_dat_o[15:8] <= #1 d;`
362			`2'h3 : wb_dat_o[7:0] <= #1 d;`
363			`endcase`
364			`end`
365			`end`
366
367			`endmodule`
368
369			`endif

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