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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  XESS SRAM interface                                         ////
////                                                              ////
////  This file is part of the OR1K test application              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Connects the SoC to SRAM. It does RMW for byte accesses     ////
////  because XSV board has WEs on a 16-bit basis.                ////
////                                                              ////
////  To Do:                                                      ////
////   - nothing really                                           ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Srot, simons@opencores.org                      ////
////      - Igor Mohor, igorm@opencores.org                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2002/01/23 07:50:44  lampret
// Added wb_err_o to flash and sram i/f for testing the buserr exception.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1.1.1  2001/11/04 19:00:09  lampret
// First import.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
module sram_top (
  wb_clk_i, wb_rst_i,
 
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
  wb_stb_i, wb_ack_o, wb_err_o,
 
  r_cen, r0_wen, r1_wen, r_oen, r_a, r_d_i, r_d_o, d_oe,
  l_cen, l0_wen, l1_wen, l_oen, l_a, l_d_i, l_d_o
);
 
//
// Paraneters
//
parameter               aw = 19;
 
//
// I/O Ports
//
input                   wb_clk_i;
input                   wb_rst_i;
 
//
// WB slave i/f
//
input   [31:0]           wb_dat_i;
output  [31:0]           wb_dat_o;
input   [31:0]           wb_adr_i;
input   [3:0]            wb_sel_i;
input                   wb_we_i;
input                   wb_cyc_i;
input                   wb_stb_i;
output                  wb_ack_o;
output                  wb_err_o;
 
//
// Right SRAM bank
//
output                  r_oen;
output                  r0_wen;
output                  r1_wen;
output                  r_cen;
input   [15:0]           r_d_i;
output  [15:0]           r_d_o;
output  [aw-1:0] r_a;
 
//
// Left SRAM bank
//
output                  l_oen;
output                  l0_wen;
output                  l1_wen;
output                  l_cen;
input   [15:0]           l_d_i;
output  [15:0]           l_d_o;
output  [aw-1:0] l_a;
 
//
// Common SRAM signals
//
output                  d_oe;
 
//
// Internal regs and wires
//
reg     [15:0]           r_data;
reg     [15:0]           l_data;
reg                     l0_wen;
wire                    l1_wen = l0_wen;
reg                     r0_wen;
wire                    r1_wen = r0_wen;
reg     [31:0]           latch_data;
reg                     ack_we;
wire                    l_oe;
wire                    r_oe;
wire                    r_ack;
reg                     Mux;
reg     [aw-1:0] LatchedAddr;
reg     [15:0]           l_read;
reg     [15:0]           r_read;
reg                     d_oe;
reg     [15:0]           l_mux;
reg     [15:0]           r_mux;
 
//
// Aliases and simple assignments
//
assign wb_dat_o = {r_d_i, l_d_i};
assign l_oen = ~l_oe;
assign r_oen = ~r_oe;
assign l_a = Mux ? LatchedAddr : wb_adr_i[aw+1:2];
assign r_a = l_a;
assign l_d_o = l_mux;
assign r_d_o = r_mux;
assign l_oe = wb_cyc_i & wb_stb_i & l0_wen;
assign r_oe = wb_cyc_i & wb_stb_i & r0_wen;
assign l_cen = ~(wb_cyc_i & wb_stb_i);
assign r_cen = l_cen;
assign wb_ack_o = (wb_cyc_i & wb_stb_i & ~wb_we_i) | ack_we;
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[27:21]);     // If Access to > 2MB (4-bit leading prefix ignored)
 
//
// RMW mux control
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    Mux <= 1'b0;
  else
  if (ack_we)
    Mux <= #1 1'b1;
  else
    Mux <= #1 1'b0;
end
 
//
// Latch address
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    LatchedAddr <= 'h0;
  else
  if (wb_cyc_i & wb_stb_i)
    LatchedAddr <= #1 wb_adr_i[aw+1:2];
end
 
//
// Latch data from RAM (read data)
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    begin
      l_read <= 16'h0;
      r_read <= 16'h0;
    end
  else
  if (wb_cyc_i & wb_stb_i)
    begin
      l_read <= #1 l_d_i[15:0];
      r_read <= #1 r_d_i[15:0];
    end
end
 
//
// Mux and latch data for writing left SRAM bank (bytes 0 and 1)
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    l_mux <= 16'h0;
  else
  if (~l0_wen)
    begin
      if (wb_sel_i[0])
        l_mux[7:0]  <= #1 wb_dat_i[7:0];
      else
        l_mux[7:0]  <= #1 l_read[7:0];
      if (wb_sel_i[1])
        l_mux[15:8] <= #1 wb_dat_i[15:8];
      else
        l_mux[15:8] <= #1 l_read[15:8];
    end
  else
    l_mux[15:0]  <= #1 16'hz;
end
 
//
// Mux and latch data for writing right SRAM bank (bytes 2 and 3)
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    r_mux <= 16'h0;
  else
  if (~r0_wen)
    begin
      if (wb_sel_i[2])
        r_mux[7:0]  <= #1 wb_dat_i[23:16];
      else
        r_mux[7:0]  <= #1 r_read[7:0];
      if (wb_sel_i[3])
        r_mux[15:8]  <= #1 wb_dat_i[31:24];
      else
        r_mux[15:8]  <= #1 r_read[15:8];
    end
  else
    r_mux <= #1 16'hz;
end
 
//
// Left WE
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    l0_wen <= 1'b1;
  else
  if (wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[1:0]) & ~wb_ack_o)
    l0_wen <= #1 1'b0;
  else
    l0_wen <= #1 1'b1;
end
 
//
// Right WE
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    r0_wen <= 1'b1;
  else
  if (wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:2]) & ~wb_ack_o)
    r0_wen <= #1 1'b0;
  else
    r0_wen <= #1 1'b1;
end
 
//
// Write acknowledge
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    ack_we <= 1'b0;
  else
  if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
    ack_we <= #1 1'b1;
  else
    ack_we <= #1 1'b0;
end
 
//
// Generate d_oe signal (tristate control)
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    d_oe <= 1'b0;
  else
  if (~l0_wen | ~r0_wen)
    d_oe <= 1'b1;
  else
    d_oe <= 1'b0;
end
 
//
// SRAM i/f monitor
//
// synopsys translate_off
integer fsram;
initial fsram = $fopen("sram.log");
always @(posedge wb_clk_i)
begin
  if (~l0_wen | ~r0_wen)
    $fdisplay(fsram, "%t [%h] <- write %h", $time, wb_adr_i, {r_d_o, l_d_o});
  else
  if ((l_oe | r_oe) & ~wb_we_i)
    $fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, {r_d_i, l_d_i});
end
// synopsys translate_on
 
endmodule

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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [mem_if/] [sram_top.v] - Blame information for rev 746

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// XESS SRAM interface ////`
4			`//// ////`
5			`//// This file is part of the OR1K test application ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Connects the SoC to SRAM. It does RMW for byte accesses ////`
10			`//// because XSV board has WEs on a 16-bit basis. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - nothing really ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Simon Srot, simons@opencores.org ////`
17			`//// - Igor Mohor, igorm@opencores.org ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20			`//// ////`
21			`//// Copyright (C) 2001 Authors ////`
22			`//// ////`
23			`//// This source file may be used and distributed without ////`
24			`//// restriction provided that this copyright statement is not ////`
25			`//// removed from the file and that any derivative work contains ////`
26			`//// the original copyright notice and the associated disclaimer. ////`
27			`//// ////`
28			`//// This source file is free software; you can redistribute it ////`
29			`//// and/or modify it under the terms of the GNU Lesser General ////`
30			`//// Public License as published by the Free Software Foundation; ////`
31			`//// either version 2.1 of the License, or (at your option) any ////`
32			`//// later version. ////`
33			`//// ////`
34			`//// This source is distributed in the hope that it will be ////`
35			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
36			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
37			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
38			`//// details. ////`
39			`//// ////`
40			`//// You should have received a copy of the GNU Lesser General ////`
41			`//// Public License along with this source; if not, download it ////`
42			`//// from http://www.opencores.org/lgpl.shtml ////`
43			`//// ////`
44			`//////////////////////////////////////////////////////////////////////`
45			`//`
46			`// CVS Revision History`
47			`//`
48			`// $Log: not supported by cvs2svn $`
49			`// Revision 1.3 2002/01/23 07:50:44 lampret`
50			`// Added wb_err_o to flash and sram i/f for testing the buserr exception.`
51			`//`
52			`// Revision 1.2 2002/01/14 06:18:22 lampret`
53			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
54			`//`
55			`// Revision 1.1.1.1 2001/11/04 19:00:09 lampret`
56			`// First import.`
57			`//`
58			`//`
59
60			`// synopsys translate_off`
61			`include "timescale.v"
62			`// synopsys translate_on`
63
64			`module sram_top (`
65			`wb_clk_i, wb_rst_i,`
66
67			`wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,`
68			`wb_stb_i, wb_ack_o, wb_err_o,`
69
70			`r_cen, r0_wen, r1_wen, r_oen, r_a, r_d_i, r_d_o, d_oe,`
71			`l_cen, l0_wen, l1_wen, l_oen, l_a, l_d_i, l_d_o`
72			`);`
73
74			`//`
75			`// Paraneters`
76			`//`
77			`parameter aw = 19;`
78
79			`//`
80			`// I/O Ports`
81			`//`
82			`input wb_clk_i;`
83			`input wb_rst_i;`
84
85			`//`
86			`// WB slave i/f`
87			`//`
88			`input [31:0] wb_dat_i;`
89			`output [31:0] wb_dat_o;`
90			`input [31:0] wb_adr_i;`
91			`input [3:0] wb_sel_i;`
92			`input wb_we_i;`
93			`input wb_cyc_i;`
94			`input wb_stb_i;`
95			`output wb_ack_o;`
96			`output wb_err_o;`
97
98			`//`
99			`// Right SRAM bank`
100			`//`
101			`output r_oen;`
102			`output r0_wen;`
103			`output r1_wen;`
104			`output r_cen;`
105			`input [15:0] r_d_i;`
106			`output [15:0] r_d_o;`
107			`output [aw-1:0] r_a;`
108
109			`//`
110			`// Left SRAM bank`
111			`//`
112			`output l_oen;`
113			`output l0_wen;`
114			`output l1_wen;`
115			`output l_cen;`
116			`input [15:0] l_d_i;`
117			`output [15:0] l_d_o;`
118			`output [aw-1:0] l_a;`
119
120			`//`
121			`// Common SRAM signals`
122			`//`
123			`output d_oe;`
124
125			`//`
126			`// Internal regs and wires`
127			`//`
128			`reg [15:0] r_data;`
129			`reg [15:0] l_data;`
130			`reg l0_wen;`
131			`wire l1_wen = l0_wen;`
132			`reg r0_wen;`
133			`wire r1_wen = r0_wen;`
134			`reg [31:0] latch_data;`
135			`reg ack_we;`
136			`wire l_oe;`
137			`wire r_oe;`
138			`wire r_ack;`
139			`reg Mux;`
140			`reg [aw-1:0] LatchedAddr;`
141			`reg [15:0] l_read;`
142			`reg [15:0] r_read;`
143			`reg d_oe;`
144			`reg [15:0] l_mux;`
145			`reg [15:0] r_mux;`
146
147			`//`
148			`// Aliases and simple assignments`
149			`//`
150			`assign wb_dat_o = {r_d_i, l_d_i};`
151			`assign l_oen = ~l_oe;`
152			`assign r_oen = ~r_oe;`
153			`assign l_a = Mux ? LatchedAddr : wb_adr_i[aw+1:2];`
154			`assign r_a = l_a;`
155			`assign l_d_o = l_mux;`
156			`assign r_d_o = r_mux;`
157			`assign l_oe = wb_cyc_i & wb_stb_i & l0_wen;`
158			`assign r_oe = wb_cyc_i & wb_stb_i & r0_wen;`
159			`assign l_cen = ~(wb_cyc_i & wb_stb_i);`
160			`assign r_cen = l_cen;`
161			`assign wb_ack_o = (wb_cyc_i & wb_stb_i & ~wb_we_i) \| ack_we;`
162			`assign wb_err_o = wb_cyc_i & wb_stb_i & (\|wb_adr_i[27:21]); // If Access to > 2MB (4-bit leading prefix ignored)`
163
164			`//`
165			`// RMW mux control`
166			`//`
167			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
168			`begin`
169			`if (wb_rst_i)`
170			`Mux <= 1'b0;`
171			`else`
172			`if (ack_we)`
173			`Mux <= #1 1'b1;`
174			`else`
175			`Mux <= #1 1'b0;`
176			`end`
177
178			`//`
179			`// Latch address`
180			`//`
181			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
182			`begin`
183			`if (wb_rst_i)`
184			`LatchedAddr <= 'h0;`
185			`else`
186			`if (wb_cyc_i & wb_stb_i)`
187			`LatchedAddr <= #1 wb_adr_i[aw+1:2];`
188			`end`
189
190			`//`
191			`// Latch data from RAM (read data)`
192			`//`
193			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
194			`begin`
195			`if (wb_rst_i)`
196			`begin`
197			`l_read <= 16'h0;`
198			`r_read <= 16'h0;`
199			`end`
200			`else`
201			`if (wb_cyc_i & wb_stb_i)`
202			`begin`
203			`l_read <= #1 l_d_i[15:0];`
204			`r_read <= #1 r_d_i[15:0];`
205			`end`
206			`end`
207
208			`//`
209			`// Mux and latch data for writing left SRAM bank (bytes 0 and 1)`
210			`//`
211			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
212			`begin`
213			`if (wb_rst_i)`
214			`l_mux <= 16'h0;`
215			`else`
216			`if (~l0_wen)`
217			`begin`
218			`if (wb_sel_i[0])`
219			`l_mux[7:0] <= #1 wb_dat_i[7:0];`
220			`else`
221			`l_mux[7:0] <= #1 l_read[7:0];`
222			`if (wb_sel_i[1])`
223			`l_mux[15:8] <= #1 wb_dat_i[15:8];`
224			`else`
225			`l_mux[15:8] <= #1 l_read[15:8];`
226			`end`
227			`else`
228			`l_mux[15:0] <= #1 16'hz;`
229			`end`
230
231			`//`
232			`// Mux and latch data for writing right SRAM bank (bytes 2 and 3)`
233			`//`
234			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
235			`begin`
236			`if (wb_rst_i)`
237			`r_mux <= 16'h0;`
238			`else`
239			`if (~r0_wen)`
240			`begin`
241			`if (wb_sel_i[2])`
242			`r_mux[7:0] <= #1 wb_dat_i[23:16];`
243			`else`
244			`r_mux[7:0] <= #1 r_read[7:0];`
245			`if (wb_sel_i[3])`
246			`r_mux[15:8] <= #1 wb_dat_i[31:24];`
247			`else`
248			`r_mux[15:8] <= #1 r_read[15:8];`
249			`end`
250			`else`
251			`r_mux <= #1 16'hz;`
252			`end`
253
254			`//`
255			`// Left WE`
256			`//`
257			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
258			`begin`
259			`if (wb_rst_i)`
260			`l0_wen <= 1'b1;`
261			`else`
262			`if (wb_cyc_i & wb_stb_i & wb_we_i & (\|wb_sel_i[1:0]) & ~wb_ack_o)`
263			`l0_wen <= #1 1'b0;`
264			`else`
265			`l0_wen <= #1 1'b1;`
266			`end`
267
268			`//`
269			`// Right WE`
270			`//`
271			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
272			`begin`
273			`if (wb_rst_i)`
274			`r0_wen <= 1'b1;`
275			`else`
276			`if (wb_cyc_i & wb_stb_i & wb_we_i & (\|wb_sel_i[3:2]) & ~wb_ack_o)`
277			`r0_wen <= #1 1'b0;`
278			`else`
279			`r0_wen <= #1 1'b1;`
280			`end`
281
282			`//`
283			`// Write acknowledge`
284			`//`
285			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
286			`begin`
287			`if (wb_rst_i)`
288			`ack_we <= 1'b0;`
289			`else`
290			`if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)`
291			`ack_we <= #1 1'b1;`
292			`else`
293			`ack_we <= #1 1'b0;`
294			`end`
295
296			`//`
297			`// Generate d_oe signal (tristate control)`
298			`//`
299			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
300			`begin`
301			`if (wb_rst_i)`
302			`d_oe <= 1'b0;`
303			`else`
304			`if (~l0_wen \| ~r0_wen)`
305			`d_oe <= 1'b1;`
306			`else`
307			`d_oe <= 1'b0;`
308			`end`
309
310			`//`
311			`// SRAM i/f monitor`
312			`//`
313			`// synopsys translate_off`
314			`integer fsram;`
315			`initial fsram = $fopen("sram.log");`
316			`always @(posedge wb_clk_i)`
317			`begin`
318			`if (~l0_wen \| ~r0_wen)`
319			`$fdisplay(fsram, "%t [%h] <- write %h", $time, wb_adr_i, {r_d_o, l_d_o});`
320			`else`
321			`if ((l_oe \| r_oe) & ~wb_we_i)`
322			`$fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, {r_d_i, l_d_i});`
323			`end`
324			`// synopsys translate_on`
325
326			`endmodule`