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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [mem_if/] [sram_top.v] - Blame information for rev 946

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  XESS SRAM interface                                         ////
////                                                              ////
////  This file is part of the OR1K test application              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Connects the SoC to SRAM. It does RMW for byte accesses     ////
////  because XSV board has WEs on a 16-bit basis.                ////
////                                                              ////
////  To Do:                                                      ////
////   - nothing really                                           ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Srot, simons@opencores.org                      ////
////      - Igor Mohor, igorm@opencores.org                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1.1.1  2002/03/21 16:55:44  lampret
// First import of the "new" XESS XSV environment.
//
//
// Revision 1.3  2002/01/23 07:50:44  lampret
// Added wb_err_o to flash and sram i/f for testing the buserr exception.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1.1.1  2001/11/04 19:00:09  lampret
// First import.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
`define SRAM_GENERIC
 
`ifdef SRAM_GENERIC
 
module sram_top (
  wb_clk_i, wb_rst_i,
 
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
  wb_stb_i, wb_ack_o, wb_err_o,
 
  r_cen, r0_wen, r1_wen, r_oen, r_a, r_d_i, r_d_o, d_oe,
  l_cen, l0_wen, l1_wen, l_oen, l_a, l_d_i, l_d_o
);
 
//
// Paraneters
//
parameter               aw = 19;
 
//
// I/O Ports
//
input                   wb_clk_i;
input                   wb_rst_i;
 
//
// WB slave i/f
//
input   [31:0]           wb_dat_i;
output  [31:0]           wb_dat_o;
input   [31:0]           wb_adr_i;
input   [3:0]            wb_sel_i;
input                   wb_we_i;
input                   wb_cyc_i;
input                   wb_stb_i;
output                  wb_ack_o;
output                  wb_err_o;
 
//
// Right SRAM bank
//
output                  r_oen;
output                  r0_wen;
output                  r1_wen;
output                  r_cen;
input   [15:0]           r_d_i;
output  [15:0]           r_d_o;
output  [aw-1:0] r_a;
 
//
// Left SRAM bank
//
output                  l_oen;
output                  l0_wen;
output                  l1_wen;
output                  l_cen;
input   [15:0]           l_d_i;
output  [15:0]           l_d_o;
output  [aw-1:0] l_a;
 
//
// Common SRAM signals
//
output                  d_oe;
 
//
// Internal wires and regs
//
reg     [7:0]           mem [2100000:0];
wire    [31:0]          adr;
`ifdef SRAM_GENERIC_REGISTERED
reg                     wb_ack_o;
reg                     wb_err_o;
reg     [31:0]          wb_dat_o;
`endif
wire                    wb_err;
 
//
// Aliases and simple assignments
//
assign wb_err = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:21]);     // If Access to > 2MB (8-bit leading prefix ignored)
assign adr = {8'h00, wb_adr_i[23:2], 2'b00};
 
`ifdef SRAM_GENERIC_REGISTERED
//
// Reading from SRAM model
//
always @(posedge wb_rst_i or posedge wb_clk_i)
        if (wb_rst_i)
                wb_dat_o <= #1 32'h0000_0000;
        else begin
                wb_dat_o[7:0] <= #1 mem[adr+3];
                wb_dat_o[15:8] <= #1 mem[adr+2];
                wb_dat_o[23:16] <= #1 mem[adr+1];
                wb_dat_o[31:24] <= #1 mem[adr+0];
        end
`else
assign wb_dat_o[7:0] = mem[adr+3];
assign wb_dat_o[15:8] = mem[adr+2];
assign wb_dat_o[23:16] = mem[adr+1];
assign wb_dat_o[31:24] = mem[adr+0];
`endif
 
//
// Writing to SRAM model
//
always @(posedge wb_rst_i or posedge wb_clk_i)
        if (wb_cyc_i & wb_stb_i & wb_we_i) begin
                if (wb_sel_i[0])
                        mem[adr+3] <= #1 wb_dat_i[7:0];
                if (wb_sel_i[1])
                        mem[adr+2] <= #1 wb_dat_i[15:8];
                if (wb_sel_i[2])
                        mem[adr+1] <= #1 wb_dat_i[23:16];
                if (wb_sel_i[3])
                        mem[adr+0] <= #1 wb_dat_i[31:24];
        end
 
`ifdef SRAM_GENERIC_REGISTERED
//
// WB Acknowledge
//
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_ack_o <= #1 1'b0;
        else
                wb_ack_o <= #1 wb_cyc_i & wb_stb_i & !wb_ack_o;
`else
assign wb_ack_o = wb_cyc_i & wb_stb_i;
`endif
 
`ifdef SRAM_GENERIC_REGISTERED
//
// WB Error
//
always @(posedge wb_clk_i or posedge wb_rst_i)
        if (wb_rst_i)
                wb_err_o <= #1 1'b0;
        else
                wb_err_o <= #1 wb_err & !wb_err_o;
`else
assign wb_err_o = wb_err;
`endif
 
//
// Flash i/f monitor
//
// synopsys translate_off
integer fsram;
initial fsram = $fopen("sram.log");
always @(posedge wb_clk_i)
        if (wb_cyc_i)
                if (wb_stb_i & wb_we_i) begin
                        if (wb_sel_i[3])
                                mem[{wb_adr_i[23:2], 2'b00}+0] = wb_dat_i[31:24];
                        if (wb_sel_i[2])
                                mem[{wb_adr_i[23:2], 2'b00}+1] = wb_dat_i[23:16];
                        if (wb_sel_i[1])
                                mem[{wb_adr_i[23:2], 2'b00}+2] = wb_dat_i[15:8];
                        if (wb_sel_i[0])
                                mem[{wb_adr_i[23:2], 2'b00}+3] = wb_dat_i[7:0];
                        $fdisplay(fsram, "%t [%h] <- write %h, byte sel %b", $time, wb_adr_i, wb_dat_i, wb_sel_i);
                end else if (wb_ack_o)
                        $fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o);
// synopsys translate_on
 
endmodule
 
`else
 
module sram_top (
  wb_clk_i, wb_rst_i,
 
  wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
  wb_stb_i, wb_ack_o, wb_err_o,
 
  r_cen, r0_wen, r1_wen, r_oen, r_a, r_d_i, r_d_o, d_oe,
  l_cen, l0_wen, l1_wen, l_oen, l_a, l_d_i, l_d_o
);
 
//
// Paraneters
//
parameter               aw = 19;
 
//
// I/O Ports
//
input                   wb_clk_i;
input                   wb_rst_i;
 
//
// WB slave i/f
//
input   [31:0]           wb_dat_i;
output  [31:0]           wb_dat_o;
input   [31:0]           wb_adr_i;
input   [3:0]            wb_sel_i;
input                   wb_we_i;
input                   wb_cyc_i;
input                   wb_stb_i;
output                  wb_ack_o;
output                  wb_err_o;
 
//
// Right SRAM bank
//
output                  r_oen;
output                  r0_wen;
output                  r1_wen;
output                  r_cen;
input   [15:0]           r_d_i;
output  [15:0]           r_d_o;
output  [aw-1:0] r_a;
 
//
// Left SRAM bank
//
output                  l_oen;
output                  l0_wen;
output                  l1_wen;
output                  l_cen;
input   [15:0]           l_d_i;
output  [15:0]           l_d_o;
output  [aw-1:0] l_a;
 
//
// Common SRAM signals
//
output                  d_oe;
 
//
// Internal regs and wires
//
reg     [15:0]           r_data;
reg     [15:0]           l_data;
reg                     l0_wen;
wire                    l1_wen = l0_wen;
reg                     r0_wen;
wire                    r1_wen = r0_wen;
reg     [31:0]           latch_data;
reg                     ack_we;
wire                    l_oe;
wire                    r_oe;
wire                    r_ack;
reg                     Mux;
reg     [aw-1:0] LatchedAddr;
reg     [15:0]           l_read;
reg     [15:0]           r_read;
reg                     d_oe;
reg     [15:0]           l_mux;
reg     [15:0]           r_mux;
 
//
// Aliases and simple assignments
//
assign wb_dat_o = {r_d_i, l_d_i};
assign l_oen = ~l_oe;
assign r_oen = ~r_oe;
assign l_a = Mux ? LatchedAddr : wb_adr_i[aw+1:2];
assign r_a = l_a;
assign l_d_o = l_mux;
assign r_d_o = r_mux;
assign l_oe = wb_cyc_i & wb_stb_i & l0_wen;
assign r_oe = wb_cyc_i & wb_stb_i & r0_wen;
assign l_cen = ~(wb_cyc_i & wb_stb_i);
assign r_cen = l_cen;
assign wb_ack_o = (wb_cyc_i & wb_stb_i & ~wb_we_i) | ack_we;
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[27:21]);     // If Access to > 2MB (4-bit leading prefix ignored)
 
//
// RMW mux control
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    Mux <= 1'b0;
  else
  if (ack_we)
    Mux <= #1 1'b1;
  else
    Mux <= #1 1'b0;
end
 
//
// Latch address
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    LatchedAddr <= 'h0;
  else
  if (wb_cyc_i & wb_stb_i)
    LatchedAddr <= #1 wb_adr_i[aw+1:2];
end
 
//
// Latch data from RAM (read data)
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    begin
      l_read <= 16'h0;
      r_read <= 16'h0;
    end
  else
  if (wb_cyc_i & wb_stb_i)
    begin
      l_read <= #1 l_d_i[15:0];
      r_read <= #1 r_d_i[15:0];
    end
end
 
//
// Mux and latch data for writing left SRAM bank (bytes 0 and 1)
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    l_mux <= 16'h0;
  else
  if (~l0_wen)
    begin
      if (wb_sel_i[0])
        l_mux[7:0]  <= #1 wb_dat_i[7:0];
      else
        l_mux[7:0]  <= #1 l_read[7:0];
      if (wb_sel_i[1])
        l_mux[15:8] <= #1 wb_dat_i[15:8];
      else
        l_mux[15:8] <= #1 l_read[15:8];
    end
  else
    l_mux[15:0]  <= #1 16'hz;
end
 
//
// Mux and latch data for writing right SRAM bank (bytes 2 and 3)
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    r_mux <= 16'h0;
  else
  if (~r0_wen)
    begin
      if (wb_sel_i[2])
        r_mux[7:0]  <= #1 wb_dat_i[23:16];
      else
        r_mux[7:0]  <= #1 r_read[7:0];
      if (wb_sel_i[3])
        r_mux[15:8]  <= #1 wb_dat_i[31:24];
      else
        r_mux[15:8]  <= #1 r_read[15:8];
    end
  else
    r_mux <= #1 16'hz;
end
 
//
// Left WE
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    l0_wen <= 1'b1;
  else
  if (wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[1:0]) & ~wb_ack_o)
    l0_wen <= #1 1'b0;
  else
    l0_wen <= #1 1'b1;
end
 
//
// Right WE
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    r0_wen <= 1'b1;
  else
  if (wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:2]) & ~wb_ack_o)
    r0_wen <= #1 1'b0;
  else
    r0_wen <= #1 1'b1;
end
 
//
// Write acknowledge
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    ack_we <= 1'b0;
  else
  if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
    ack_we <= #1 1'b1;
  else
    ack_we <= #1 1'b0;
end
 
//
// Generate d_oe signal (tristate control)
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
  if (wb_rst_i)
    d_oe <= 1'b0;
  else
  if (~l0_wen | ~r0_wen)
    d_oe <= 1'b1;
  else
    d_oe <= 1'b0;
end
 
//
// SRAM i/f monitor
//
// synopsys translate_off
integer fsram;
initial fsram = $fopen("sram.log");
always @(posedge wb_clk_i)
begin
  if (~l0_wen | ~r0_wen)
    $fdisplay(fsram, "%t [%h] <- write %h", $time, wb_adr_i, {r_d_o, l_d_o});
  else
  if ((l_oe | r_oe) & ~wb_we_i)
    $fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, {r_d_i, l_d_i});
end
// synopsys translate_on
 
endmodule
 
`endif

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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [mem_if/] [sram_top.v] - Blame information for rev 946

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// XESS SRAM interface ////`
4			`//// ////`
5			`//// This file is part of the OR1K test application ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Connects the SoC to SRAM. It does RMW for byte accesses ////`
10			`//// because XSV board has WEs on a 16-bit basis. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - nothing really ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Simon Srot, simons@opencores.org ////`
17			`//// - Igor Mohor, igorm@opencores.org ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20			`//// ////`
21			`//// Copyright (C) 2001 Authors ////`
22			`//// ////`
23			`//// This source file may be used and distributed without ////`
24			`//// restriction provided that this copyright statement is not ////`
25			`//// removed from the file and that any derivative work contains ////`
26			`//// the original copyright notice and the associated disclaimer. ////`
27			`//// ////`
28			`//// This source file is free software; you can redistribute it ////`
29			`//// and/or modify it under the terms of the GNU Lesser General ////`
30			`//// Public License as published by the Free Software Foundation; ////`
31			`//// either version 2.1 of the License, or (at your option) any ////`
32			`//// later version. ////`
33			`//// ////`
34			`//// This source is distributed in the hope that it will be ////`
35			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
36			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
37			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
38			`//// details. ////`
39			`//// ////`
40			`//// You should have received a copy of the GNU Lesser General ////`
41			`//// Public License along with this source; if not, download it ////`
42			`//// from http://www.opencores.org/lgpl.shtml ////`
43			`//// ////`
44			`//////////////////////////////////////////////////////////////////////`
45			`//`
46			`// CVS Revision History`
47			`//`
48			`// $Log: not supported by cvs2svn $`
49	946	lampret	`// Revision 1.1.1.1 2002/03/21 16:55:44 lampret`
50			`// First import of the "new" XESS XSV environment.`
51			`//`
52			`//`
53	746	lampret	`// Revision 1.3 2002/01/23 07:50:44 lampret`
54			`// Added wb_err_o to flash and sram i/f for testing the buserr exception.`
55			`//`
56			`// Revision 1.2 2002/01/14 06:18:22 lampret`
57			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
58			`//`
59			`// Revision 1.1.1.1 2001/11/04 19:00:09 lampret`
60			`// First import.`
61			`//`
62			`//`
63
64			`// synopsys translate_off`
65			`include "timescale.v"
66			`// synopsys translate_on`
67
68	946	lampret	`define SRAM_GENERIC
69
70			`ifdef SRAM_GENERIC
71
72	746	lampret	`module sram_top (`
73			`wb_clk_i, wb_rst_i,`
74
75			`wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,`
76			`wb_stb_i, wb_ack_o, wb_err_o,`
77
78			`r_cen, r0_wen, r1_wen, r_oen, r_a, r_d_i, r_d_o, d_oe,`
79			`l_cen, l0_wen, l1_wen, l_oen, l_a, l_d_i, l_d_o`
80			`);`
81
82			`//`
83			`// Paraneters`
84			`//`
85			`parameter aw = 19;`
86
87			`//`
88			`// I/O Ports`
89			`//`
90			`input wb_clk_i;`
91			`input wb_rst_i;`
92
93			`//`
94			`// WB slave i/f`
95			`//`
96			`input [31:0] wb_dat_i;`
97			`output [31:0] wb_dat_o;`
98			`input [31:0] wb_adr_i;`
99			`input [3:0] wb_sel_i;`
100			`input wb_we_i;`
101			`input wb_cyc_i;`
102			`input wb_stb_i;`
103			`output wb_ack_o;`
104			`output wb_err_o;`
105
106			`//`
107			`// Right SRAM bank`
108			`//`
109			`output r_oen;`
110			`output r0_wen;`
111			`output r1_wen;`
112			`output r_cen;`
113			`input [15:0] r_d_i;`
114			`output [15:0] r_d_o;`
115			`output [aw-1:0] r_a;`
116
117			`//`
118			`// Left SRAM bank`
119			`//`
120			`output l_oen;`
121			`output l0_wen;`
122			`output l1_wen;`
123			`output l_cen;`
124			`input [15:0] l_d_i;`
125			`output [15:0] l_d_o;`
126			`output [aw-1:0] l_a;`
127
128			`//`
129			`// Common SRAM signals`
130			`//`
131			`output d_oe;`
132
133			`//`
134	946	lampret	`// Internal wires and regs`
135			`//`
136			`reg [7:0] mem [2100000:0];`
137			`wire [31:0] adr;`
138			`ifdef SRAM_GENERIC_REGISTERED
139			`reg wb_ack_o;`
140			`reg wb_err_o;`
141			`reg [31:0] wb_dat_o;`
142			`endif
143			`wire wb_err;`
144
145			`//`
146			`// Aliases and simple assignments`
147			`//`
148			`assign wb_err = wb_cyc_i & wb_stb_i & (\|wb_adr_i[23:21]); // If Access to > 2MB (8-bit leading prefix ignored)`
149			`assign adr = {8'h00, wb_adr_i[23:2], 2'b00};`
150
151			`ifdef SRAM_GENERIC_REGISTERED
152			`//`
153			`// Reading from SRAM model`
154			`//`
155			`always @(posedge wb_rst_i or posedge wb_clk_i)`
156			`if (wb_rst_i)`
157			`wb_dat_o <= #1 32'h0000_0000;`
158			`else begin`
159			`wb_dat_o[7:0] <= #1 mem[adr+3];`
160			`wb_dat_o[15:8] <= #1 mem[adr+2];`
161			`wb_dat_o[23:16] <= #1 mem[adr+1];`
162			`wb_dat_o[31:24] <= #1 mem[adr+0];`
163			`end`
164			`else
165			`assign wb_dat_o[7:0] = mem[adr+3];`
166			`assign wb_dat_o[15:8] = mem[adr+2];`
167			`assign wb_dat_o[23:16] = mem[adr+1];`
168			`assign wb_dat_o[31:24] = mem[adr+0];`
169			`endif
170
171			`//`
172			`// Writing to SRAM model`
173			`//`
174			`always @(posedge wb_rst_i or posedge wb_clk_i)`
175			`if (wb_cyc_i & wb_stb_i & wb_we_i) begin`
176			`if (wb_sel_i[0])`
177			`mem[adr+3] <= #1 wb_dat_i[7:0];`
178			`if (wb_sel_i[1])`
179			`mem[adr+2] <= #1 wb_dat_i[15:8];`
180			`if (wb_sel_i[2])`
181			`mem[adr+1] <= #1 wb_dat_i[23:16];`
182			`if (wb_sel_i[3])`
183			`mem[adr+0] <= #1 wb_dat_i[31:24];`
184			`end`
185
186			`ifdef SRAM_GENERIC_REGISTERED
187			`//`
188			`// WB Acknowledge`
189			`//`
190			`always @(posedge wb_clk_i or posedge wb_rst_i)`
191			`if (wb_rst_i)`
192			`wb_ack_o <= #1 1'b0;`
193			`else`
194			`wb_ack_o <= #1 wb_cyc_i & wb_stb_i & !wb_ack_o;`
195			`else
196			`assign wb_ack_o = wb_cyc_i & wb_stb_i;`
197			`endif
198
199			`ifdef SRAM_GENERIC_REGISTERED
200			`//`
201			`// WB Error`
202			`//`
203			`always @(posedge wb_clk_i or posedge wb_rst_i)`
204			`if (wb_rst_i)`
205			`wb_err_o <= #1 1'b0;`
206			`else`
207			`wb_err_o <= #1 wb_err & !wb_err_o;`
208			`else
209			`assign wb_err_o = wb_err;`
210			`endif
211
212			`//`
213			`// Flash i/f monitor`
214			`//`
215			`// synopsys translate_off`
216			`integer fsram;`
217			`initial fsram = $fopen("sram.log");`
218			`always @(posedge wb_clk_i)`
219			`if (wb_cyc_i)`
220			`if (wb_stb_i & wb_we_i) begin`
221			`if (wb_sel_i[3])`
222			`mem[{wb_adr_i[23:2], 2'b00}+0] = wb_dat_i[31:24];`
223			`if (wb_sel_i[2])`
224			`mem[{wb_adr_i[23:2], 2'b00}+1] = wb_dat_i[23:16];`
225			`if (wb_sel_i[1])`
226			`mem[{wb_adr_i[23:2], 2'b00}+2] = wb_dat_i[15:8];`
227			`if (wb_sel_i[0])`
228			`mem[{wb_adr_i[23:2], 2'b00}+3] = wb_dat_i[7:0];`
229			`$fdisplay(fsram, "%t [%h] <- write %h, byte sel %b", $time, wb_adr_i, wb_dat_i, wb_sel_i);`
230			`end else if (wb_ack_o)`
231			`$fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, wb_dat_o);`
232			`// synopsys translate_on`
233
234			`endmodule`
235
236			`else
237
238			`module sram_top (`
239			`wb_clk_i, wb_rst_i,`
240
241			`wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,`
242			`wb_stb_i, wb_ack_o, wb_err_o,`
243
244			`r_cen, r0_wen, r1_wen, r_oen, r_a, r_d_i, r_d_o, d_oe,`
245			`l_cen, l0_wen, l1_wen, l_oen, l_a, l_d_i, l_d_o`
246			`);`
247
248			`//`
249			`// Paraneters`
250			`//`
251			`parameter aw = 19;`
252
253			`//`
254			`// I/O Ports`
255			`//`
256			`input wb_clk_i;`
257			`input wb_rst_i;`
258
259			`//`
260			`// WB slave i/f`
261			`//`
262			`input [31:0] wb_dat_i;`
263			`output [31:0] wb_dat_o;`
264			`input [31:0] wb_adr_i;`
265			`input [3:0] wb_sel_i;`
266			`input wb_we_i;`
267			`input wb_cyc_i;`
268			`input wb_stb_i;`
269			`output wb_ack_o;`
270			`output wb_err_o;`
271
272			`//`
273			`// Right SRAM bank`
274			`//`
275			`output r_oen;`
276			`output r0_wen;`
277			`output r1_wen;`
278			`output r_cen;`
279			`input [15:0] r_d_i;`
280			`output [15:0] r_d_o;`
281			`output [aw-1:0] r_a;`
282
283			`//`
284			`// Left SRAM bank`
285			`//`
286			`output l_oen;`
287			`output l0_wen;`
288			`output l1_wen;`
289			`output l_cen;`
290			`input [15:0] l_d_i;`
291			`output [15:0] l_d_o;`
292			`output [aw-1:0] l_a;`
293
294			`//`
295			`// Common SRAM signals`
296			`//`
297			`output d_oe;`
298
299			`//`
300	746	lampret	`// Internal regs and wires`
301			`//`
302			`reg [15:0] r_data;`
303			`reg [15:0] l_data;`
304			`reg l0_wen;`
305			`wire l1_wen = l0_wen;`
306			`reg r0_wen;`
307			`wire r1_wen = r0_wen;`
308			`reg [31:0] latch_data;`
309			`reg ack_we;`
310			`wire l_oe;`
311			`wire r_oe;`
312			`wire r_ack;`
313			`reg Mux;`
314			`reg [aw-1:0] LatchedAddr;`
315			`reg [15:0] l_read;`
316			`reg [15:0] r_read;`
317			`reg d_oe;`
318			`reg [15:0] l_mux;`
319			`reg [15:0] r_mux;`
320
321			`//`
322			`// Aliases and simple assignments`
323			`//`
324			`assign wb_dat_o = {r_d_i, l_d_i};`
325			`assign l_oen = ~l_oe;`
326			`assign r_oen = ~r_oe;`
327			`assign l_a = Mux ? LatchedAddr : wb_adr_i[aw+1:2];`
328			`assign r_a = l_a;`
329			`assign l_d_o = l_mux;`
330			`assign r_d_o = r_mux;`
331			`assign l_oe = wb_cyc_i & wb_stb_i & l0_wen;`
332			`assign r_oe = wb_cyc_i & wb_stb_i & r0_wen;`
333			`assign l_cen = ~(wb_cyc_i & wb_stb_i);`
334			`assign r_cen = l_cen;`
335			`assign wb_ack_o = (wb_cyc_i & wb_stb_i & ~wb_we_i) \| ack_we;`
336			`assign wb_err_o = wb_cyc_i & wb_stb_i & (\|wb_adr_i[27:21]); // If Access to > 2MB (4-bit leading prefix ignored)`
337
338			`//`
339			`// RMW mux control`
340			`//`
341			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
342			`begin`
343			`if (wb_rst_i)`
344			`Mux <= 1'b0;`
345			`else`
346			`if (ack_we)`
347			`Mux <= #1 1'b1;`
348			`else`
349			`Mux <= #1 1'b0;`
350			`end`
351
352			`//`
353			`// Latch address`
354			`//`
355			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
356			`begin`
357			`if (wb_rst_i)`
358			`LatchedAddr <= 'h0;`
359			`else`
360			`if (wb_cyc_i & wb_stb_i)`
361			`LatchedAddr <= #1 wb_adr_i[aw+1:2];`
362			`end`
363
364			`//`
365			`// Latch data from RAM (read data)`
366			`//`
367			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
368			`begin`
369			`if (wb_rst_i)`
370			`begin`
371			`l_read <= 16'h0;`
372			`r_read <= 16'h0;`
373			`end`
374			`else`
375			`if (wb_cyc_i & wb_stb_i)`
376			`begin`
377			`l_read <= #1 l_d_i[15:0];`
378			`r_read <= #1 r_d_i[15:0];`
379			`end`
380			`end`
381
382			`//`
383			`// Mux and latch data for writing left SRAM bank (bytes 0 and 1)`
384			`//`
385			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
386			`begin`
387			`if (wb_rst_i)`
388			`l_mux <= 16'h0;`
389			`else`
390			`if (~l0_wen)`
391			`begin`
392			`if (wb_sel_i[0])`
393			`l_mux[7:0] <= #1 wb_dat_i[7:0];`
394			`else`
395			`l_mux[7:0] <= #1 l_read[7:0];`
396			`if (wb_sel_i[1])`
397			`l_mux[15:8] <= #1 wb_dat_i[15:8];`
398			`else`
399			`l_mux[15:8] <= #1 l_read[15:8];`
400			`end`
401			`else`
402			`l_mux[15:0] <= #1 16'hz;`
403			`end`
404
405			`//`
406			`// Mux and latch data for writing right SRAM bank (bytes 2 and 3)`
407			`//`
408			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
409			`begin`
410			`if (wb_rst_i)`
411			`r_mux <= 16'h0;`
412			`else`
413			`if (~r0_wen)`
414			`begin`
415			`if (wb_sel_i[2])`
416			`r_mux[7:0] <= #1 wb_dat_i[23:16];`
417			`else`
418			`r_mux[7:0] <= #1 r_read[7:0];`
419			`if (wb_sel_i[3])`
420			`r_mux[15:8] <= #1 wb_dat_i[31:24];`
421			`else`
422			`r_mux[15:8] <= #1 r_read[15:8];`
423			`end`
424			`else`
425			`r_mux <= #1 16'hz;`
426			`end`
427
428			`//`
429			`// Left WE`
430			`//`
431			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
432			`begin`
433			`if (wb_rst_i)`
434			`l0_wen <= 1'b1;`
435			`else`
436			`if (wb_cyc_i & wb_stb_i & wb_we_i & (\|wb_sel_i[1:0]) & ~wb_ack_o)`
437			`l0_wen <= #1 1'b0;`
438			`else`
439			`l0_wen <= #1 1'b1;`
440			`end`
441
442			`//`
443			`// Right WE`
444			`//`
445			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
446			`begin`
447			`if (wb_rst_i)`
448			`r0_wen <= 1'b1;`
449			`else`
450			`if (wb_cyc_i & wb_stb_i & wb_we_i & (\|wb_sel_i[3:2]) & ~wb_ack_o)`
451			`r0_wen <= #1 1'b0;`
452			`else`
453			`r0_wen <= #1 1'b1;`
454			`end`
455
456			`//`
457			`// Write acknowledge`
458			`//`
459			`always @ (posedge wb_clk_i or posedge wb_rst_i)`
460			`begin`
461			`if (wb_rst_i)`
462			`ack_we <= 1'b0;`
463			`else`
464			`if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)`
465			`ack_we <= #1 1'b1;`
466			`else`
467			`ack_we <= #1 1'b0;`
468			`end`
469
470			`//`
471			`// Generate d_oe signal (tristate control)`
472			`//`
473			`always @ (negedge wb_clk_i or posedge wb_rst_i)`
474			`begin`
475			`if (wb_rst_i)`
476			`d_oe <= 1'b0;`
477			`else`
478			`if (~l0_wen \| ~r0_wen)`
479			`d_oe <= 1'b1;`
480			`else`
481			`d_oe <= 1'b0;`
482			`end`
483
484			`//`
485			`// SRAM i/f monitor`
486			`//`
487			`// synopsys translate_off`
488			`integer fsram;`
489			`initial fsram = $fopen("sram.log");`
490			`always @(posedge wb_clk_i)`
491			`begin`
492			`if (~l0_wen \| ~r0_wen)`
493			`$fdisplay(fsram, "%t [%h] <- write %h", $time, wb_adr_i, {r_d_o, l_d_o});`
494			`else`
495			`if ((l_oe \| r_oe) & ~wb_we_i)`
496			`$fdisplay(fsram, "%t [%h] -> read %h", $time, wb_adr_i, {r_d_i, l_d_i});`
497			`end`
498			`// synopsys translate_on`
499
500			`endmodule`
501	946	lampret
502			`endif