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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's ALU                                                ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  ALU                                                         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.3  2002/01/28 01:15:59  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/12 01:45:40  lampret
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:45  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_alu(
        a, b, mult_mac_result, macrc_op,
        alu_op, shrot_op, comp_op,
        result, flagforw, flag_we
);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [width-1:0]              mult_mac_result;
input                           macrc_op;
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
input   [`OR1200_SHROTOP_WIDTH-1:0]      shrot_op;
input   [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
output  [width-1:0]              result;
output                          flagforw;
output                          flag_we;
 
//
// Internal wires and regs
//
reg     [width-1:0]              result;
reg     [width-1:0]              shifted_rotated;
reg                             flagforw;
reg                             flagcomp;
reg                             flag_we;
integer                         d1;
integer                         d2;
wire    [width-1:0]              comp_a;
wire    [width-1:0]              comp_b;
`ifdef OR1200_IMPL_ALU_COMP1
wire                            a_eq_b;
wire                            a_lt_b;
`endif
wire    [width-1:0]              result_sum;
wire    [width-1:0]              result_and;
 
//
// Combinatorial logic
//
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
assign result_sum = a + b;
assign result_and = a & b;
 
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
        if (result === 32'bx)
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
 
//
// Central part of the ALU
//
always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin
        casex (alu_op)          // synopsys parallel_case full_case
                `OR1200_ALUOP_SHROT : begin
                                result = shifted_rotated;
                end
                `OR1200_ALUOP_ADD : begin
                                result = result_sum;
                end
                `OR1200_ALUOP_SUB : begin
                                result = a - b;
                end
                `OR1200_ALUOP_XOR : begin
                                result = a ^ b;
                end
                `OR1200_ALUOP_OR  : begin
                                result = a | b;
                end
                `OR1200_ALUOP_IMM : begin
                                result = b;
                end
                `OR1200_ALUOP_MOVHI : begin
                                if (macrc_op) begin
                                        result = mult_mac_result;
                                end
                                else begin
                                        result = b << 16;
                                end
                end
                `OR1200_ALUOP_MUL : begin
                                result = mult_mac_result;
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result);
// synopsys translate_on
`endif
                end
// synopsys translate_off
`ifdef OR1200_SIM_ALU_DIV
                `OR1200_ALUOP_DIV : begin
                                d1 = a;
                                d2 = b;
                                $display("DIV operation: %d / %d = %d", d1, d2, d1/d2);
                                if (d2)
                                        result = d1 / d2;
                                else
                                        result = 32'h00000000;
                end
`endif
`ifdef OR1200_SIM_ALU_DIVU
                `OR1200_ALUOP_DIVU : begin
                                if (b)
                                        result = a / b;
                                else
                                        result = 32'h00000000;
                end
`endif
// synopsys translate_on
                `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
                                result = result_and;
                end
        endcase
end
 
//
// Generate flag and flag write enable
//
always @(alu_op or result_sum or result_and or flagcomp) begin
        casex (alu_op)          // synopsys parallel_case full_case
                `OR1200_ALUOP_ADD : begin
                        flagforw = (result_sum == 32'h0000_0000);
                        flag_we = 1'b0;
                end
                `OR1200_ALUOP_AND: begin
                        flagforw = (result_and == 32'h0000_0000);
                        flag_we = 1'b0;
                end
                `OR1200_ALUOP_COMP: begin
                        flagforw = flagcomp;
                        flag_we = 1'b1;
                end
                default: begin
                        flagforw = 1'b0;
                        flag_we = 1'b0;
                end
        endcase
end
 
//
// Shifts and rotation
//
always @(shrot_op or a or b) begin
        case (shrot_op)         // synopsys parallel_case
        `OR1200_SHROTOP_SLL :
                                shifted_rotated = (a << b[4:0]);
                `OR1200_SHROTOP_SRL :
                                shifted_rotated = (a >> b[4:0]);
 
`ifdef OR1200_IMPL_ALU_ROTATE
                `OR1200_SHROTOP_ROR :
                                shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) | (a >> b[4:0]);
`endif
                default:
                                shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) | a >> b[4:0];
        endcase
end
 
//
// First type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
        case(comp_op[2:0])       // synopsys parallel_case full_case
                `OR1200_COP_SFEQ:
                        flagcomp = a_eq_b;
                `OR1200_COP_SFNE:
                        flagcomp = ~a_eq_b;
                `OR1200_COP_SFGT:
                        flagcomp = ~(a_eq_b | a_lt_b);
                `OR1200_COP_SFGE:
                        flagcomp = ~a_lt_b;
                `OR1200_COP_SFLT:
                        flagcomp = a_lt_b;
                `OR1200_COP_SFLE:
                        flagcomp = a_eq_b | a_lt_b;
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
//
// Second type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP2
always @(comp_op or comp_a or comp_b) begin
        case(comp_op[2:0])       // synopsys parallel_case full_case
                `OR1200_COP_SFEQ:
                        flagcomp = (comp_a == comp_b);
                `OR1200_COP_SFNE:
                        flagcomp = (comp_a != comp_b);
                `OR1200_COP_SFGT:
                        flagcomp = (comp_a > comp_b);
                `OR1200_COP_SFGE:
                        flagcomp = (comp_a >= comp_b);
                `OR1200_COP_SFLT:
                        flagcomp = (comp_a < comp_b);
                `OR1200_COP_SFLE:
                        flagcomp = (comp_a <= comp_b);
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
endmodule

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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [or1200.old/] [or1200_alu.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's ALU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.3 2002/01/28 01:15:59 lampret`
48			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
49			`//`
50			`// Revision 1.2 2002/01/14 06:18:22 lampret`
51			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
52			`//`
53			`// Revision 1.1 2002/01/03 08:16:15 lampret`
54			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
55			`//`
56			`// Revision 1.10 2001/11/12 01:45:40 lampret`
57			`// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.`
58			`//`
59			`// Revision 1.9 2001/10/21 17:57:16 lampret`
60			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
61			`//`
62			`// Revision 1.8 2001/10/19 23:28:45 lampret`
63			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
64			`//`
65			`// Revision 1.7 2001/10/14 13:12:09 lampret`
66			`// MP3 version.`
67			`//`
68			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
69			`// no message`
70			`//`
71			`// Revision 1.2 2001/08/09 13:39:33 lampret`
72			`// Major clean-up.`
73			`//`
74			`// Revision 1.1 2001/07/20 00:46:03 lampret`
75			`// Development version of RTL. Libraries are missing.`
76			`//`
77			`//`
78
79			`// synopsys translate_off`
80			`include "timescale.v"
81			`// synopsys translate_on`
82			`include "or1200_defines.v"
83
84			`module or1200_alu(`
85			`a, b, mult_mac_result, macrc_op,`
86			`alu_op, shrot_op, comp_op,`
87			`result, flagforw, flag_we`
88			`);`
89
90			parameter width = `OR1200_OPERAND_WIDTH;
91
92			`//`
93			`// I/O`
94			`//`
95			`input [width-1:0] a;`
96			`input [width-1:0] b;`
97			`input [width-1:0] mult_mac_result;`
98			`input macrc_op;`
99			input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
100			input [`OR1200_SHROTOP_WIDTH-1:0] shrot_op;
101			input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
102			`output [width-1:0] result;`
103			`output flagforw;`
104			`output flag_we;`
105
106			`//`
107			`// Internal wires and regs`
108			`//`
109			`reg [width-1:0] result;`
110			`reg [width-1:0] shifted_rotated;`
111			`reg flagforw;`
112			`reg flagcomp;`
113			`reg flag_we;`
114			`integer d1;`
115			`integer d2;`
116			`wire [width-1:0] comp_a;`
117			`wire [width-1:0] comp_b;`
118			`ifdef OR1200_IMPL_ALU_COMP1
119			`wire a_eq_b;`
120			`wire a_lt_b;`
121			`endif
122			`wire [width-1:0] result_sum;`
123			`wire [width-1:0] result_and;`
124
125			`//`
126			`// Combinatorial logic`
127			`//`
128			`assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};`
129			`assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};`
130			`ifdef OR1200_IMPL_ALU_COMP1
131			`assign a_eq_b = (comp_a == comp_b);`
132			`assign a_lt_b = (comp_a < comp_b);`
133			`endif
134			`assign result_sum = a + b;`
135			`assign result_and = a & b;`
136
137			`//`
138			`// Simulation check for bad ALU behavior`
139			`//`
140			`ifdef OR1200_WARNINGS
141			`// synopsys translate_off`
142			`always @(result) begin`
143			`if (result === 32'bx)`
144			`$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);`
145			`end`
146			`// synopsys translate_on`
147			`endif
148
149			`//`
150			`// Central part of the ALU`
151			`//`
152			`always @(alu_op or a or b or result_sum or result_and or macrc_op or shifted_rotated or mult_mac_result) begin`
153			`casex (alu_op) // synopsys parallel_case full_case`
154			`OR1200_ALUOP_SHROT : begin
155			`result = shifted_rotated;`
156			`end`
157			`OR1200_ALUOP_ADD : begin
158			`result = result_sum;`
159			`end`
160			`OR1200_ALUOP_SUB : begin
161			`result = a - b;`
162			`end`
163			`OR1200_ALUOP_XOR : begin
164			`result = a ^ b;`
165			`end`
166			`OR1200_ALUOP_OR : begin
167			`result = a \| b;`
168			`end`
169			`OR1200_ALUOP_IMM : begin
170			`result = b;`
171			`end`
172			`OR1200_ALUOP_MOVHI : begin
173			`if (macrc_op) begin`
174			`result = mult_mac_result;`
175			`end`
176			`else begin`
177			`result = b << 16;`
178			`end`
179			`end`
180			`OR1200_ALUOP_MUL : begin
181			`result = mult_mac_result;`
182			`ifdef OR1200_VERBOSE
183			`// synopsys translate_off`
184			`$display("%t: MUL operation: %h * %h = %h", $time, a, b, mult_mac_result);`
185			`// synopsys translate_on`
186			`endif
187			`end`
188			`// synopsys translate_off`
189			`ifdef OR1200_SIM_ALU_DIV
190			`OR1200_ALUOP_DIV : begin
191			`d1 = a;`
192			`d2 = b;`
193			`$display("DIV operation: %d / %d = %d", d1, d2, d1/d2);`
194			`if (d2)`
195			`result = d1 / d2;`
196			`else`
197			`result = 32'h00000000;`
198			`end`
199			`endif
200			`ifdef OR1200_SIM_ALU_DIVU
201			`OR1200_ALUOP_DIVU : begin
202			`if (b)`
203			`result = a / b;`
204			`else`
205			`result = 32'h00000000;`
206			`end`
207			`endif
208			`// synopsys translate_on`
209			`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
210			`result = result_and;`
211			`end`
212			`endcase`
213			`end`
214
215			`//`
216			`// Generate flag and flag write enable`
217			`//`
218			`always @(alu_op or result_sum or result_and or flagcomp) begin`
219			`casex (alu_op) // synopsys parallel_case full_case`
220			`OR1200_ALUOP_ADD : begin
221			`flagforw = (result_sum == 32'h0000_0000);`
222			`flag_we = 1'b0;`
223			`end`
224			`OR1200_ALUOP_AND: begin
225			`flagforw = (result_and == 32'h0000_0000);`
226			`flag_we = 1'b0;`
227			`end`
228			`OR1200_ALUOP_COMP: begin
229			`flagforw = flagcomp;`
230			`flag_we = 1'b1;`
231			`end`
232			`default: begin`
233			`flagforw = 1'b0;`
234			`flag_we = 1'b0;`
235			`end`
236			`endcase`
237			`end`
238
239			`//`
240			`// Shifts and rotation`
241			`//`
242			`always @(shrot_op or a or b) begin`
243			`case (shrot_op) // synopsys parallel_case`
244			`OR1200_SHROTOP_SLL :
245			`shifted_rotated = (a << b[4:0]);`
246			`OR1200_SHROTOP_SRL :
247			`shifted_rotated = (a >> b[4:0]);`
248
249			`ifdef OR1200_IMPL_ALU_ROTATE
250			`OR1200_SHROTOP_ROR :
251			`shifted_rotated = (a << (6'd32-{1'b0, b[4:0]})) \| (a >> b[4:0]);`
252			`endif
253			`default:`
254			`shifted_rotated = ({32{a[31]}} << (6'd32-{1'b0, b[4:0]})) \| a >> b[4:0];`
255			`endcase`
256			`end`
257
258			`//`
259			`// First type of compare implementation`
260			`//`
261			`ifdef OR1200_IMPL_ALU_COMP1
262			`always @(comp_op or a_eq_b or a_lt_b) begin`
263			`case(comp_op[2:0]) // synopsys parallel_case full_case`
264			`OR1200_COP_SFEQ:
265			`flagcomp = a_eq_b;`
266			`OR1200_COP_SFNE:
267			`flagcomp = ~a_eq_b;`
268			`OR1200_COP_SFGT:
269			`flagcomp = ~(a_eq_b \| a_lt_b);`
270			`OR1200_COP_SFGE:
271			`flagcomp = ~a_lt_b;`
272			`OR1200_COP_SFLT:
273			`flagcomp = a_lt_b;`
274			`OR1200_COP_SFLE:
275			`flagcomp = a_eq_b \| a_lt_b;`
276			`default:`
277			`flagcomp = 1'b0;`
278			`endcase`
279			`end`
280			`endif
281
282			`//`
283			`// Second type of compare implementation`
284			`//`
285			`ifdef OR1200_IMPL_ALU_COMP2
286			`always @(comp_op or comp_a or comp_b) begin`
287			`case(comp_op[2:0]) // synopsys parallel_case full_case`
288			`OR1200_COP_SFEQ:
289			`flagcomp = (comp_a == comp_b);`
290			`OR1200_COP_SFNE:
291			`flagcomp = (comp_a != comp_b);`
292			`OR1200_COP_SFGT:
293			`flagcomp = (comp_a > comp_b);`
294			`OR1200_COP_SFGE:
295			`flagcomp = (comp_a >= comp_b);`
296			`OR1200_COP_SFLT:
297			`flagcomp = (comp_a < comp_b);`
298			`OR1200_COP_SFLE:
299			`flagcomp = (comp_a <= comp_b);`
300			`default:`
301			`flagcomp = 1'b0;`
302			`endcase`
303			`end`
304			`endif
305
306			`endmodule`