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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's DC FSM                                             ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Data cache state machine                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2002/02/11 04:33:17  lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4  2002/02/01 19:56:54  lampret
// Fixed combinational loops.
//
// Revision 1.3  2002/01/28 01:15:59  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`define OR1200_DCFSM_IDLE       3'd0
`define OR1200_DCFSM_CLOAD      3'd1
`define OR1200_DCFSM_LREFILL3   3'd2
`define OR1200_DCFSM_CSTORE     3'd3
`define OR1200_DCFSM_SREFILL4   3'd4
`define OR1200_DCFSM_ILOAD      3'd5
`define OR1200_DCFSM_ISTORE     3'd6
 
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
//
 
module or1200_dc_fsm(
        // Clock and reset
        clk, rst,
 
        // Internal i/f to top level DC
        dc_en, dcdmmu_cycstb_i, dcdmmu_ci_i, dcpu_we_i, dcpu_sel_i,
        tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
        dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,
        burst, tag_we, dc_addr
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           dc_en;
input                           dcdmmu_cycstb_i;
input                           dcdmmu_ci_i;
input                           dcpu_we_i;
input   [3:0]                    dcpu_sel_i;
input                           tagcomp_miss;
input                           biudata_valid;
input                           biudata_error;
input   [31:0]                   start_addr;
output  [31:0]                   saved_addr;
output  [3:0]                    dcram_we;
output                          biu_read;
output                          biu_write;
output                          first_hit_ack;
output                          first_miss_ack;
output                          first_miss_err;
output                          burst;
output                          tag_we;
output  [31:0]                   dc_addr;
 
//
// Internal wires and regs
//
reg     [31:0]                   saved_addr_r;
reg     [2:0]                    state;
reg     [2:0]                    cnt;
reg                             hitmiss_eval;
reg                             store;
reg                             load;
reg                             cache_inhibit;
wire                            first_store_hit_ack;
 
//
// Generate of DCRAM write enables
//
assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} | {4{first_store_hit_ack}} & dcpu_sel_i;
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
 
//
// BIU read and write
//
assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
assign biu_write = store;
 
assign dc_addr = (biu_read | biu_write) & !hitmiss_eval ? saved_addr : start_addr;
assign saved_addr = saved_addr_r;
 
//
// Assert for cache hit first word ready
// Assert for store cache hit first word ready
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//
assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss & !cache_inhibit & !dcdmmu_ci_i | first_store_hit_ack;
assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid & !cache_inhibit & !dcdmmu_ci_i;
assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) | (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
 
//
// Assert burst when doing reload of complete cache line
//
assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit
                | (state == `OR1200_DCFSM_LREFILL3)
`ifdef OR1200_DC_STORE_REFILL
                | (state == `OR1200_DCFSM_SREFILL4)
`endif
                ;
 
//
// Main DC FSM
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                state <= #1 `OR1200_DCFSM_IDLE;
                saved_addr_r <= #1 32'b0;
                hitmiss_eval <= #1 1'b0;
                store <= #1 1'b0;
                load <= #1 1'b0;
                cnt <= #1 3'b000;
                cache_inhibit <= #1 1'b0;
        end
        else
        case (state)    // synopsys parallel_case
                `OR1200_DCFSM_IDLE :
                        if (dc_en & dcdmmu_cycstb_i & dcpu_we_i) begin  // store
                                state <= #1 `OR1200_DCFSM_CSTORE;
                                saved_addr_r <= #1 start_addr;
                                hitmiss_eval <= #1 1'b1;
                                store <= #1 1'b1;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (dc_en & dcdmmu_cycstb_i) begin         // load
                                state <= #1 `OR1200_DCFSM_CLOAD;
                                saved_addr_r <= #1 start_addr;
                                hitmiss_eval <= #1 1'b1;
                                store <= #1 1'b0;
                                load <= #1 1'b1;
                                cache_inhibit <= #1 1'b0;
                        end
                        else begin                                                      // idle
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                `OR1200_DCFSM_CLOAD: begin              // load
                        if (dcdmmu_cycstb_i & dcdmmu_ci_i)
                                cache_inhibit <= #1 1'b1;
                        if (hitmiss_eval)
                                saved_addr_r[31:13] <= #1 start_addr[31:13];
                        if (!dc_en)
                                state <= #1 `OR1200_DCFSM_IDLE;
                        else if (hitmiss_eval & !dcdmmu_cycstb_i) begin // load aborted (usually caused by DMMU)
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (biudata_error) begin                   // load terminated with an error
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if ((cache_inhibit | dcdmmu_ci_i) & biudata_valid) begin   // load from cache-inhibited area
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (tagcomp_miss & biudata_valid) begin    // load missed, finish current external load and refill
                                state <= #1 `OR1200_DCFSM_LREFILL3;
                                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
                                hitmiss_eval <= #1 1'b0;
                                cnt <= #1 `OR1200_DCLS-2;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (!tagcomp_miss & !dcdmmu_ci_i) begin    // load hit, finish immediately
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else                                            // load in-progress
                                hitmiss_eval <= #1 1'b0;
                end
                `OR1200_DCFSM_LREFILL3 : begin
                        if (!dc_en)
                                state <= #1 `OR1200_DCFSM_IDLE;
                        else if (biudata_valid && (|cnt)) begin         // refill ack, more loads to come
                                cnt <= #1 cnt - 'd1;
                                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
                        end
                        else if (biudata_valid) begin                   // last load of line refill
                                state <= #1 `OR1200_DCFSM_IDLE;
                                load <= #1 1'b0;
                        end
                end
                `OR1200_DCFSM_CSTORE: begin             // store
                        if (dcdmmu_cycstb_i & dcdmmu_ci_i)
                                cache_inhibit <= #1 1'b1;
                        if (hitmiss_eval)
                                saved_addr_r[31:13] <= #1 start_addr[31:13];
                        if (!dc_en)
                                state <= #1 `OR1200_DCFSM_IDLE;
                        else if (hitmiss_eval & !dcdmmu_cycstb_i) begin // store aborted (usually caused by DMMU)
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (biudata_error) begin                   // store terminated with an error
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if ((cache_inhibit | dcdmmu_ci_i) & biudata_valid) begin   // store to cache-inhibited area
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
`ifdef OR1200_DC_STORE_REFILL
                        else if (tagcomp_miss & biudata_valid) begin    // store missed, finish write-through and do load refill
                                state <= #1 `OR1200_DCFSM_SREFILL4;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                load <= #1 1'b1;
                                cnt <= #1 `OR1200_DCLS-1;
                                cache_inhibit <= #1 1'b0;
                        end
`endif
                        else if (biudata_valid) begin                   // store hit, finish write-through
                                state <= #1 `OR1200_DCFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                store <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else                                            // store write-through in-progress
                                hitmiss_eval <= #1 1'b0;
                        end
`ifdef OR1200_DC_STORE_REFILL
                `OR1200_DCFSM_SREFILL4 : begin
                        if (!dc_en)
                                state <= #1 `OR1200_DCFSM_IDLE;
                        else if (biudata_valid && (|cnt)) begin         // refill ack, more loads to come
                                cnt <= #1 cnt - 'd1;
                                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
                        end
                        else if (biudata_valid) begin                   // last load of line refill
                                state <= #1 `OR1200_DCFSM_IDLE;
                                load <= #1 1'b0;
                        end
                end
`endif
                default:
                        state <= #1 `OR1200_DCFSM_IDLE;
        endcase
end
 
endmodule

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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [or1200.old/] [or1200_dc_fsm.v] - Blame information for rev 746

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's DC FSM ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Data cache state machine ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.5 2002/02/11 04:33:17 lampret`
48			`// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.`
49			`//`
50			`// Revision 1.4 2002/02/01 19:56:54 lampret`
51			`// Fixed combinational loops.`
52			`//`
53			`// Revision 1.3 2002/01/28 01:15:59 lampret`
54			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
55			`//`
56			`// Revision 1.2 2002/01/14 06:18:22 lampret`
57			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
58			`//`
59			`// Revision 1.1 2002/01/03 08:16:15 lampret`
60			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
61			`//`
62			`// Revision 1.9 2001/10/21 17:57:16 lampret`
63			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
64			`//`
65			`// Revision 1.8 2001/10/19 23:28:46 lampret`
66			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
67			`//`
68			`// Revision 1.7 2001/10/14 13:12:09 lampret`
69			`// MP3 version.`
70			`//`
71			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
72			`// no message`
73			`//`
74			`// Revision 1.2 2001/08/09 13:39:33 lampret`
75			`// Major clean-up.`
76			`//`
77			`// Revision 1.1 2001/07/20 00:46:03 lampret`
78			`// Development version of RTL. Libraries are missing.`
79			`//`
80			`//`
81
82			`// synopsys translate_off`
83			`include "timescale.v"
84			`// synopsys translate_on`
85			`include "or1200_defines.v"
86
87			`define OR1200_DCFSM_IDLE 3'd0
88			`define OR1200_DCFSM_CLOAD 3'd1
89			`define OR1200_DCFSM_LREFILL3 3'd2
90			`define OR1200_DCFSM_CSTORE 3'd3
91			`define OR1200_DCFSM_SREFILL4 3'd4
92			`define OR1200_DCFSM_ILOAD 3'd5
93			`define OR1200_DCFSM_ISTORE 3'd6
94
95			`//`
96			`// Data cache FSM for cache line of 16 bytes (4x singleword)`
97			`//`
98
99			`module or1200_dc_fsm(`
100			`// Clock and reset`
101			`clk, rst,`
102
103			`// Internal i/f to top level DC`
104			`dc_en, dcdmmu_cycstb_i, dcdmmu_ci_i, dcpu_we_i, dcpu_sel_i,`
105			`tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,`
106			`dcram_we, biu_read, biu_write, first_hit_ack, first_miss_ack, first_miss_err,`
107			`burst, tag_we, dc_addr`
108			`);`
109
110			`//`
111			`// I/O`
112			`//`
113			`input clk;`
114			`input rst;`
115			`input dc_en;`
116			`input dcdmmu_cycstb_i;`
117			`input dcdmmu_ci_i;`
118			`input dcpu_we_i;`
119			`input [3:0] dcpu_sel_i;`
120			`input tagcomp_miss;`
121			`input biudata_valid;`
122			`input biudata_error;`
123			`input [31:0] start_addr;`
124			`output [31:0] saved_addr;`
125			`output [3:0] dcram_we;`
126			`output biu_read;`
127			`output biu_write;`
128			`output first_hit_ack;`
129			`output first_miss_ack;`
130			`output first_miss_err;`
131			`output burst;`
132			`output tag_we;`
133			`output [31:0] dc_addr;`
134
135			`//`
136			`// Internal wires and regs`
137			`//`
138			`reg [31:0] saved_addr_r;`
139			`reg [2:0] state;`
140			`reg [2:0] cnt;`
141			`reg hitmiss_eval;`
142			`reg store;`
143			`reg load;`
144			`reg cache_inhibit;`
145			`wire first_store_hit_ack;`
146
147			`//`
148			`// Generate of DCRAM write enables`
149			`//`
150			`assign dcram_we = {4{load & biudata_valid & !cache_inhibit}} \| {4{first_store_hit_ack}} & dcpu_sel_i;`
151			`assign tag_we = biu_read & biudata_valid & !cache_inhibit;`
152
153			`//`
154			`// BIU read and write`
155			`//`
156			`assign biu_read = (hitmiss_eval & tagcomp_miss) \| (!hitmiss_eval & load);`
157			`assign biu_write = store;`
158
159			`assign dc_addr = (biu_read \| biu_write) & !hitmiss_eval ? saved_addr : start_addr;`
160			`assign saved_addr = saved_addr_r;`
161
162			`//`
163			`// Assert for cache hit first word ready`
164			`// Assert for store cache hit first word ready`
165			`// Assert for cache miss first word stored/loaded OK`
166			`// Assert for cache miss first word stored/loaded with an error`
167			`//`
168			assign first_hit_ack = (state == `OR1200_DCFSM_CLOAD) & !tagcomp_miss & !cache_inhibit & !dcdmmu_ci_i \| first_store_hit_ack;
169			assign first_store_hit_ack = (state == `OR1200_DCFSM_CSTORE) & !tagcomp_miss & biudata_valid & !cache_inhibit & !dcdmmu_ci_i;
170			assign first_miss_ack = ((state == `OR1200_DCFSM_CLOAD) \| (state == `OR1200_DCFSM_CSTORE)) & biudata_valid;
171			assign first_miss_err = ((state == `OR1200_DCFSM_CLOAD) \| (state == `OR1200_DCFSM_CSTORE)) & biudata_error;
172
173			`//`
174			`// Assert burst when doing reload of complete cache line`
175			`//`
176			assign burst = (state == `OR1200_DCFSM_CLOAD) & tagcomp_miss & !cache_inhibit
177			\| (state == `OR1200_DCFSM_LREFILL3)
178			`ifdef OR1200_DC_STORE_REFILL
179			\| (state == `OR1200_DCFSM_SREFILL4)
180			`endif
181			`;`
182
183			`//`
184			`// Main DC FSM`
185			`//`
186			`always @(posedge clk or posedge rst) begin`
187			`if (rst) begin`
188			state <= #1 `OR1200_DCFSM_IDLE;
189			`saved_addr_r <= #1 32'b0;`
190			`hitmiss_eval <= #1 1'b0;`
191			`store <= #1 1'b0;`
192			`load <= #1 1'b0;`
193			`cnt <= #1 3'b000;`
194			`cache_inhibit <= #1 1'b0;`
195			`end`
196			`else`
197			`case (state) // synopsys parallel_case`
198			`OR1200_DCFSM_IDLE :
199			`if (dc_en & dcdmmu_cycstb_i & dcpu_we_i) begin // store`
200			state <= #1 `OR1200_DCFSM_CSTORE;
201			`saved_addr_r <= #1 start_addr;`
202			`hitmiss_eval <= #1 1'b1;`
203			`store <= #1 1'b1;`
204			`load <= #1 1'b0;`
205			`cache_inhibit <= #1 1'b0;`
206			`end`
207			`else if (dc_en & dcdmmu_cycstb_i) begin // load`
208			state <= #1 `OR1200_DCFSM_CLOAD;
209			`saved_addr_r <= #1 start_addr;`
210			`hitmiss_eval <= #1 1'b1;`
211			`store <= #1 1'b0;`
212			`load <= #1 1'b1;`
213			`cache_inhibit <= #1 1'b0;`
214			`end`
215			`else begin // idle`
216			state <= #1 `OR1200_DCFSM_IDLE;
217			`hitmiss_eval <= #1 1'b0;`
218			`store <= #1 1'b0;`
219			`load <= #1 1'b0;`
220			`cache_inhibit <= #1 1'b0;`
221			`end`
222			`OR1200_DCFSM_CLOAD: begin // load
223			`if (dcdmmu_cycstb_i & dcdmmu_ci_i)`
224			`cache_inhibit <= #1 1'b1;`
225			`if (hitmiss_eval)`
226			`saved_addr_r[31:13] <= #1 start_addr[31:13];`
227			`if (!dc_en)`
228			state <= #1 `OR1200_DCFSM_IDLE;
229			`else if (hitmiss_eval & !dcdmmu_cycstb_i) begin // load aborted (usually caused by DMMU)`
230			state <= #1 `OR1200_DCFSM_IDLE;
231			`hitmiss_eval <= #1 1'b0;`
232			`load <= #1 1'b0;`
233			`cache_inhibit <= #1 1'b0;`
234			`end`
235			`else if (biudata_error) begin // load terminated with an error`
236			state <= #1 `OR1200_DCFSM_IDLE;
237			`hitmiss_eval <= #1 1'b0;`
238			`load <= #1 1'b0;`
239			`cache_inhibit <= #1 1'b0;`
240			`end`
241			`else if ((cache_inhibit \| dcdmmu_ci_i) & biudata_valid) begin // load from cache-inhibited area`
242			state <= #1 `OR1200_DCFSM_IDLE;
243			`hitmiss_eval <= #1 1'b0;`
244			`load <= #1 1'b0;`
245			`cache_inhibit <= #1 1'b0;`
246			`end`
247			`else if (tagcomp_miss & biudata_valid) begin // load missed, finish current external load and refill`
248			state <= #1 `OR1200_DCFSM_LREFILL3;
249			`saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;`
250			`hitmiss_eval <= #1 1'b0;`
251			cnt <= #1 `OR1200_DCLS-2;
252			`cache_inhibit <= #1 1'b0;`
253			`end`
254			`else if (!tagcomp_miss & !dcdmmu_ci_i) begin // load hit, finish immediately`
255			state <= #1 `OR1200_DCFSM_IDLE;
256			`hitmiss_eval <= #1 1'b0;`
257			`load <= #1 1'b0;`
258			`cache_inhibit <= #1 1'b0;`
259			`end`
260			`else // load in-progress`
261			`hitmiss_eval <= #1 1'b0;`
262			`end`
263			`OR1200_DCFSM_LREFILL3 : begin
264			`if (!dc_en)`
265			state <= #1 `OR1200_DCFSM_IDLE;
266			`else if (biudata_valid && (\|cnt)) begin // refill ack, more loads to come`
267			`cnt <= #1 cnt - 'd1;`
268			`saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;`
269			`end`
270			`else if (biudata_valid) begin // last load of line refill`
271			state <= #1 `OR1200_DCFSM_IDLE;
272			`load <= #1 1'b0;`
273			`end`
274			`end`
275			`OR1200_DCFSM_CSTORE: begin // store
276			`if (dcdmmu_cycstb_i & dcdmmu_ci_i)`
277			`cache_inhibit <= #1 1'b1;`
278			`if (hitmiss_eval)`
279			`saved_addr_r[31:13] <= #1 start_addr[31:13];`
280			`if (!dc_en)`
281			state <= #1 `OR1200_DCFSM_IDLE;
282			`else if (hitmiss_eval & !dcdmmu_cycstb_i) begin // store aborted (usually caused by DMMU)`
283			state <= #1 `OR1200_DCFSM_IDLE;
284			`hitmiss_eval <= #1 1'b0;`
285			`store <= #1 1'b0;`
286			`cache_inhibit <= #1 1'b0;`
287			`end`
288			`else if (biudata_error) begin // store terminated with an error`
289			state <= #1 `OR1200_DCFSM_IDLE;
290			`hitmiss_eval <= #1 1'b0;`
291			`store <= #1 1'b0;`
292			`cache_inhibit <= #1 1'b0;`
293			`end`
294			`else if ((cache_inhibit \| dcdmmu_ci_i) & biudata_valid) begin // store to cache-inhibited area`
295			state <= #1 `OR1200_DCFSM_IDLE;
296			`hitmiss_eval <= #1 1'b0;`
297			`store <= #1 1'b0;`
298			`cache_inhibit <= #1 1'b0;`
299			`end`
300			`ifdef OR1200_DC_STORE_REFILL
301			`else if (tagcomp_miss & biudata_valid) begin // store missed, finish write-through and do load refill`
302			state <= #1 `OR1200_DCFSM_SREFILL4;
303			`hitmiss_eval <= #1 1'b0;`
304			`store <= #1 1'b0;`
305			`load <= #1 1'b1;`
306			cnt <= #1 `OR1200_DCLS-1;
307			`cache_inhibit <= #1 1'b0;`
308			`end`
309			`endif
310			`else if (biudata_valid) begin // store hit, finish write-through`
311			state <= #1 `OR1200_DCFSM_IDLE;
312			`hitmiss_eval <= #1 1'b0;`
313			`store <= #1 1'b0;`
314			`cache_inhibit <= #1 1'b0;`
315			`end`
316			`else // store write-through in-progress`
317			`hitmiss_eval <= #1 1'b0;`
318			`end`
319			`ifdef OR1200_DC_STORE_REFILL
320			`OR1200_DCFSM_SREFILL4 : begin
321			`if (!dc_en)`
322			state <= #1 `OR1200_DCFSM_IDLE;
323			`else if (biudata_valid && (\|cnt)) begin // refill ack, more loads to come`
324			`cnt <= #1 cnt - 'd1;`
325			`saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;`
326			`end`
327			`else if (biudata_valid) begin // last load of line refill`
328			state <= #1 `OR1200_DCFSM_IDLE;
329			`load <= #1 1'b0;`
330			`end`
331			`end`
332			`endif
333			`default:`
334			state <= #1 `OR1200_DCFSM_IDLE;
335			`endcase`
336			`end`
337
338			`endmodule`