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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [or1200.old/] [or1200_dc_ram.v] - Blame information for rev 1765

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's DC RAMs                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instatiation of DC RAM blocks.                              ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_dc_ram(
        // Reset and clock
        clk, rst,
 
        // Internal i/f
        addr, en, we, datain, dataout
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_DCINDX;
 
//
// I/O
//
input                           clk;
input                           rst;
input   [aw-1:0]         addr;
input                           en;
input   [3:0]                    we;
input   [dw-1:0]         datain;
output  [dw-1:0]         dataout;
 
`ifdef OR1200_NO_DC
 
//
// Data cache not implemented
//
 
assign dataout = {dw{1'b0}};
 
`else
 
//
// Instantiation of RAM block 0
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_1024x8 dc_ram0(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x8 dc_ram0(
`endif
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[0]),
        .oe(1'b1),
        .addr(addr),
        .di(datain[7:0]),
        .do(dataout[7:0])
);
 
//
// Instantiation of RAM block 1
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_1024x8 dc_ram1(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x8 dc_ram1(
`endif
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[1]),
        .oe(1'b1),
        .addr(addr),
        .di(datain[15:8]),
        .do(dataout[15:8])
);
 
//
// Instantiation of RAM block 2
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_1024x8 dc_ram2(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x8 dc_ram2(
`endif
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[2]),
        .oe(1'b1),
        .addr(addr),
        .di(datain[23:16]),
        .do(dataout[23:16])
);
 
//
// Instantiation of RAM block 3
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_1024x8 dc_ram3(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x8 dc_ram3(
`endif
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we[3]),
        .oe(1'b1),
        .addr(addr),
        .di(datain[31:24]),
        .do(dataout[31:24])
);
 
`endif
 
endmodule

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's DC RAMs ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instatiation of DC RAM blocks. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.1 2002/01/03 08:16:15 lampret`
48			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
49			`//`
50			`// Revision 1.8 2001/10/21 17:57:16 lampret`
51			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
52			`//`
53			`// Revision 1.7 2001/10/14 13:12:09 lampret`
54			`// MP3 version.`
55			`//`
56			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
57			`// no message`
58			`//`
59			`// Revision 1.2 2001/08/09 13:39:33 lampret`
60			`// Major clean-up.`
61			`//`
62			`// Revision 1.1 2001/07/20 00:46:03 lampret`
63			`// Development version of RTL. Libraries are missing.`
64			`//`
65			`//`
66
67			`// synopsys translate_off`
68			`include "timescale.v"
69			`// synopsys translate_on`
70			`include "or1200_defines.v"
71
72			`module or1200_dc_ram(`
73			`// Reset and clock`
74			`clk, rst,`
75
76			`// Internal i/f`
77			`addr, en, we, datain, dataout`
78			`);`
79
80			parameter dw = `OR1200_OPERAND_WIDTH;
81			parameter aw = `OR1200_DCINDX;
82
83			`//`
84			`// I/O`
85			`//`
86			`input clk;`
87			`input rst;`
88			`input [aw-1:0] addr;`
89			`input en;`
90			`input [3:0] we;`
91			`input [dw-1:0] datain;`
92			`output [dw-1:0] dataout;`
93
94			`ifdef OR1200_NO_DC
95
96			`//`
97			`// Data cache not implemented`
98			`//`
99
100			`assign dataout = {dw{1'b0}};`
101
102			`else
103
104			`//`
105			`// Instantiation of RAM block 0`
106			`//`
107			`ifdef OR1200_DC_1W_4KB
108			`or1200_spram_1024x8 dc_ram0(`
109			`endif
110			`ifdef OR1200_DC_1W_8KB
111			`or1200_spram_2048x8 dc_ram0(`
112			`endif
113			`.clk(clk),`
114			`.rst(rst),`
115			`.ce(en),`
116			`.we(we[0]),`
117			`.oe(1'b1),`
118			`.addr(addr),`
119			`.di(datain[7:0]),`
120			`.do(dataout[7:0])`
121			`);`
122
123			`//`
124			`// Instantiation of RAM block 1`
125			`//`
126			`ifdef OR1200_DC_1W_4KB
127			`or1200_spram_1024x8 dc_ram1(`
128			`endif
129			`ifdef OR1200_DC_1W_8KB
130			`or1200_spram_2048x8 dc_ram1(`
131			`endif
132			`.clk(clk),`
133			`.rst(rst),`
134			`.ce(en),`
135			`.we(we[1]),`
136			`.oe(1'b1),`
137			`.addr(addr),`
138			`.di(datain[15:8]),`
139			`.do(dataout[15:8])`
140			`);`
141
142			`//`
143			`// Instantiation of RAM block 2`
144			`//`
145			`ifdef OR1200_DC_1W_4KB
146			`or1200_spram_1024x8 dc_ram2(`
147			`endif
148			`ifdef OR1200_DC_1W_8KB
149			`or1200_spram_2048x8 dc_ram2(`
150			`endif
151			`.clk(clk),`
152			`.rst(rst),`
153			`.ce(en),`
154			`.we(we[2]),`
155			`.oe(1'b1),`
156			`.addr(addr),`
157			`.di(datain[23:16]),`
158			`.do(dataout[23:16])`
159			`);`
160
161			`//`
162			`// Instantiation of RAM block 3`
163			`//`
164			`ifdef OR1200_DC_1W_4KB
165			`or1200_spram_1024x8 dc_ram3(`
166			`endif
167			`ifdef OR1200_DC_1W_8KB
168			`or1200_spram_2048x8 dc_ram3(`
169			`endif
170			`.clk(clk),`
171			`.rst(rst),`
172			`.ce(en),`
173			`.we(we[3]),`
174			`.oe(1'b1),`
175			`.addr(addr),`
176			`.di(datain[31:24]),`
177			`.do(dataout[31:24])`
178			`);`
179
180			`endif
181
182			`endmodule`

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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [or1200.old/] [or1200_dc_ram.v] - Blame information for rev 1765