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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Debug Unit                                         ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Basic OR1200 debug unit.                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2002/03/14 00:30:24  lampret
// Added alternative for critical path in DU.
//
// Revision 1.5  2002/02/11 04:33:17  lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4  2002/01/28 01:16:00  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.3  2002/01/18 07:56:00  lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.12  2001/11/30 18:58:00  simons
// Trap insn couses break after exits ex_insn.
//
// Revision 1.11  2001/11/23 08:38:51  lampret
// Changed DSR/DRR behavior and exception detection.
//
// Revision 1.10  2001/11/20 21:25:44  lampret
// Fixed dbg_is_o assignment width.
//
// Revision 1.9  2001/11/20 18:46:14  simons
// Break point bug fixed
//
// Revision 1.8  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.7  2001/10/21 18:09:53  lampret
// Fixed sensitivity list.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
//
// Debug unit
//
 
module or1200_du(
        // RISC Internal Interface
        clk, rst,
        dcpu_cycstb_i, dcpu_we_i,
        icpu_cycstb_i, ex_freeze, branch_op, ex_insn, du_dsr,
        du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write, du_except,
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
 
        // External Debug Interface
        dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,
        dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// RISC Internal Interface
//
input                           clk;            // Clock
input                           rst;            // Reset
input                           dcpu_cycstb_i;  // LSU status
input                           dcpu_we_i;      // LSU status
input   [`OR1200_FETCHOP_WIDTH-1:0]      icpu_cycstb_i;  // IFETCH unit status
input                           ex_freeze;      // EX stage freeze
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;      // Branch op
input   [dw-1:0]         ex_insn;        // EX insn
output  [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;           // DSR
output                          du_stall;       // Debug Unit Stall
output  [aw-1:0]         du_addr;        // Debug Unit Address
input   [dw-1:0]         du_dat_i;       // Debug Unit Data In
output  [dw-1:0]         du_dat_o;       // Debug Unit Data Out
output                          du_read;        // Debug Unit Read Enable
output                          du_write;       // Debug Unit Write Enable
input   [12:0]                   du_except;      // Exception masked by DSR
input                           spr_cs;         // SPR Chip Select
input                           spr_write;      // SPR Read/Write
input   [aw-1:0]         spr_addr;       // SPR Address
input   [dw-1:0]         spr_dat_i;      // SPR Data Input
output  [dw-1:0]         spr_dat_o;      // SPR Data Output
 
//
// External Debug Interface
//
input                           dbg_stall_i;    // External Stall Input
input   [dw-1:0]         dbg_dat_i;      // External Data Input
input   [aw-1:0]         dbg_adr_i;      // External Address Input
input   [2:0]                    dbg_op_i;       // External Operation Select Input
input                           dbg_ewt_i;      // External Watchpoint Trigger Input
output  [3:0]                    dbg_lss_o;      // External Load/Store Unit Status
output  [1:0]                    dbg_is_o;       // External Insn Fetch Status
output  [10:0]                   dbg_wp_o;       // Watchpoints Outputs
output                          dbg_bp_o;       // Breakpoint Output
output  [dw-1:0]         dbg_dat_o;      // External Data Output
 
 
//
// Some connections go directly from the CPU through DU to Debug I/F
//
`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
assign dbg_lss_o = 4'b0000;
assign dbg_is_o = 2'b00;
`else
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
assign dbg_is_o = {1'b0, icpu_cycstb_i};
`endif
assign dbg_wp_o = 11'b000_0000_0000;
assign dbg_dat_o = du_dat_i;
 
//
// Some connections go directly from Debug I/F through DU to the CPU
//
assign du_stall = dbg_stall_i;
assign du_addr = dbg_adr_i;
assign du_dat_o = dbg_dat_i;
assign du_read = (dbg_op_i == `OR1200_DU_OP_READSPR);
assign du_write = (dbg_op_i == `OR1200_DU_OP_WRITESPR);
 
`ifdef OR1200_DU_IMPLEMENTED
 
//
// Debug Mode Register 1 (only ST and BT implemented)
//
`ifdef OR1200_DU_DMR1
reg     [23:22]                 dmr1;           // DMR1 implemented (ST & BT)
`else
wire    [23:22]                 dmr1;           // DMR1 not implemented
`endif
 
//
// Debug Mode Register 2 (not implemented)
//
`ifdef OR1200_DU_DMR2
wire    [31:0]                   dmr2;           // DMR not implemented
`endif
 
//
// Debug Stop Register
//
`ifdef OR1200_DU_DSR
reg     [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR implemented
`else
wire    [`OR1200_DU_DSR_WIDTH-1:0]       dsr;            // DSR not implemented
`endif
 
//
// Debug Reason Register
//
`ifdef OR1200_DU_DRR
reg     [13:0]                   drr;            // DRR implemented
`else
wire    [13:0]                   drr;            // DRR not implemented
`endif
 
//
// Internal wires
//
wire                            dmr1_sel;       // DMR1 select
wire                            dsr_sel;        // DSR select
wire                            drr_sel;        // DRR select
reg                             dbg_bp_r;
`ifdef OR1200_DU_READREGS
reg     [31:0]                   spr_dat_o;
`endif
reg     [13:0]                   except_stop;    // Exceptions that stop because of DSR
 
//
// DU registers address decoder
//
`ifdef OR1200_DU_DMR1
assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DMR1));
`endif
`ifdef OR1200_DU_DSR
assign dsr_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DSR));
`endif
`ifdef OR1200_DU_DRR
assign drr_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DRR));
`endif
 
//
// Decode started exception
//
always @(du_except) begin
        except_stop = 14'b0000_0000_0000;
        casex (du_except)
                13'b1_xxxx_xxxx_xxxx:
                        except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
                13'b0_1xxx_xxxx_xxxx: begin
                        except_stop[`OR1200_DU_DRR_IE] = 1'b1;
                end
                13'b0_01xx_xxxx_xxxx: begin
                        except_stop[`OR1200_DU_DRR_IME] = 1'b1;
                end
                13'b0_001x_xxxx_xxxx:
                        except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
                13'b0_0001_xxxx_xxxx: begin
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
                end
                13'b0_0000_1xxx_xxxx:
                        except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
                13'b0_0000_01xx_xxxx: begin
                        except_stop[`OR1200_DU_DRR_AE] = 1'b1;
                end
                13'b0_0000_001x_xxxx: begin
                        except_stop[`OR1200_DU_DRR_DME] = 1'b1;
                end
                13'b0_0000_0001_xxxx:
                        except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
                13'b0_0000_0000_1xxx:
                        except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
                13'b0_0000_0000_01xx: begin
                        except_stop[`OR1200_DU_DRR_RE] = 1'b1;
                end
                13'b0_0000_0000_001x: begin
                        except_stop[`OR1200_DU_DRR_TE] = 1'b1;
                end
                13'b0_0000_0000_0001:
                        except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
                default:
                        except_stop = 14'b0000_0000_0000;
        endcase
end
 
//
// dbg_bp_o is registered
//
assign dbg_bp_o = dbg_bp_r;
 
//
// Breakpoint activation register
//
always @(posedge clk or posedge rst)
        if (rst)
                dbg_bp_r <= #1 1'b0;
        else if (!ex_freeze)
                dbg_bp_r <= #1 |except_stop
`ifdef OR1200_DU_DMR1_ST
                        | ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
`endif
`ifdef OR1200_DU_DMR1_BT
                        | (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
`endif
                        ;
        else
                dbg_bp_r <= #1 |except_stop;
 
//
// Write to DMR1
//
`ifdef OR1200_DU_DMR1
always @(posedge clk or posedge rst)
        if (rst)
                dmr1 <= 2'b00;
        else if (dmr1_sel && spr_write)
                dmr1 <= #1 spr_dat_i[23:22];
`else
assign dmr1 = 2'b00;
`endif
 
//
// DMR2 bits tied to zero
//
`ifdef OR1200_DU_DMR2
assign dmr2 = 32'h0000_0000;
`endif
 
//
// Write to DSR
//
`ifdef OR1200_DU_DSR
always @(posedge clk or posedge rst)
        if (rst)
                dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
        else if (dsr_sel && spr_write)
                dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
`else
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
`endif
 
//
// Write to DRR
//
`ifdef OR1200_DU_DRR
always @(posedge clk or posedge rst)
        if (rst)
                drr <= 14'b0;
        else if (drr_sel && spr_write)
                drr <= #1 spr_dat_i[13:0];
        else
                drr <= #1 drr | except_stop;
`else
assign drr = 14'b0;
`endif
 
//
// Read DU registers
//
`ifdef OR1200_DU_READREGS
always @(spr_addr or dsr or drr or dmr1 or dmr2)
        case (spr_addr[`OR1200_SPR_OFS_BITS])
`ifdef OR1200_DU_DMR1
                `OR1200_DU_OFS_DMR1:
                        spr_dat_o = {8'b0, dmr1, 22'b0};
`endif
`ifdef OR1200_DU_DMR2
                `OR1200_DU_OFS_DMR2:
                        spr_dat_o = dmr2;
`endif
`ifdef OR1200_DU_DSR
                `OR1200_DU_OFS_DSR:
                        spr_dat_o = {18'b0, dsr};
`endif
`ifdef OR1200_DU_DRR
                `OR1200_DU_OFS_DRR:
                        spr_dat_o = {18'b0, drr};
`endif
                default:
                        spr_dat_o = 32'h0000_0000;
        endcase
`endif
 
//
// DSR alias
//
assign du_dsr = dsr;
 
`else
 
//
// When DU is not implemented, drive all outputs as would when DU is disabled
//
assign dbg_bp_o = 1'b0;
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
 
//
// Read DU registers
//
`ifdef OR1200_DU_READREGS
assign spr_dat_o = 32'h0000_0000;
`ifdef OR1200_DU_UNUSED_ZERO
`endif
`endif
 
`endif
 
endmodule

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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [or1200.old/] [or1200_du.v] - Blame information for rev 746

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Debug Unit ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Basic OR1200 debug unit. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.6 2002/03/14 00:30:24 lampret`
48			`// Added alternative for critical path in DU.`
49			`//`
50			`// Revision 1.5 2002/02/11 04:33:17 lampret`
51			`// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.`
52			`//`
53			`// Revision 1.4 2002/01/28 01:16:00 lampret`
54			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
55			`//`
56			`// Revision 1.3 2002/01/18 07:56:00 lampret`
57			`// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.`
58			`//`
59			`// Revision 1.2 2002/01/14 06:18:22 lampret`
60			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
61			`//`
62			`// Revision 1.1 2002/01/03 08:16:15 lampret`
63			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
64			`//`
65			`// Revision 1.12 2001/11/30 18:58:00 simons`
66			`// Trap insn couses break after exits ex_insn.`
67			`//`
68			`// Revision 1.11 2001/11/23 08:38:51 lampret`
69			`// Changed DSR/DRR behavior and exception detection.`
70			`//`
71			`// Revision 1.10 2001/11/20 21:25:44 lampret`
72			`// Fixed dbg_is_o assignment width.`
73			`//`
74			`// Revision 1.9 2001/11/20 18:46:14 simons`
75			`// Break point bug fixed`
76			`//`
77			`// Revision 1.8 2001/11/18 08:36:28 lampret`
78			`// For GDB changed single stepping and disabled trap exception.`
79			`//`
80			`// Revision 1.7 2001/10/21 18:09:53 lampret`
81			`// Fixed sensitivity list.`
82			`//`
83			`// Revision 1.6 2001/10/14 13:12:09 lampret`
84			`// MP3 version.`
85			`//`
86			`//`
87
88			`// synopsys translate_off`
89			`include "timescale.v"
90			`// synopsys translate_on`
91			`include "or1200_defines.v"
92
93			`//`
94			`// Debug unit`
95			`//`
96
97			`module or1200_du(`
98			`// RISC Internal Interface`
99			`clk, rst,`
100			`dcpu_cycstb_i, dcpu_we_i,`
101			`icpu_cycstb_i, ex_freeze, branch_op, ex_insn, du_dsr,`
102			`du_stall, du_addr, du_dat_i, du_dat_o, du_read, du_write, du_except,`
103			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
104
105			`// External Debug Interface`
106			`dbg_stall_i, dbg_dat_i, dbg_adr_i, dbg_op_i, dbg_ewt_i,`
107			`dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o, dbg_dat_o`
108			`);`
109
110			parameter dw = `OR1200_OPERAND_WIDTH;
111			parameter aw = `OR1200_OPERAND_WIDTH;
112
113			`//`
114			`// I/O`
115			`//`
116
117			`//`
118			`// RISC Internal Interface`
119			`//`
120			`input clk; // Clock`
121			`input rst; // Reset`
122			`input dcpu_cycstb_i; // LSU status`
123			`input dcpu_we_i; // LSU status`
124			input [`OR1200_FETCHOP_WIDTH-1:0] icpu_cycstb_i; // IFETCH unit status
125			`input ex_freeze; // EX stage freeze`
126			input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch op
127			`input [dw-1:0] ex_insn; // EX insn`
128			output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR
129			`output du_stall; // Debug Unit Stall`
130			`output [aw-1:0] du_addr; // Debug Unit Address`
131			`input [dw-1:0] du_dat_i; // Debug Unit Data In`
132			`output [dw-1:0] du_dat_o; // Debug Unit Data Out`
133			`output du_read; // Debug Unit Read Enable`
134			`output du_write; // Debug Unit Write Enable`
135			`input [12:0] du_except; // Exception masked by DSR`
136			`input spr_cs; // SPR Chip Select`
137			`input spr_write; // SPR Read/Write`
138			`input [aw-1:0] spr_addr; // SPR Address`
139			`input [dw-1:0] spr_dat_i; // SPR Data Input`
140			`output [dw-1:0] spr_dat_o; // SPR Data Output`
141
142			`//`
143			`// External Debug Interface`
144			`//`
145			`input dbg_stall_i; // External Stall Input`
146			`input [dw-1:0] dbg_dat_i; // External Data Input`
147			`input [aw-1:0] dbg_adr_i; // External Address Input`
148			`input [2:0] dbg_op_i; // External Operation Select Input`
149			`input dbg_ewt_i; // External Watchpoint Trigger Input`
150			`output [3:0] dbg_lss_o; // External Load/Store Unit Status`
151			`output [1:0] dbg_is_o; // External Insn Fetch Status`
152			`output [10:0] dbg_wp_o; // Watchpoints Outputs`
153			`output dbg_bp_o; // Breakpoint Output`
154			`output [dw-1:0] dbg_dat_o; // External Data Output`
155
156
157			`//`
158			`// Some connections go directly from the CPU through DU to Debug I/F`
159			`//`
160			`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
161			`assign dbg_lss_o = 4'b0000;`
162			`assign dbg_is_o = 2'b00;`
163			`else
164			`assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;`
165			`assign dbg_is_o = {1'b0, icpu_cycstb_i};`
166			`endif
167			`assign dbg_wp_o = 11'b000_0000_0000;`
168			`assign dbg_dat_o = du_dat_i;`
169
170			`//`
171			`// Some connections go directly from Debug I/F through DU to the CPU`
172			`//`
173			`assign du_stall = dbg_stall_i;`
174			`assign du_addr = dbg_adr_i;`
175			`assign du_dat_o = dbg_dat_i;`
176			assign du_read = (dbg_op_i == `OR1200_DU_OP_READSPR);
177			assign du_write = (dbg_op_i == `OR1200_DU_OP_WRITESPR);
178
179			`ifdef OR1200_DU_IMPLEMENTED
180
181			`//`
182			`// Debug Mode Register 1 (only ST and BT implemented)`
183			`//`
184			`ifdef OR1200_DU_DMR1
185			`reg [23:22] dmr1; // DMR1 implemented (ST & BT)`
186			`else
187			`wire [23:22] dmr1; // DMR1 not implemented`
188			`endif
189
190			`//`
191			`// Debug Mode Register 2 (not implemented)`
192			`//`
193			`ifdef OR1200_DU_DMR2
194			`wire [31:0] dmr2; // DMR not implemented`
195			`endif
196
197			`//`
198			`// Debug Stop Register`
199			`//`
200			`ifdef OR1200_DU_DSR
201			reg [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR implemented
202			`else
203			wire [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR not implemented
204			`endif
205
206			`//`
207			`// Debug Reason Register`
208			`//`
209			`ifdef OR1200_DU_DRR
210			`reg [13:0] drr; // DRR implemented`
211			`else
212			`wire [13:0] drr; // DRR not implemented`
213			`endif
214
215			`//`
216			`// Internal wires`
217			`//`
218			`wire dmr1_sel; // DMR1 select`
219			`wire dsr_sel; // DSR select`
220			`wire drr_sel; // DRR select`
221			`reg dbg_bp_r;`
222			`ifdef OR1200_DU_READREGS
223			`reg [31:0] spr_dat_o;`
224			`endif
225			`reg [13:0] except_stop; // Exceptions that stop because of DSR`
226
227			`//`
228			`// DU registers address decoder`
229			`//`
230			`ifdef OR1200_DU_DMR1
231			assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DMR1));
232			`endif
233			`ifdef OR1200_DU_DSR
234			assign dsr_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DSR));
235			`endif
236			`ifdef OR1200_DU_DRR
237			assign drr_sel = (spr_cs && (spr_addr[`OR1200_SPR_OFS_BITS] == `OR1200_DU_OFS_DRR));
238			`endif
239
240			`//`
241			`// Decode started exception`
242			`//`
243			`always @(du_except) begin`
244			`except_stop = 14'b0000_0000_0000;`
245			`casex (du_except)`
246			`13'b1_xxxx_xxxx_xxxx:`
247			except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
248			`13'b0_1xxx_xxxx_xxxx: begin`
249			except_stop[`OR1200_DU_DRR_IE] = 1'b1;
250			`end`
251			`13'b0_01xx_xxxx_xxxx: begin`
252			except_stop[`OR1200_DU_DRR_IME] = 1'b1;
253			`end`
254			`13'b0_001x_xxxx_xxxx:`
255			except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
256			`13'b0_0001_xxxx_xxxx: begin`
257			except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
258			`end`
259			`13'b0_0000_1xxx_xxxx:`
260			except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
261			`13'b0_0000_01xx_xxxx: begin`
262			except_stop[`OR1200_DU_DRR_AE] = 1'b1;
263			`end`
264			`13'b0_0000_001x_xxxx: begin`
265			except_stop[`OR1200_DU_DRR_DME] = 1'b1;
266			`end`
267			`13'b0_0000_0001_xxxx:`
268			except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
269			`13'b0_0000_0000_1xxx:`
270			except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
271			`13'b0_0000_0000_01xx: begin`
272			except_stop[`OR1200_DU_DRR_RE] = 1'b1;
273			`end`
274			`13'b0_0000_0000_001x: begin`
275			except_stop[`OR1200_DU_DRR_TE] = 1'b1;
276			`end`
277			`13'b0_0000_0000_0001:`
278			except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
279			`default:`
280			`except_stop = 14'b0000_0000_0000;`
281			`endcase`
282			`end`
283
284			`//`
285			`// dbg_bp_o is registered`
286			`//`
287			`assign dbg_bp_o = dbg_bp_r;`
288
289			`//`
290			`// Breakpoint activation register`
291			`//`
292			`always @(posedge clk or posedge rst)`
293			`if (rst)`
294			`dbg_bp_r <= #1 1'b0;`
295			`else if (!ex_freeze)`
296			`dbg_bp_r <= #1 \|except_stop`
297			`ifdef OR1200_DU_DMR1_ST
298			\| ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
299			`endif
300			`ifdef OR1200_DU_DMR1_BT
301			\| (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
302			`endif
303			`;`
304			`else`
305			`dbg_bp_r <= #1 \|except_stop;`
306
307			`//`
308			`// Write to DMR1`
309			`//`
310			`ifdef OR1200_DU_DMR1
311			`always @(posedge clk or posedge rst)`
312			`if (rst)`
313			`dmr1 <= 2'b00;`
314			`else if (dmr1_sel && spr_write)`
315			`dmr1 <= #1 spr_dat_i[23:22];`
316			`else
317			`assign dmr1 = 2'b00;`
318			`endif
319
320			`//`
321			`// DMR2 bits tied to zero`
322			`//`
323			`ifdef OR1200_DU_DMR2
324			`assign dmr2 = 32'h0000_0000;`
325			`endif
326
327			`//`
328			`// Write to DSR`
329			`//`
330			`ifdef OR1200_DU_DSR
331			`always @(posedge clk or posedge rst)`
332			`if (rst)`
333			dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
334			`else if (dsr_sel && spr_write)`
335			dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
336			`else
337			assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
338			`endif
339
340			`//`
341			`// Write to DRR`
342			`//`
343			`ifdef OR1200_DU_DRR
344			`always @(posedge clk or posedge rst)`
345			`if (rst)`
346			`drr <= 14'b0;`
347			`else if (drr_sel && spr_write)`
348			`drr <= #1 spr_dat_i[13:0];`
349			`else`
350			`drr <= #1 drr \| except_stop;`
351			`else
352			`assign drr = 14'b0;`
353			`endif
354
355			`//`
356			`// Read DU registers`
357			`//`
358			`ifdef OR1200_DU_READREGS
359			`always @(spr_addr or dsr or drr or dmr1 or dmr2)`
360			case (spr_addr[`OR1200_SPR_OFS_BITS])
361			`ifdef OR1200_DU_DMR1
362			`OR1200_DU_OFS_DMR1:
363			`spr_dat_o = {8'b0, dmr1, 22'b0};`
364			`endif
365			`ifdef OR1200_DU_DMR2
366			`OR1200_DU_OFS_DMR2:
367			`spr_dat_o = dmr2;`
368			`endif
369			`ifdef OR1200_DU_DSR
370			`OR1200_DU_OFS_DSR:
371			`spr_dat_o = {18'b0, dsr};`
372			`endif
373			`ifdef OR1200_DU_DRR
374			`OR1200_DU_OFS_DRR:
375			`spr_dat_o = {18'b0, drr};`
376			`endif
377			`default:`
378			`spr_dat_o = 32'h0000_0000;`
379			`endcase`
380			`endif
381
382			`//`
383			`// DSR alias`
384			`//`
385			`assign du_dsr = dsr;`
386
387			`else
388
389			`//`
390			`// When DU is not implemented, drive all outputs as would when DU is disabled`
391			`//`
392			`assign dbg_bp_o = 1'b0;`
393			assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
394
395			`//`
396			`// Read DU registers`
397			`//`
398			`ifdef OR1200_DU_READREGS
399			`assign spr_dat_o = 32'h0000_0000;`
400			`ifdef OR1200_DU_UNUSED_ZERO
401			`endif
402			`endif
403
404			`endif
405
406			`endmodule`