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lampret |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's Exception logic ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/cores/or1k/ ////
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//// ////
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//// Description ////
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//// Handles all OR1K exceptions inside CPU block. ////
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//// ////
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//// To Do: ////
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//// - make it smaller and faster ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.9 2002/02/11 04:33:17 lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.8 2002/01/28 01:16:00 lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.7 2002/01/23 07:52:36 lampret
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// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
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//
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// Revision 1.6 2002/01/18 14:21:43 lampret
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// Fixed 'the NPC single-step fix'.
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//
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// Revision 1.5 2002/01/18 07:56:00 lampret
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// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
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//
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// Revision 1.4 2002/01/14 21:11:50 lampret
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// Changed alignment exception EPCR. Not tested yet.
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//
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// Revision 1.3 2002/01/14 19:09:57 lampret
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// Fixed order of syscall and range exceptions.
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//
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// Revision 1.2 2002/01/14 06:18:22 lampret
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// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
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//
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// Revision 1.1 2002/01/03 08:16:15 lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.15 2001/11/27 23:13:11 lampret
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// Fixed except_stop width and fixed EX PC for 1400444f no-ops.
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//
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// Revision 1.14 2001/11/23 08:38:51 lampret
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// Changed DSR/DRR behavior and exception detection.
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//
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// Revision 1.13 2001/11/20 18:46:15 simons
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// Break point bug fixed
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//
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// Revision 1.12 2001/11/18 09:58:28 lampret
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// Fixed some l.trap typos.
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//
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// Revision 1.11 2001/11/18 08:36:28 lampret
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// For GDB changed single stepping and disabled trap exception.
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//
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// Revision 1.10 2001/11/13 10:02:21 lampret
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// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
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//
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// Revision 1.9 2001/11/10 03:43:57 lampret
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// Fixed exceptions.
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//
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// Revision 1.8 2001/10/21 17:57:16 lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.7 2001/10/14 13:12:09 lampret
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// MP3 version.
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//
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// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
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// no message
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//
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// Revision 1.2 2001/08/09 13:39:33 lampret
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// Major clean-up.
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//
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// Revision 1.1 2001/07/20 00:46:03 lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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`define OR1200_EXCEPTFSM_WIDTH 3
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`define OR1200_EXCEPTFSM_IDLE `OR1200_EXCEPTFSM_WIDTH'd0
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`define OR1200_EXCEPTFSM_FLU1 `OR1200_EXCEPTFSM_WIDTH'd1
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`define OR1200_EXCEPTFSM_FLU2 `OR1200_EXCEPTFSM_WIDTH'd2
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`define OR1200_EXCEPTFSM_FLU3 `OR1200_EXCEPTFSM_WIDTH'd3
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`define OR1200_EXCEPTFSM_FLU4 `OR1200_EXCEPTFSM_WIDTH'd4
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`define OR1200_EXCEPTFSM_FLU5 `OR1200_EXCEPTFSM_WIDTH'd5
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//
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// Exception recognition and sequencing
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//
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module or1200_except(
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// Clock and reset
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clk, rst,
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// Internal i/f
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sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss, sig_dmmufault,
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sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault, sig_tick,
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branch_taken, id_freeze, ex_freeze, wb_freeze, if_stall,
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if_pc, lr_sav, flushpipe, extend_flush, except_type, except_start,
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except_started, except_stop, ex_void,
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spr_dat_ppc, spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
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esr, sr, lsu_addr, abort_ex
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);
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//
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// I/O
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//
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input clk;
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input rst;
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input sig_ibuserr;
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input sig_dbuserr;
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input sig_illegal;
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input sig_align;
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input sig_range;
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input sig_dtlbmiss;
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input sig_dmmufault;
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input sig_int;
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input sig_syscall;
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input sig_trap;
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input sig_itlbmiss;
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input sig_immufault;
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input sig_tick;
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input branch_taken;
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input id_freeze;
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input ex_freeze;
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input wb_freeze;
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input if_stall;
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input [31:0] if_pc;
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output [31:2] lr_sav;
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input [31:0] datain;
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input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
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input epcr_we;
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input eear_we;
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input esr_we;
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input pc_we;
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output [31:0] epcr;
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output [31:0] eear;
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output [`OR1200_SR_WIDTH-1:0] esr;
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input [`OR1200_SR_WIDTH-1:0] sr;
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input [31:0] lsu_addr;
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output flushpipe;
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output extend_flush;
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output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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output except_start;
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output except_started;
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output [12:0] except_stop;
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input ex_void;
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output [31:0] spr_dat_ppc;
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output [31:0] spr_dat_npc;
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output abort_ex;
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//
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// Internal regs and wires
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//
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reg [`OR1200_EXCEPT_WIDTH-1:0] except_type;
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reg [31:0] id_pc;
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reg [31:0] ex_pc;
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reg [31:0] wb_pc;
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reg [31:0] epcr;
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reg [31:0] eear;
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reg [`OR1200_SR_WIDTH-1:0] esr;
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reg [2:0] id_exceptflags;
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reg [2:0] ex_exceptflags;
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reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
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reg extend_flush;
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reg extend_flush_last;
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reg ex_dslot;
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reg delayed1_ex_dslot;
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reg delayed2_ex_dslot;
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wire except_started;
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wire [12:0] except_trig;
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wire except_flushpipe;
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reg [2:0] delayed_iee;
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reg [2:0] delayed_tee;
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wire int_pending;
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wire tick_pending;
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//
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// Simple combinatorial logic
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//
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assign except_started = extend_flush & except_start;
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assign lr_sav = ex_pc[31:2];
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assign spr_dat_ppc = wb_pc;
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assign spr_dat_npc = ex_void ? id_pc : ex_pc;
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//assign except_start = (except_type != `OR1200_EXCEPT_NONE); // damjan
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assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
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assign int_pending = sig_int & sr[`OR1200_SR_IEE] & delayed_iee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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//assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & delayed_tee[2] & ~ex_freeze & ~branch_taken & ~ex_dslot; // works with uclinux. except_test fails
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//assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & ~ex_freeze & ~branch_taken & ~ex_dslot; // works with uclinux, except_tets almost works (priority fails)
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assign tick_pending = sig_tick & sr[`OR1200_SR_TEE] & ~ex_freeze & ~branch_taken & ~ex_dslot;
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assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align | sig_illegal; // Abort write into RF by load & other instructions
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//
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// Order defines exception detection priority
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//
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assign except_trig = {
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tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE],
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int_pending & ~du_dsr[`OR1200_DU_DSR_IE],
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ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME],
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ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_IPFE],
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ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
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sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
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sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
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sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_range & ~du_dsr[`OR1200_DU_DSR_RE],
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sig_trap & ~du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
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sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
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};
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assign except_stop = {
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tick_pending & du_dsr[`OR1200_DU_DSR_TTE],
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int_pending & du_dsr[`OR1200_DU_DSR_IE],
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ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IME],
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ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_IPFE],
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ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_illegal & du_dsr[`OR1200_DU_DSR_IIE],
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sig_align & du_dsr[`OR1200_DU_DSR_AE],
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sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
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sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
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sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
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sig_range & du_dsr[`OR1200_DU_DSR_RE],
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sig_trap & du_dsr[`OR1200_DU_DSR_TE] & ~ex_freeze,
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sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
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};
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//
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// PC and Exception flags pipelines
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//
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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id_pc <= #1 32'd0;
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id_exceptflags <= #1 3'b000;
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end
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else if (flushpipe) begin
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id_pc <= #1 32'h0000_0000;
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id_exceptflags <= #1 3'b000;
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end
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else if (!id_freeze) begin
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id_pc <= #1 if_pc;
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id_exceptflags <= #1 { sig_ibuserr, sig_itlbmiss, sig_immufault };
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end
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end
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//
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// delayed_iee
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//
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// SR[IEE] should not enable interrupts right away
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// when it is restored with l.rfe. Instead delayed_iee
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// together with SR[IEE] enables interrupts once
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// pipeline is again ready.
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//
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always @(posedge rst or posedge clk)
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if (rst)
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delayed_iee <= #1 3'b000;
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else if (!sr[`OR1200_SR_IEE])
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delayed_iee <= #1 3'b000;
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else
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delayed_iee <= #1 {delayed_iee[1:0], 1'b1};
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|
| 299 |
|
|
//
|
| 300 |
|
|
// delayed_tee
|
| 301 |
|
|
//
|
| 302 |
|
|
// SR[TEE] should not enable tick exceptions right away
|
| 303 |
|
|
// when it is restored with l.rfe. Instead delayed_tee
|
| 304 |
|
|
// together with SR[TEE] enables tick exceptions once
|
| 305 |
|
|
// pipeline is again ready.
|
| 306 |
|
|
//
|
| 307 |
|
|
always @(posedge rst or posedge clk)
|
| 308 |
|
|
if (rst)
|
| 309 |
|
|
delayed_tee <= #1 3'b000;
|
| 310 |
|
|
else if (!sr[`OR1200_SR_TEE])
|
| 311 |
|
|
delayed_tee <= #1 3'b000;
|
| 312 |
|
|
else
|
| 313 |
|
|
delayed_tee <= #1 {delayed_tee[1:0], 1'b1};
|
| 314 |
|
|
|
| 315 |
|
|
//
|
| 316 |
|
|
// PC and Exception flags pipelines
|
| 317 |
|
|
//
|
| 318 |
|
|
always @(posedge clk or posedge rst) begin
|
| 319 |
|
|
if (rst) begin
|
| 320 |
|
|
ex_dslot <= #1 1'b0;
|
| 321 |
|
|
ex_pc <= #1 32'd0;
|
| 322 |
|
|
ex_exceptflags <= #1 3'b000;
|
| 323 |
|
|
delayed1_ex_dslot <= #1 1'b0;
|
| 324 |
|
|
delayed2_ex_dslot <= #1 1'b0;
|
| 325 |
|
|
end
|
| 326 |
|
|
else if (flushpipe) begin
|
| 327 |
|
|
ex_dslot <= #1 1'b0;
|
| 328 |
|
|
ex_pc <= #1 32'h0000_0000;
|
| 329 |
|
|
ex_exceptflags <= #1 3'b000;
|
| 330 |
|
|
delayed1_ex_dslot <= #1 1'b0;
|
| 331 |
|
|
delayed2_ex_dslot <= #1 1'b0;
|
| 332 |
|
|
end
|
| 333 |
|
|
else if (!ex_freeze & id_freeze) begin
|
| 334 |
|
|
ex_dslot <= #1 1'b0;
|
| 335 |
|
|
ex_pc <= #1 id_pc;
|
| 336 |
|
|
ex_exceptflags <= #1 3'b000;
|
| 337 |
|
|
delayed1_ex_dslot <= #1 ex_dslot;
|
| 338 |
|
|
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
|
| 339 |
|
|
end
|
| 340 |
|
|
else if (!ex_freeze) begin
|
| 341 |
|
|
`ifdef OR1200_VERBOSE
|
| 342 |
|
|
// synopsys translate_off
|
| 343 |
|
|
$display("%t: ex_pc <= %h", $time, id_pc);
|
| 344 |
|
|
// synopsys translate_on
|
| 345 |
|
|
`endif
|
| 346 |
|
|
ex_dslot <= #1 branch_taken;
|
| 347 |
|
|
ex_pc <= #1 id_pc;
|
| 348 |
|
|
ex_exceptflags <= #1 id_exceptflags;
|
| 349 |
|
|
delayed1_ex_dslot <= #1 ex_dslot;
|
| 350 |
|
|
delayed2_ex_dslot <= #1 delayed1_ex_dslot;
|
| 351 |
|
|
end
|
| 352 |
|
|
end
|
| 353 |
|
|
|
| 354 |
|
|
//
|
| 355 |
|
|
// PC and Exception flags pipelines
|
| 356 |
|
|
//
|
| 357 |
|
|
always @(posedge clk or posedge rst) begin
|
| 358 |
|
|
if (rst) begin
|
| 359 |
|
|
wb_pc <= #1 32'd0;
|
| 360 |
|
|
end
|
| 361 |
|
|
else if (!wb_freeze) begin
|
| 362 |
|
|
wb_pc <= #1 ex_pc;
|
| 363 |
|
|
end
|
| 364 |
|
|
end
|
| 365 |
|
|
|
| 366 |
|
|
//
|
| 367 |
|
|
// Flush pipeline
|
| 368 |
|
|
//
|
| 369 |
|
|
assign flushpipe = except_flushpipe | pc_we | extend_flush;
|
| 370 |
|
|
|
| 371 |
|
|
//
|
| 372 |
|
|
// We have started execution of exception handler:
|
| 373 |
|
|
// 1. Asserted for 3 clock cycles
|
| 374 |
|
|
// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler
|
| 375 |
|
|
//
|
| 376 |
|
|
assign except_flushpipe = |except_trig & !state;
|
| 377 |
|
|
|
| 378 |
|
|
//
|
| 379 |
|
|
// Exception FSM that sequences execution of exception handler
|
| 380 |
|
|
//
|
| 381 |
|
|
// except_type signals which exception handler we start fetching in:
|
| 382 |
|
|
// 1. Asserted in next clock cycle after exception is recognized
|
| 383 |
|
|
//
|
| 384 |
|
|
always @(posedge clk or posedge rst) begin
|
| 385 |
|
|
if (rst) begin
|
| 386 |
|
|
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
| 387 |
|
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
| 388 |
|
|
extend_flush <= #1 1'b0;
|
| 389 |
|
|
epcr <= #1 32'b0;
|
| 390 |
|
|
eear <= #1 32'b0;
|
| 391 |
|
|
esr <= #1 {1'b1, {`OR1200_SR_WIDTH-2{1'b0}}, 1'b1};
|
| 392 |
|
|
extend_flush_last <= #1 1'b0;
|
| 393 |
|
|
end
|
| 394 |
|
|
else begin
|
| 395 |
|
|
case (state) // synopsys full_case parallel_case
|
| 396 |
|
|
`OR1200_EXCEPTFSM_IDLE:
|
| 397 |
|
|
if (except_flushpipe) begin
|
| 398 |
|
|
state <= #1 `OR1200_EXCEPTFSM_FLU1;
|
| 399 |
|
|
extend_flush <= #1 1'b1;
|
| 400 |
|
|
if (ex_dslot) begin
|
| 401 |
|
|
`ifdef OR1200_VERBOSE
|
| 402 |
|
|
// synopsys translate_off
|
| 403 |
|
|
$display(" INFO: Exception during first delay slot instruction.");
|
| 404 |
|
|
// synopsys translate_on
|
| 405 |
|
|
`endif
|
| 406 |
|
|
end
|
| 407 |
|
|
else if (delayed1_ex_dslot) begin
|
| 408 |
|
|
`ifdef OR1200_VERBOSE
|
| 409 |
|
|
// synopsys translate_off
|
| 410 |
|
|
$display(" INFO: Exception during second (NOP) delay slot instruction.");
|
| 411 |
|
|
// synopsys translate_on
|
| 412 |
|
|
`endif
|
| 413 |
|
|
end
|
| 414 |
|
|
else if (delayed2_ex_dslot) begin
|
| 415 |
|
|
`ifdef OR1200_VERBOSE
|
| 416 |
|
|
// synopsys translate_off
|
| 417 |
|
|
$display(" INFO: Exception during third delay slot (SHOULD NOT HAPPEN).");
|
| 418 |
|
|
// synopsys translate_on
|
| 419 |
|
|
`endif
|
| 420 |
|
|
end
|
| 421 |
|
|
else begin
|
| 422 |
|
|
`ifdef OR1200_VERBOSE
|
| 423 |
|
|
// synopsys translate_off
|
| 424 |
|
|
$display(" INFO: Exception during normal (no delay slot) instruction.");
|
| 425 |
|
|
// synopsys translate_on
|
| 426 |
|
|
`endif
|
| 427 |
|
|
end
|
| 428 |
|
|
|
| 429 |
|
|
esr <= #1 sr;
|
| 430 |
|
|
casex (except_trig)
|
| 431 |
|
|
13'b1_xxxx_xxxx_xxxx: begin
|
| 432 |
|
|
except_type <= #1 `OR1200_EXCEPT_TICK;
|
| 433 |
|
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
| 434 |
|
|
end
|
| 435 |
|
|
13'b0_1xxx_xxxx_xxxx: begin
|
| 436 |
|
|
except_type <= #1 `OR1200_EXCEPT_INT;
|
| 437 |
|
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
| 438 |
|
|
end
|
| 439 |
|
|
13'b0_01xx_xxxx_xxxx: begin
|
| 440 |
|
|
except_type <= #1 `OR1200_EXCEPT_ITLBMISS;
|
| 441 |
|
|
eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
| 442 |
|
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
| 443 |
|
|
end
|
| 444 |
|
|
13'b0_001x_xxxx_xxxx: begin
|
| 445 |
|
|
except_type <= #1 `OR1200_EXCEPT_IPF;
|
| 446 |
|
|
eear <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
| 447 |
|
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
| 448 |
|
|
end
|
| 449 |
|
|
13'b0_0001_xxxx_xxxx: begin
|
| 450 |
|
|
except_type <= #1 `OR1200_EXCEPT_BUSERR;
|
| 451 |
|
|
eear <= #1 ex_dslot ? wb_pc : ex_pc;
|
| 452 |
|
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
| 453 |
|
|
end
|
| 454 |
|
|
13'b0_0000_1xxx_xxxx: begin
|
| 455 |
|
|
except_type <= #1 `OR1200_EXCEPT_ILLEGAL;
|
| 456 |
|
|
eear <= #1 ex_pc;
|
| 457 |
|
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
| 458 |
|
|
end
|
| 459 |
|
|
13'b0_0000_01xx_xxxx: begin
|
| 460 |
|
|
except_type <= #1 `OR1200_EXCEPT_ALIGN;
|
| 461 |
|
|
eear <= #1 lsu_addr;
|
| 462 |
|
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
| 463 |
|
|
end
|
| 464 |
|
|
13'b0_0000_001x_xxxx: begin
|
| 465 |
|
|
except_type <= #1 `OR1200_EXCEPT_DTLBMISS;
|
| 466 |
|
|
eear <= #1 lsu_addr;
|
| 467 |
|
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
| 468 |
|
|
end
|
| 469 |
|
|
13'b0_0000_0001_xxxx: begin
|
| 470 |
|
|
except_type <= #1 `OR1200_EXCEPT_DPF;
|
| 471 |
|
|
eear <= #1 lsu_addr;
|
| 472 |
|
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
| 473 |
|
|
end
|
| 474 |
|
|
13'b0_0000_0000_1xxx: begin // Data Bus Error
|
| 475 |
|
|
except_type <= #1 `OR1200_EXCEPT_BUSERR;
|
| 476 |
|
|
eear <= #1 lsu_addr;
|
| 477 |
|
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
| 478 |
|
|
end
|
| 479 |
|
|
13'b0_0000_0000_01xx: begin
|
| 480 |
|
|
except_type <= #1 `OR1200_EXCEPT_RANGE;
|
| 481 |
|
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
| 482 |
|
|
end
|
| 483 |
|
|
13'b0_0000_0000_001x: begin
|
| 484 |
|
|
except_type <= #1 `OR1200_EXCEPT_TRAP;
|
| 485 |
|
|
epcr <= #1 ex_dslot ? wb_pc : ex_pc;
|
| 486 |
|
|
end
|
| 487 |
|
|
13'b0_0000_0000_0001: begin
|
| 488 |
|
|
except_type <= #1 `OR1200_EXCEPT_SYSCALL;
|
| 489 |
|
|
epcr <= #1 ex_dslot ? wb_pc : delayed1_ex_dslot ? id_pc : delayed2_ex_dslot ? id_pc : id_pc;
|
| 490 |
|
|
end
|
| 491 |
|
|
default:
|
| 492 |
|
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
| 493 |
|
|
endcase
|
| 494 |
|
|
end
|
| 495 |
|
|
else if (pc_we) begin
|
| 496 |
|
|
state <= #1 `OR1200_EXCEPTFSM_FLU1;
|
| 497 |
|
|
extend_flush <= #1 1'b1;
|
| 498 |
|
|
end
|
| 499 |
|
|
else begin
|
| 500 |
|
|
if (epcr_we)
|
| 501 |
|
|
epcr <= #1 datain;
|
| 502 |
|
|
if (eear_we)
|
| 503 |
|
|
eear <= #1 datain;
|
| 504 |
|
|
if (esr_we)
|
| 505 |
|
|
esr <= #1 {1'b1, datain[`OR1200_SR_WIDTH-2:0]};
|
| 506 |
|
|
end
|
| 507 |
|
|
`OR1200_EXCEPTFSM_FLU1:
|
| 508 |
|
|
// if (!if_stall & !id_freeze)
|
| 509 |
|
|
state <= #1 `OR1200_EXCEPTFSM_FLU2;
|
| 510 |
|
|
`OR1200_EXCEPTFSM_FLU2:
|
| 511 |
|
|
if (except_type == `OR1200_EXCEPT_TRAP) begin
|
| 512 |
|
|
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
| 513 |
|
|
extend_flush <= #1 1'b0;
|
| 514 |
|
|
extend_flush_last <= #1 1'b0;
|
| 515 |
|
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
| 516 |
|
|
end
|
| 517 |
|
|
else
|
| 518 |
|
|
// if (!if_stall & !id_freeze)
|
| 519 |
|
|
state <= #1 `OR1200_EXCEPTFSM_FLU3;
|
| 520 |
|
|
`OR1200_EXCEPTFSM_FLU3:
|
| 521 |
|
|
// if (!if_stall && !id_freeze)
|
| 522 |
|
|
begin
|
| 523 |
|
|
`ifdef OR1200_VERBOSE
|
| 524 |
|
|
// synopsys translate_off
|
| 525 |
|
|
if (except_flushpipe)
|
| 526 |
|
|
$display(" INFO: EPCR0 %h EEAR %h ESR %h", epcr, eear, esr);
|
| 527 |
|
|
// synopsys translate_on
|
| 528 |
|
|
`endif
|
| 529 |
|
|
state <= #1 `OR1200_EXCEPTFSM_FLU4;
|
| 530 |
|
|
end
|
| 531 |
|
|
`OR1200_EXCEPTFSM_FLU4: begin
|
| 532 |
|
|
state <= #1 `OR1200_EXCEPTFSM_FLU5;
|
| 533 |
|
|
extend_flush <= #1 1'b0;
|
| 534 |
|
|
extend_flush_last <= #1 1'b0; // damjan
|
| 535 |
|
|
end
|
| 536 |
|
|
`OR1200_EXCEPTFSM_FLU5: begin
|
| 537 |
|
|
if (!if_stall && !id_freeze) begin
|
| 538 |
|
|
`ifdef OR1200_VERBOSE
|
| 539 |
|
|
// synopsys translate_off
|
| 540 |
|
|
$display(" INFO: Just finished flushing pipeline.");
|
| 541 |
|
|
// synopsys translate_on
|
| 542 |
|
|
`endif
|
| 543 |
|
|
state <= #1 `OR1200_EXCEPTFSM_IDLE;
|
| 544 |
|
|
except_type <= #1 `OR1200_EXCEPT_NONE;
|
| 545 |
|
|
extend_flush_last <= #1 1'b0;
|
| 546 |
|
|
end
|
| 547 |
|
|
end
|
| 548 |
|
|
endcase
|
| 549 |
|
|
end
|
| 550 |
|
|
end
|
| 551 |
|
|
|
| 552 |
|
|
endmodule
|
