OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [or1200.old/] [or1200_freeze.v] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 746 lampret
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's Freeze logic                                       ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/cores/or1k/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Generates all freezes and stalls inside RISC                ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46
// $Log: not supported by cvs2svn $
47
// Revision 1.3  2002/01/28 01:16:00  lampret
48
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
49
//
50
// Revision 1.2  2002/01/14 06:18:22  lampret
51
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
52
//
53
// Revision 1.1  2002/01/03 08:16:15  lampret
54
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
55
//
56
// Revision 1.10  2001/11/13 10:02:21  lampret
57
// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
58
//
59
// Revision 1.9  2001/10/21 17:57:16  lampret
60
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
61
//
62
// Revision 1.8  2001/10/19 23:28:46  lampret
63
// Fixed some synthesis warnings. Configured with caches and MMUs.
64
//
65
// Revision 1.7  2001/10/14 13:12:09  lampret
66
// MP3 version.
67
//
68
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
69
// no message
70
//
71
// Revision 1.2  2001/08/09 13:39:33  lampret
72
// Major clean-up.
73
//
74
// Revision 1.1  2001/07/20 00:46:03  lampret
75
// Development version of RTL. Libraries are missing.
76
//
77
//
78
 
79
// synopsys translate_off
80
`include "timescale.v"
81
// synopsys translate_on
82
`include "or1200_defines.v"
83
 
84
`define OR1200_NO_FREEZE        3'd0
85
`define OR1200_FREEZE_BYDC      3'd1
86
`define OR1200_FREEZE_BYMULTICYCLE      3'd2
87
`define OR1200_WAIT_LSU_TO_FINISH       3'd3
88
`define OR1200_WAIT_IC                  3'd4
89
 
90
//
91
// Freeze logic (stalls CPU pipeline, ifetcher etc.)
92
//
93
module or1200_freeze(
94
        // Clock and reset
95
        clk, rst,
96
 
97
        // Internal i/f
98
        multicycle, flushpipe, extend_flush, lsu_stall, if_stall,
99
        lsu_unstall, du_stall, mac_stall,
100
        force_dslot_fetch, abort_ex,
101
        genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze
102
);
103
 
104
//
105
// I/O
106
//
107
input                           clk;
108
input                           rst;
109
input   [`OR1200_MULTICYCLE_WIDTH-1:0]   multicycle;
110
input                           flushpipe;
111
input                           extend_flush;
112
input                           lsu_stall;
113
input                           if_stall;
114
input                           lsu_unstall;
115
input                           force_dslot_fetch;
116
input                           abort_ex;
117
input                           du_stall;
118
input                           mac_stall;
119
output                          genpc_freeze;
120
output                          if_freeze;
121
output                          id_freeze;
122
output                          ex_freeze;
123
output                          wb_freeze;
124
 
125
//
126
// Internal wires and regs
127
//
128
wire                            multicycle_freeze;
129
reg     [2:0]                    multicycle_cnt;
130
 
131
//
132
// Pipeline freeze
133
//
134
// Rules how to create freeze signals:
135
// 1. Not overwriting pipeline stages:
136
// Freze signals at the beginning of pipeline (such as if_freeze) can be asserted more
137
// often than freeze signals at the of pipeline (such as wb_freeze). In other words, wb_freeze must never
138
// be asserted when ex_freeze is not. ex_freeze must never be asserted when id_freeze is not etc.
139
//
140
// 2. Inserting NOPs in the middle of pipeline only if supported:
141
// At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.
142
// This way NOP is asserted from stage ID into EX stage.
143
//
144
assign genpc_freeze = du_stall | flushpipe;
145
assign if_freeze = id_freeze | extend_flush;
146
//assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~flushpipe | du_stall;
147
assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) | du_stall;
148
assign ex_freeze = wb_freeze;
149
//assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) & ~flushpipe | du_stall | mac_stall;
150
assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) | du_stall | mac_stall | abort_ex;
151
 
152
//
153
// Multicycle freeze
154
//
155
assign multicycle_freeze = |multicycle_cnt;
156
 
157
//
158
// Multicycle counter
159
//
160
always @(posedge clk or posedge rst)
161
        if (rst)
162
                multicycle_cnt <= #1 3'b0;
163
        else if (multicycle_cnt)
164
                multicycle_cnt <= #1 multicycle_cnt - 'd1;
165
        else if (multicycle & !ex_freeze)
166
                multicycle_cnt <= #1 multicycle;
167
 
168
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.