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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [or1200.old/] [or1200_genpc.v] - Blame information for rev 1765

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's generate PC                                        ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  PC, interface to IC.                                        ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2002/02/11 04:33:17  lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4  2002/01/28 01:16:00  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.3  2002/01/18 07:56:00  lampret
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/20 18:46:15  simons
// Break point bug fixed
//
// Revision 1.9  2001/11/18 09:58:28  lampret
// Fixed some l.trap typos.
//
// Revision 1.8  2001/11/18 08:36:28  lampret
// For GDB changed single stepping and disabled trap exception.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_genpc(
        // Clock and reset
        clk, rst,
 
        // External i/f to IC
        icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
        icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i,
 
        // Internal i/f
        branch_op, except_type, except_prefix,
        branch_addrofs, lr_restor, flag, taken, except_start,
        binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
        genpc_freeze, flushpipe, no_more_dslot
);
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// External i/f to IC
//
output  [31:0]                   icpu_adr_o;
output                          icpu_cycstb_o;
output  [3:0]                    icpu_sel_o;
output  [3:0]                    icpu_tag_o;
input                           icpu_ack_i;
input                           icpu_rty_i;
input                           icpu_err_i;
input   [31:0]                   icpu_adr_i;
 
//
// Internal i/f
//
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
input   [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
input                                   except_prefix;
input   [31:2]                  branch_addrofs;
input   [31:0]                   lr_restor;
input                           flag;
output                          taken;
input                           except_start;
input   [31:2]                  binsn_addr;
input   [31:0]                   epcr;
input   [31:0]                   spr_dat_i;
input                           spr_pc_we;
input                           genpc_refetch;
input                           genpc_freeze;
input                           flushpipe;
input                           no_more_dslot;
 
//
// Internal wires and regs
//
reg     [31:2]                  pcreg;
reg     [31:0]                   pc;
reg                             taken;  /* Set to in case of jump or taken branch */
reg                             dslot;  /* set when fetching delay slot insn */
reg                             btarget; /* set when fetching branch target insns */
 
//
// Address of insn to be fecthed
//
assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
 
//
// Control access to IC subsystem
//
// assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot;
assign icpu_cycstb_o = !genpc_freeze;
assign icpu_sel_o = 4'b1111;
assign icpu_tag_o = `OR1200_ITAG_NI;
 
//
// Async calculation of new PC value. This value is used for addressing the IC.
//
always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
        or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
        casex ({spr_pc_we, except_start, branch_op})    // synopsys parallel_case
                {2'b00, `OR1200_BRANCHOP_NOP}: begin
                        pc = {pcreg + 'd1, 2'b0};
                        taken = 1'b0;
                end
                {2'b00, `OR1200_BRANCHOP_J}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);
// synopsys translate_on
`endif
                        pc = {branch_addrofs, 2'b0};
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_JR}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);
// synopsys translate_on
`endif
                        pc = lr_restor;
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_BAL}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                        pc = {binsn_addr + branch_addrofs, 2'b0};
                        taken = 1'b1;
                end
                {2'b00, `OR1200_BRANCHOP_BF}:
                        if (flag) begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                                pc = {binsn_addr + branch_addrofs, 2'b0};
                                taken = 1'b1;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BF: not taken", $time);
// synopsys translate_on
`endif
                                pc = {pcreg + 'd1, 2'b0};
                                taken = 1'b0;
                        end
                {2'b00, `OR1200_BRANCHOP_BNF}:
                        if (flag) begin
                                pc = {pcreg + 'd1, 2'b0};
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BNF: not taken", $time);
// synopsys translate_on
`endif
                                taken = 1'b0;
                        end
                        else begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                                $display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
// synopsys translate_on
`endif
                                pc = {binsn_addr + branch_addrofs, 2'b0};
                                taken = 1'b1;
                        end
                {2'b00, `OR1200_BRANCHOP_RFE}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);
// synopsys translate_on
`endif
                        pc = epcr;
                        taken = 1'b1;
                end
                {2'b01, 3'bxxx}: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("Starting exception: %h.", except_type);
// synopsys translate_on
`endif
                        pc = { {4{except_prefix}}, 16'h0000, except_type, 8'h00};
                        taken = 1'b1;
                end
                default: begin
`ifdef OR1200_VERBOSE
// synopsys translate_off
                        $display("l.mtspr writing into PC: %h.", spr_dat_i);
// synopsys translate_on
`endif
                        pc = spr_dat_i;
                        taken = 1'b0;
                end
        endcase
end
 
//
// PC register
//
always @(posedge clk or posedge rst)
        if (rst)
                pcreg <= #1 30'd63;
        else if (spr_pc_we)
                pcreg <= #1 spr_dat_i[31:2];
        else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
//      else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
                pcreg <= #1 pc[31:2];
 
endmodule

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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [or1200.old/] [or1200_genpc.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's generate PC ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// PC, interface to IC. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.5 2002/02/11 04:33:17 lampret`
48			`// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.`
49			`//`
50			`// Revision 1.4 2002/01/28 01:16:00 lampret`
51			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
52			`//`
53			`// Revision 1.3 2002/01/18 07:56:00 lampret`
54			`// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.`
55			`//`
56			`// Revision 1.2 2002/01/14 06:18:22 lampret`
57			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
58			`//`
59			`// Revision 1.1 2002/01/03 08:16:15 lampret`
60			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
61			`//`
62			`// Revision 1.10 2001/11/20 18:46:15 simons`
63			`// Break point bug fixed`
64			`//`
65			`// Revision 1.9 2001/11/18 09:58:28 lampret`
66			`// Fixed some l.trap typos.`
67			`//`
68			`// Revision 1.8 2001/11/18 08:36:28 lampret`
69			`// For GDB changed single stepping and disabled trap exception.`
70			`//`
71			`// Revision 1.7 2001/10/21 17:57:16 lampret`
72			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
73			`//`
74			`// Revision 1.6 2001/10/14 13:12:09 lampret`
75			`// MP3 version.`
76			`//`
77			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
78			`// no message`
79			`//`
80			`// Revision 1.1 2001/08/09 13:39:33 lampret`
81			`// Major clean-up.`
82			`//`
83			`//`
84
85			`// synopsys translate_off`
86			`include "timescale.v"
87			`// synopsys translate_on`
88			`include "or1200_defines.v"
89
90			`module or1200_genpc(`
91			`// Clock and reset`
92			`clk, rst,`
93
94			`// External i/f to IC`
95			`icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,`
96			`icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i,`
97
98			`// Internal i/f`
99			`branch_op, except_type, except_prefix,`
100			`branch_addrofs, lr_restor, flag, taken, except_start,`
101			`binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,`
102			`genpc_freeze, flushpipe, no_more_dslot`
103			`);`
104
105			`//`
106			`// I/O`
107			`//`
108
109			`//`
110			`// Clock and reset`
111			`//`
112			`input clk;`
113			`input rst;`
114
115			`//`
116			`// External i/f to IC`
117			`//`
118			`output [31:0] icpu_adr_o;`
119			`output icpu_cycstb_o;`
120			`output [3:0] icpu_sel_o;`
121			`output [3:0] icpu_tag_o;`
122			`input icpu_ack_i;`
123			`input icpu_rty_i;`
124			`input icpu_err_i;`
125			`input [31:0] icpu_adr_i;`
126
127			`//`
128			`// Internal i/f`
129			`//`
130			input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
131			input [`OR1200_EXCEPT_WIDTH-1:0] except_type;
132			`input except_prefix;`
133			`input [31:2] branch_addrofs;`
134			`input [31:0] lr_restor;`
135			`input flag;`
136			`output taken;`
137			`input except_start;`
138			`input [31:2] binsn_addr;`
139			`input [31:0] epcr;`
140			`input [31:0] spr_dat_i;`
141			`input spr_pc_we;`
142			`input genpc_refetch;`
143			`input genpc_freeze;`
144			`input flushpipe;`
145			`input no_more_dslot;`
146
147			`//`
148			`// Internal wires and regs`
149			`//`
150			`reg [31:2] pcreg;`
151			`reg [31:0] pc;`
152			`reg taken; /* Set to in case of jump or taken branch */`
153			`reg dslot; /* set when fetching delay slot insn */`
154			`reg btarget; /* set when fetching branch target insns */`
155
156			`//`
157			`// Address of insn to be fecthed`
158			`//`
159			`assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i \| genpc_refetch) ? icpu_adr_i : pc;`
160			`// assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i \| genpc_refetch) ? icpu_adr_i : pc;`
161
162			`//`
163			`// Control access to IC subsystem`
164			`//`
165			`// assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot;`
166			`assign icpu_cycstb_o = !genpc_freeze;`
167			`assign icpu_sel_o = 4'b1111;`
168			assign icpu_tag_o = `OR1200_ITAG_NI;
169
170			`//`
171			`// Async calculation of new PC value. This value is used for addressing the IC.`
172			`//`
173			`always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type`
174			`or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin`
175			`casex ({spr_pc_we, except_start, branch_op}) // synopsys parallel_case`
176			{2'b00, `OR1200_BRANCHOP_NOP}: begin
177			`pc = {pcreg + 'd1, 2'b0};`
178			`taken = 1'b0;`
179			`end`
180			{2'b00, `OR1200_BRANCHOP_J}: begin
181			`ifdef OR1200_VERBOSE
182			`// synopsys translate_off`
183			`$display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);`
184			`// synopsys translate_on`
185			`endif
186			`pc = {branch_addrofs, 2'b0};`
187			`taken = 1'b1;`
188			`end`
189			{2'b00, `OR1200_BRANCHOP_JR}: begin
190			`ifdef OR1200_VERBOSE
191			`// synopsys translate_off`
192			`$display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);`
193			`// synopsys translate_on`
194			`endif
195			`pc = lr_restor;`
196			`taken = 1'b1;`
197			`end`
198			{2'b00, `OR1200_BRANCHOP_BAL}: begin
199			`ifdef OR1200_VERBOSE
200			`// synopsys translate_off`
201			`$display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
202			`// synopsys translate_on`
203			`endif
204			`pc = {binsn_addr + branch_addrofs, 2'b0};`
205			`taken = 1'b1;`
206			`end`
207			{2'b00, `OR1200_BRANCHOP_BF}:
208			`if (flag) begin`
209			`ifdef OR1200_VERBOSE
210			`// synopsys translate_off`
211			`$display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
212			`// synopsys translate_on`
213			`endif
214			`pc = {binsn_addr + branch_addrofs, 2'b0};`
215			`taken = 1'b1;`
216			`end`
217			`else begin`
218			`ifdef OR1200_VERBOSE
219			`// synopsys translate_off`
220			`$display("%t: BRANCHOP_BF: not taken", $time);`
221			`// synopsys translate_on`
222			`endif
223			`pc = {pcreg + 'd1, 2'b0};`
224			`taken = 1'b0;`
225			`end`
226			{2'b00, `OR1200_BRANCHOP_BNF}:
227			`if (flag) begin`
228			`pc = {pcreg + 'd1, 2'b0};`
229			`ifdef OR1200_VERBOSE
230			`// synopsys translate_off`
231			`$display("%t: BRANCHOP_BNF: not taken", $time);`
232			`// synopsys translate_on`
233			`endif
234			`taken = 1'b0;`
235			`end`
236			`else begin`
237			`ifdef OR1200_VERBOSE
238			`// synopsys translate_off`
239			`$display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);`
240			`// synopsys translate_on`
241			`endif
242			`pc = {binsn_addr + branch_addrofs, 2'b0};`
243			`taken = 1'b1;`
244			`end`
245			{2'b00, `OR1200_BRANCHOP_RFE}: begin
246			`ifdef OR1200_VERBOSE
247			`// synopsys translate_off`
248			`$display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);`
249			`// synopsys translate_on`
250			`endif
251			`pc = epcr;`
252			`taken = 1'b1;`
253			`end`
254			`{2'b01, 3'bxxx}: begin`
255			`ifdef OR1200_VERBOSE
256			`// synopsys translate_off`
257			`$display("Starting exception: %h.", except_type);`
258			`// synopsys translate_on`
259			`endif
260			`pc = { {4{except_prefix}}, 16'h0000, except_type, 8'h00};`
261			`taken = 1'b1;`
262			`end`
263			`default: begin`
264			`ifdef OR1200_VERBOSE
265			`// synopsys translate_off`
266			`$display("l.mtspr writing into PC: %h.", spr_dat_i);`
267			`// synopsys translate_on`
268			`endif
269			`pc = spr_dat_i;`
270			`taken = 1'b0;`
271			`end`
272			`endcase`
273			`end`
274
275			`//`
276			`// PC register`
277			`//`
278			`always @(posedge clk or posedge rst)`
279			`if (rst)`
280			`pcreg <= #1 30'd63;`
281			`else if (spr_pc_we)`
282			`pcreg <= #1 spr_dat_i[31:2];`
283			`else if (no_more_dslot \| except_start \| !genpc_freeze & !icpu_rty_i & !genpc_refetch)`
284			`// else if (except_start \| !genpc_freeze & !icpu_rty_i & !genpc_refetch)`
285			`pcreg <= #1 pc[31:2];`
286
287			`endmodule`