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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's IC FSM                                             ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Data cache state machine                                    ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5  2002/02/11 04:33:17  lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.4  2002/02/01 19:56:54  lampret
// Fixed combinational loops.
//
// Revision 1.3  2002/01/28 01:16:00  lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.2  2002/01/14 06:18:22  lampret
// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.9  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.
//
// Revision 1.8  2001/10/19 23:28:46  lampret
// Fixed some synthesis warnings. Configured with caches and MMUs.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:35  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`define OR1200_ICFSM_IDLE       3'd0
`define OR1200_ICFSM_CFETCH     3'd1
`define OR1200_ICFSM_LREFILL3   3'd2
`define OR1200_ICFSM_IFETCH     3'd3
 
//
// Data cache FSM for cache line of 16 bytes (4x singleword)
//
 
module or1200_ic_fsm(
        // Clock and reset
        clk, rst,
 
        // Internal i/f to top level IC
        ic_en, icimmu_cycstb_i, icimmu_ci_i, icpu_sel_i,
        tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,
        icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,
        burst, tag_we
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           ic_en;
input                           icimmu_cycstb_i;
input                           icimmu_ci_i;
input   [3:0]                    icpu_sel_i;
input                           tagcomp_miss;
input                           biudata_valid;
input                           biudata_error;
input   [31:0]                   start_addr;
output  [31:0]                   saved_addr;
output  [3:0]                    icram_we;
output                          biu_read;
output                          first_hit_ack;
output                          first_miss_ack;
output                          first_miss_err;
output                          burst;
output                          tag_we;
 
//
// Internal wires and regs
//
reg     [31:0]                   saved_addr_r;
reg     [2:0]                    state;
reg     [2:0]                    cnt;
reg                             hitmiss_eval;
reg                             load;
reg                             cache_inhibit;
 
//
// Generate of ICRAM write enables
//
assign icram_we = {4{load & biudata_valid & !cache_inhibit}};
assign tag_we = biu_read & biudata_valid & !cache_inhibit;
 
//
// BIU read and write
//
assign biu_read = (hitmiss_eval & tagcomp_miss) | (!hitmiss_eval & load);
 
//assign saved_addr = hitmiss_eval ? start_addr : saved_addr_r;
assign saved_addr = saved_addr_r;
 
//
// Assert for cache hit first word ready
// Assert for cache miss first word stored/loaded OK
// Assert for cache miss first word stored/loaded with an error
//
assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & !tagcomp_miss & !cache_inhibit & !icimmu_ci_i;
assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
 
//
// Assert burst when doing reload of complete cache line
//
assign burst = (state == `OR1200_ICFSM_CFETCH) & tagcomp_miss & !cache_inhibit
                | (state == `OR1200_ICFSM_LREFILL3);
 
//
// Main IC FSM
//
always @(posedge clk or posedge rst) begin
        if (rst) begin
                state <= #1 `OR1200_ICFSM_IDLE;
                saved_addr_r <= #1 32'b0;
                hitmiss_eval <= #1 1'b0;
                load <= #1 1'b0;
                cnt <= #1 3'b000;
                cache_inhibit <= #1 1'b0;
        end
        else
        case (state)    // synopsys parallel_case
                `OR1200_ICFSM_IDLE :
                        if (ic_en & icimmu_cycstb_i) begin              // fetch
                                state <= #1 `OR1200_ICFSM_CFETCH;
                                saved_addr_r <= #1 start_addr;
                                hitmiss_eval <= #1 1'b1;
                                load <= #1 1'b1;
                                cache_inhibit <= #1 1'b0;
                        end
                        else begin                                                      // idle
                                state <= #1 `OR1200_ICFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                `OR1200_ICFSM_CFETCH: begin     // fetch
                        if (icimmu_cycstb_i & icimmu_ci_i)
                                cache_inhibit <= #1 1'b1;
                        if (hitmiss_eval)
                                saved_addr_r[31:13] <= #1 start_addr[31:13];
                        if (!ic_en)
                                state <= #1 `OR1200_ICFSM_IDLE;
                        else if (hitmiss_eval & !icimmu_cycstb_i) begin // fetch aborted (usually caused by IMMU)
                                state <= #1 `OR1200_ICFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (biudata_error) begin                   // fetch terminated with an error
                                state <= #1 `OR1200_ICFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (cache_inhibit & biudata_valid) begin   // fetch from cache-inhibited page
                                state <= #1 `OR1200_ICFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (tagcomp_miss & biudata_valid) begin    // fetch missed, finish current external fetch and refill
                                state <= #1 `OR1200_ICFSM_LREFILL3;
                                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
                                hitmiss_eval <= #1 1'b0;
                                cnt <= #1 `OR1200_ICLS-2;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (!tagcomp_miss & !icimmu_ci_i) begin    // fetch hit, finish immediately
                                state <= #1 `OR1200_ICFSM_CFETCH;
                                saved_addr_r <= #1 start_addr;
                                hitmiss_eval <= #1 1'b1;
                                load <= #1 1'b1;
                                cache_inhibit <= #1 1'b0;
                        end
                        else if (!icimmu_cycstb_i) begin        // fetch aborted (usually caused by exception)
                                state <= #1 `OR1200_ICFSM_IDLE;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                                cache_inhibit <= #1 1'b0;
                        end
                        else                                            // fetch in-progress
                                hitmiss_eval <= #1 1'b0;
                end
                `OR1200_ICFSM_LREFILL3 : begin
                        if (!ic_en)
                                state <= #1 `OR1200_ICFSM_IDLE;
                        else if (biudata_valid && (|cnt)) begin         // refill ack, more fetchs to come
                                cnt <= #1 cnt - 'd1;
                                saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;
                        end
                        else if (biudata_valid) begin                   // last fetch of line refill
                                state <= #1 `OR1200_ICFSM_IDLE;
                                saved_addr_r <= #1 start_addr;
                                hitmiss_eval <= #1 1'b0;
                                load <= #1 1'b0;
                        end
                end
                default:
                        state <= #1 `OR1200_ICFSM_IDLE;
        endcase
end
 
endmodule

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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [or1200.old/] [or1200_ic_fsm.v] - Blame information for rev 746

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's IC FSM ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Data cache state machine ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`// Revision 1.5 2002/02/11 04:33:17 lampret`
48			`// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.`
49			`//`
50			`// Revision 1.4 2002/02/01 19:56:54 lampret`
51			`// Fixed combinational loops.`
52			`//`
53			`// Revision 1.3 2002/01/28 01:16:00 lampret`
54			`// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.`
55			`//`
56			`// Revision 1.2 2002/01/14 06:18:22 lampret`
57			`// Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.`
58			`//`
59			`// Revision 1.1 2002/01/03 08:16:15 lampret`
60			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
61			`//`
62			`// Revision 1.9 2001/10/21 17:57:16 lampret`
63			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from ic.v and ic.v. Fixed CR+LF.`
64			`//`
65			`// Revision 1.8 2001/10/19 23:28:46 lampret`
66			`// Fixed some synthesis warnings. Configured with caches and MMUs.`
67			`//`
68			`// Revision 1.7 2001/10/14 13:12:09 lampret`
69			`// MP3 version.`
70			`//`
71			`// Revision 1.1.1.1 2001/10/06 10:18:35 igorm`
72			`// no message`
73			`//`
74			`// Revision 1.2 2001/08/09 13:39:33 lampret`
75			`// Major clean-up.`
76			`//`
77			`// Revision 1.1 2001/07/20 00:46:03 lampret`
78			`// Development version of RTL. Libraries are missing.`
79			`//`
80			`//`
81
82			`// synopsys translate_off`
83			`include "timescale.v"
84			`// synopsys translate_on`
85			`include "or1200_defines.v"
86
87			`define OR1200_ICFSM_IDLE 3'd0
88			`define OR1200_ICFSM_CFETCH 3'd1
89			`define OR1200_ICFSM_LREFILL3 3'd2
90			`define OR1200_ICFSM_IFETCH 3'd3
91
92			`//`
93			`// Data cache FSM for cache line of 16 bytes (4x singleword)`
94			`//`
95
96			`module or1200_ic_fsm(`
97			`// Clock and reset`
98			`clk, rst,`
99
100			`// Internal i/f to top level IC`
101			`ic_en, icimmu_cycstb_i, icimmu_ci_i, icpu_sel_i,`
102			`tagcomp_miss, biudata_valid, biudata_error, start_addr, saved_addr,`
103			`icram_we, biu_read, first_hit_ack, first_miss_ack, first_miss_err,`
104			`burst, tag_we`
105			`);`
106
107			`//`
108			`// I/O`
109			`//`
110			`input clk;`
111			`input rst;`
112			`input ic_en;`
113			`input icimmu_cycstb_i;`
114			`input icimmu_ci_i;`
115			`input [3:0] icpu_sel_i;`
116			`input tagcomp_miss;`
117			`input biudata_valid;`
118			`input biudata_error;`
119			`input [31:0] start_addr;`
120			`output [31:0] saved_addr;`
121			`output [3:0] icram_we;`
122			`output biu_read;`
123			`output first_hit_ack;`
124			`output first_miss_ack;`
125			`output first_miss_err;`
126			`output burst;`
127			`output tag_we;`
128
129			`//`
130			`// Internal wires and regs`
131			`//`
132			`reg [31:0] saved_addr_r;`
133			`reg [2:0] state;`
134			`reg [2:0] cnt;`
135			`reg hitmiss_eval;`
136			`reg load;`
137			`reg cache_inhibit;`
138
139			`//`
140			`// Generate of ICRAM write enables`
141			`//`
142			`assign icram_we = {4{load & biudata_valid & !cache_inhibit}};`
143			`assign tag_we = biu_read & biudata_valid & !cache_inhibit;`
144
145			`//`
146			`// BIU read and write`
147			`//`
148			`assign biu_read = (hitmiss_eval & tagcomp_miss) \| (!hitmiss_eval & load);`
149
150			`//assign saved_addr = hitmiss_eval ? start_addr : saved_addr_r;`
151			`assign saved_addr = saved_addr_r;`
152
153			`//`
154			`// Assert for cache hit first word ready`
155			`// Assert for cache miss first word stored/loaded OK`
156			`// Assert for cache miss first word stored/loaded with an error`
157			`//`
158			assign first_hit_ack = (state == `OR1200_ICFSM_CFETCH) & hitmiss_eval & !tagcomp_miss & !cache_inhibit & !icimmu_ci_i;
159			assign first_miss_ack = (state == `OR1200_ICFSM_CFETCH) & biudata_valid;
160			assign first_miss_err = (state == `OR1200_ICFSM_CFETCH) & biudata_error;
161
162			`//`
163			`// Assert burst when doing reload of complete cache line`
164			`//`
165			assign burst = (state == `OR1200_ICFSM_CFETCH) & tagcomp_miss & !cache_inhibit
166			\| (state == `OR1200_ICFSM_LREFILL3);
167
168			`//`
169			`// Main IC FSM`
170			`//`
171			`always @(posedge clk or posedge rst) begin`
172			`if (rst) begin`
173			state <= #1 `OR1200_ICFSM_IDLE;
174			`saved_addr_r <= #1 32'b0;`
175			`hitmiss_eval <= #1 1'b0;`
176			`load <= #1 1'b0;`
177			`cnt <= #1 3'b000;`
178			`cache_inhibit <= #1 1'b0;`
179			`end`
180			`else`
181			`case (state) // synopsys parallel_case`
182			`OR1200_ICFSM_IDLE :
183			`if (ic_en & icimmu_cycstb_i) begin // fetch`
184			state <= #1 `OR1200_ICFSM_CFETCH;
185			`saved_addr_r <= #1 start_addr;`
186			`hitmiss_eval <= #1 1'b1;`
187			`load <= #1 1'b1;`
188			`cache_inhibit <= #1 1'b0;`
189			`end`
190			`else begin // idle`
191			state <= #1 `OR1200_ICFSM_IDLE;
192			`hitmiss_eval <= #1 1'b0;`
193			`load <= #1 1'b0;`
194			`cache_inhibit <= #1 1'b0;`
195			`end`
196			`OR1200_ICFSM_CFETCH: begin // fetch
197			`if (icimmu_cycstb_i & icimmu_ci_i)`
198			`cache_inhibit <= #1 1'b1;`
199			`if (hitmiss_eval)`
200			`saved_addr_r[31:13] <= #1 start_addr[31:13];`
201			`if (!ic_en)`
202			state <= #1 `OR1200_ICFSM_IDLE;
203			`else if (hitmiss_eval & !icimmu_cycstb_i) begin // fetch aborted (usually caused by IMMU)`
204			state <= #1 `OR1200_ICFSM_IDLE;
205			`hitmiss_eval <= #1 1'b0;`
206			`load <= #1 1'b0;`
207			`cache_inhibit <= #1 1'b0;`
208			`end`
209			`else if (biudata_error) begin // fetch terminated with an error`
210			state <= #1 `OR1200_ICFSM_IDLE;
211			`hitmiss_eval <= #1 1'b0;`
212			`load <= #1 1'b0;`
213			`cache_inhibit <= #1 1'b0;`
214			`end`
215			`else if (cache_inhibit & biudata_valid) begin // fetch from cache-inhibited page`
216			state <= #1 `OR1200_ICFSM_IDLE;
217			`hitmiss_eval <= #1 1'b0;`
218			`load <= #1 1'b0;`
219			`cache_inhibit <= #1 1'b0;`
220			`end`
221			`else if (tagcomp_miss & biudata_valid) begin // fetch missed, finish current external fetch and refill`
222			state <= #1 `OR1200_ICFSM_LREFILL3;
223			`saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;`
224			`hitmiss_eval <= #1 1'b0;`
225			cnt <= #1 `OR1200_ICLS-2;
226			`cache_inhibit <= #1 1'b0;`
227			`end`
228			`else if (!tagcomp_miss & !icimmu_ci_i) begin // fetch hit, finish immediately`
229			state <= #1 `OR1200_ICFSM_CFETCH;
230			`saved_addr_r <= #1 start_addr;`
231			`hitmiss_eval <= #1 1'b1;`
232			`load <= #1 1'b1;`
233			`cache_inhibit <= #1 1'b0;`
234			`end`
235			`else if (!icimmu_cycstb_i) begin // fetch aborted (usually caused by exception)`
236			state <= #1 `OR1200_ICFSM_IDLE;
237			`hitmiss_eval <= #1 1'b0;`
238			`load <= #1 1'b0;`
239			`cache_inhibit <= #1 1'b0;`
240			`end`
241			`else // fetch in-progress`
242			`hitmiss_eval <= #1 1'b0;`
243			`end`
244			`OR1200_ICFSM_LREFILL3 : begin
245			`if (!ic_en)`
246			state <= #1 `OR1200_ICFSM_IDLE;
247			`else if (biudata_valid && (\|cnt)) begin // refill ack, more fetchs to come`
248			`cnt <= #1 cnt - 'd1;`
249			`saved_addr_r[3:2] <= #1 saved_addr_r[3:2] + 'd1;`
250			`end`
251			`else if (biudata_valid) begin // last fetch of line refill`
252			state <= #1 `OR1200_ICFSM_IDLE;
253			`saved_addr_r <= #1 start_addr;`
254			`hitmiss_eval <= #1 1'b0;`
255			`load <= #1 1'b0;`
256			`end`
257			`end`
258			`default:`
259			state <= #1 `OR1200_ICFSM_IDLE;
260			`endcase`
261			`end`
262
263			`endmodule`