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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Top level multiplier and MAC                       ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Multiplier is 32x32 however multiply instructions only      ////
////  use lower 32 bits of the result. MAC is 32x32=64+64.        ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.3  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.2  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:38  igorm
// no message
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_mult_mac(
        // Clock and reset
        clk, rst,
 
        // Multiplier/MAC interface
        ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op, result, mac_stall_r,
 
        // SPR interface
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// Multiplier/MAC interface
//
input                           ex_freeze;
input                           id_macrc_op;
input                           macrc_op;
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [`OR1200_MACOP_WIDTH-1:0]        mac_op;
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
output  [width-1:0]              result;
output                          mac_stall_r;
 
//
// SPR interface
//
input                           spr_cs;
input                           spr_write;
input   [31:0]                   spr_addr;
input   [31:0]                   spr_dat_i;
output  [31:0]                   spr_dat_o;
 
//
// Internal wires and regs
//
wire    [width-1:0]              result;
reg     [2*width-1:0]            mul_prod_r;
reg     [2*width-1:0]            mac_r;
wire    [2*width-1:0]            mul_prod;
wire    [`OR1200_MACOP_WIDTH-1:0]        mac_op;
reg     [`OR1200_MACOP_WIDTH-1:0]        mac_op_r1;
reg     [`OR1200_MACOP_WIDTH-1:0]        mac_op_r2;
reg     [`OR1200_MACOP_WIDTH-1:0]        mac_op_r3;
reg                             mac_stall_r;
wire    [width-1:0]              x;
wire    [width-1:0]              y;
wire                            spr_maclo_we;
wire                            spr_machi_we;
 
//
// Combinatorial logic
//
assign result = (alu_op == `OR1200_ALUOP_MUL) ? mul_prod_r[31:0] : mac_r[59:28];
assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];
assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];
`ifdef OR1200_LOWPWR_MULT
assign x = (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? a : 32'h0000_0000;
assign y = (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? b : 32'h0000_0000;
`else
assign x = a;
assign y = b;
`endif
 
//
// Instantiation of the multiplier
//
`ifdef OR1200_ASIC_MULTP2_32X32
or1200_amultp2_32x32 or1200_amultp2_32x32(
        .X(x),
        .Y(y),
        .RST(rst),
        .CLK(clk),
        .P(mul_prod)
);
`else
or1200_gmultp2_32x32 or1200_gmultp2_32x32(
        .X(x),
        .Y(y),
        .RST(rst),
        .CLK(clk),
        .P(mul_prod)
);
`endif
 
//
// Registered output from the multiplier
//
always @(posedge rst or posedge clk)
        if (rst)
                mul_prod_r <= #1 64'h0000_0000_0000_0000;
        else
                mul_prod_r <= #1 mul_prod[63:0];
 
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
        if (rst)
                mac_op_r1 <= #1 `OR1200_MACOP_WIDTH'b0;
        else
                mac_op_r1 <= #1 mac_op;
 
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
        if (rst)
                mac_op_r2 <= #1 `OR1200_MACOP_WIDTH'b0;
        else
                mac_op_r2 <= #1 mac_op_r1;
 
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
        if (rst)
                mac_op_r3 <= #1 `OR1200_MACOP_WIDTH'b0;
        else
                mac_op_r3 <= #1 mac_op_r2;
 
//
// Implementation of MAC
//
always @(posedge rst or posedge clk)
        if (rst)
                mac_r <= #1 64'h0000_0000_0000_0000;
`ifdef OR1200_MAC_SPR_WE
        else if (spr_maclo_we)
                mac_r[31:0] <= #1 spr_dat_i;
        else if (spr_machi_we)
                mac_r[63:32] <= #1 spr_dat_i;
`endif
        else if (mac_op_r3 == `OR1200_MACOP_MAC)
                mac_r <= #1 mac_r + mul_prod_r;
        else if (mac_op_r3 == `OR1200_MACOP_MSB)
                mac_r <= #1 mac_r - mul_prod_r;
        else if (macrc_op & !ex_freeze)
                mac_r <= #1 64'h0000_0000_0000_0000;
 
//
// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions
// in EX stage (e.g. inside multiplier)
//
always @(posedge rst or posedge clk)
        if (rst)
                mac_stall_r <= #1 1'b0;
        else
                mac_stall_r <= #1 (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & id_macrc_op;
 
endmodule

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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [or1200.old/] [or1200_mult_mac.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Top level multiplier and MAC ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Multiplier is 32x32 however multiply instructions only ////`
10			`//// use lower 32 bits of the result. MAC is 32x32=64+64. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - make it smaller and faster ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`// Revision 1.1 2002/01/03 08:16:15 lampret`
49			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
50			`//`
51			`// Revision 1.3 2001/10/21 17:57:16 lampret`
52			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
53			`//`
54			`// Revision 1.2 2001/10/14 13:12:09 lampret`
55			`// MP3 version.`
56			`//`
57			`// Revision 1.1.1.1 2001/10/06 10:18:38 igorm`
58			`// no message`
59			`//`
60			`//`
61
62			`// synopsys translate_off`
63			`include "timescale.v"
64			`// synopsys translate_on`
65			`include "or1200_defines.v"
66
67			`module or1200_mult_mac(`
68			`// Clock and reset`
69			`clk, rst,`
70
71			`// Multiplier/MAC interface`
72			`ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op, result, mac_stall_r,`
73
74			`// SPR interface`
75			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o`
76			`);`
77
78			parameter width = `OR1200_OPERAND_WIDTH;
79
80			`//`
81			`// I/O`
82			`//`
83
84			`//`
85			`// Clock and reset`
86			`//`
87			`input clk;`
88			`input rst;`
89
90			`//`
91			`// Multiplier/MAC interface`
92			`//`
93			`input ex_freeze;`
94			`input id_macrc_op;`
95			`input macrc_op;`
96			`input [width-1:0] a;`
97			`input [width-1:0] b;`
98			input [`OR1200_MACOP_WIDTH-1:0] mac_op;
99			input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
100			`output [width-1:0] result;`
101			`output mac_stall_r;`
102
103			`//`
104			`// SPR interface`
105			`//`
106			`input spr_cs;`
107			`input spr_write;`
108			`input [31:0] spr_addr;`
109			`input [31:0] spr_dat_i;`
110			`output [31:0] spr_dat_o;`
111
112			`//`
113			`// Internal wires and regs`
114			`//`
115			`wire [width-1:0] result;`
116			`reg [2*width-1:0] mul_prod_r;`
117			`reg [2*width-1:0] mac_r;`
118			`wire [2*width-1:0] mul_prod;`
119			wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
120			reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
121			reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
122			reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
123			`reg mac_stall_r;`
124			`wire [width-1:0] x;`
125			`wire [width-1:0] y;`
126			`wire spr_maclo_we;`
127			`wire spr_machi_we;`
128
129			`//`
130			`// Combinatorial logic`
131			`//`
132			assign result = (alu_op == `OR1200_ALUOP_MUL) ? mul_prod_r[31:0] : mac_r[59:28];
133			assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
134			assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];
135			assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];
136			`ifdef OR1200_LOWPWR_MULT
137			assign x = (alu_op == `OR1200_ALUOP_MUL) \| (\|mac_op) ? a : 32'h0000_0000;
138			assign y = (alu_op == `OR1200_ALUOP_MUL) \| (\|mac_op) ? b : 32'h0000_0000;
139			`else
140			`assign x = a;`
141			`assign y = b;`
142			`endif
143
144			`//`
145			`// Instantiation of the multiplier`
146			`//`
147			`ifdef OR1200_ASIC_MULTP2_32X32
148			`or1200_amultp2_32x32 or1200_amultp2_32x32(`
149			`.X(x),`
150			`.Y(y),`
151			`.RST(rst),`
152			`.CLK(clk),`
153			`.P(mul_prod)`
154			`);`
155			`else
156			`or1200_gmultp2_32x32 or1200_gmultp2_32x32(`
157			`.X(x),`
158			`.Y(y),`
159			`.RST(rst),`
160			`.CLK(clk),`
161			`.P(mul_prod)`
162			`);`
163			`endif
164
165			`//`
166			`// Registered output from the multiplier`
167			`//`
168			`always @(posedge rst or posedge clk)`
169			`if (rst)`
170			`mul_prod_r <= #1 64'h0000_0000_0000_0000;`
171			`else`
172			`mul_prod_r <= #1 mul_prod[63:0];`
173
174			`//`
175			`// Propagation of l.mac opcode`
176			`//`
177			`always @(posedge clk or posedge rst)`
178			`if (rst)`
179			mac_op_r1 <= #1 `OR1200_MACOP_WIDTH'b0;
180			`else`
181			`mac_op_r1 <= #1 mac_op;`
182
183			`//`
184			`// Propagation of l.mac opcode`
185			`//`
186			`always @(posedge clk or posedge rst)`
187			`if (rst)`
188			mac_op_r2 <= #1 `OR1200_MACOP_WIDTH'b0;
189			`else`
190			`mac_op_r2 <= #1 mac_op_r1;`
191
192			`//`
193			`// Propagation of l.mac opcode`
194			`//`
195			`always @(posedge clk or posedge rst)`
196			`if (rst)`
197			mac_op_r3 <= #1 `OR1200_MACOP_WIDTH'b0;
198			`else`
199			`mac_op_r3 <= #1 mac_op_r2;`
200
201			`//`
202			`// Implementation of MAC`
203			`//`
204			`always @(posedge rst or posedge clk)`
205			`if (rst)`
206			`mac_r <= #1 64'h0000_0000_0000_0000;`
207			`ifdef OR1200_MAC_SPR_WE
208			`else if (spr_maclo_we)`
209			`mac_r[31:0] <= #1 spr_dat_i;`
210			`else if (spr_machi_we)`
211			`mac_r[63:32] <= #1 spr_dat_i;`
212			`endif
213			else if (mac_op_r3 == `OR1200_MACOP_MAC)
214			`mac_r <= #1 mac_r + mul_prod_r;`
215			else if (mac_op_r3 == `OR1200_MACOP_MSB)
216			`mac_r <= #1 mac_r - mul_prod_r;`
217			`else if (macrc_op & !ex_freeze)`
218			`mac_r <= #1 64'h0000_0000_0000_0000;`
219
220			`//`
221			`// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions`
222			`// in EX stage (e.g. inside multiplier)`
223			`//`
224			`always @(posedge rst or posedge clk)`
225			`if (rst)`
226			`mac_stall_r <= #1 1'b0;`
227			`else`
228			`mac_stall_r <= #1 (\|mac_op \| (\|mac_op_r1) \| (\|mac_op_r2)) & id_macrc_op;`
229
230			`endmodule`