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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [or1200.old/] [or1200_rf.v] - Blame information for rev 1765

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1 746 lampret
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's register file inside CPU                           ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Instantiation of register file memories                     ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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// Revision 1.1  2002/01/03 08:16:15  lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.13  2001/11/20 18:46:15  simons
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// Break point bug fixed
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//
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// Revision 1.12  2001/11/13 10:02:21  lampret
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// Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
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//
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// Revision 1.11  2001/11/12 01:45:40  lampret
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// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
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//
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// Revision 1.10  2001/11/10 03:43:57  lampret
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// Fixed exceptions.
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//
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// Revision 1.9  2001/10/21 17:57:16  lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.8  2001/10/14 13:12:10  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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// Revision 1.3  2001/08/09 13:39:33  lampret
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// Major clean-up.
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//
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// Revision 1.2  2001/07/22 03:31:54  lampret
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// Fixed RAM's oen bug. Cache bypass under development.
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//
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// Revision 1.1  2001/07/20 00:46:21  lampret
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// Development version of RTL. Libraries are missing.
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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87
module or1200_rf(
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        // Clock and reset
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        clk, rst,
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91
        // Write i/f
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        supv, wb_freeze, addrw, dataw, we, flushpipe,
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94
        // Read i/f
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        id_freeze, addra, addrb, dataa, datab, rda, rdb,
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97
        // Debug
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        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
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);
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101
parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
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104
//
105
// I/O
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//
107
 
108
//
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// Clock and reset
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//
111
input                           clk;
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input                           rst;
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114
//
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// Write i/f
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//
117
input                           supv;
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input                           wb_freeze;
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input   [aw-1:0]         addrw;
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input   [dw-1:0]         dataw;
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input                           we;
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input                           flushpipe;
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124
//
125
// Read i/f
126
//
127
input                           id_freeze;
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input   [aw-1:0]         addra;
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input   [aw-1:0]         addrb;
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output  [dw-1:0]         dataa;
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output  [dw-1:0]         datab;
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input                           rda;
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input                           rdb;
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135
//
136
// SPR access for debugging purposes
137
//
138
input                           spr_cs;
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input                           spr_write;
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input   [31:0]                   spr_addr;
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input   [31:0]                   spr_dat_i;
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output  [31:0]                   spr_dat_o;
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144
//
145
// Internal wires and regs
146
//
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wire    [dw-1:0]         from_rfa;
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wire    [dw-1:0]         from_rfb;
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reg     [dw:0]                   dataa_saved;
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reg     [dw:0]                   datab_saved;
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wire    [aw-1:0]         rf_addra;
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wire    [aw-1:0]         rf_addrw;
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wire    [dw-1:0]         rf_dataw;
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wire                            rf_we;
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wire                            spr_valid;
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wire                            rf_ena;
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wire                            rf_enb;
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reg                             rf_we_allow;
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160
//
161
// SPR access is valid when spr_cs is asserted and
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// SPR address matches GPR addresses
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//
164
assign spr_valid = spr_cs & (spr_addr[10:5] == `OR1200_SPR_RF);
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166
//
167
// SPR data output is always from RF A
168
//
169
assign spr_dat_o = from_rfa;
170
 
171
//
172
// Operand A comes from RF or from saved A register
173
//
174
assign dataa = (dataa_saved[32]) ? dataa_saved[31:0] : from_rfa;
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176
//
177
// Operand B comes from RF or from saved B register
178
//
179
assign datab = (datab_saved[32]) ? datab_saved[31:0] : from_rfb;
180
 
181
//
182
// RF A read address is either from SPRS or normal from CPU control
183
//
184
assign rf_addra = (spr_valid & !spr_write) ? spr_addr[4:0] : addra;
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186
//
187
// RF write address is either from SPRS or normal from CPU control
188
//
189
assign rf_addrw = (spr_valid & spr_write) ? spr_addr[4:0] : addrw;
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191
//
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// RF write data is either from SPRS or normal from CPU datapath
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//
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assign rf_dataw = (spr_valid & spr_write) ? spr_dat_i : dataw;
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196
//
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// RF write enable is either from SPRS or normal from CPU control
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//
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always @(posedge rst or posedge clk)
200
        if (rst)
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                rf_we_allow <= #1 1'b1;
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        else if (~wb_freeze)
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                rf_we_allow <= #1 ~flushpipe;
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assign rf_we = ((spr_valid & spr_write) | (we & ~wb_freeze)) & rf_we_allow & (supv | (|rf_addrw));
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207
//
208
// CS RF A asserted when instruction reads operand A and ID stage
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// is not stalled
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//
211
assign rf_ena = rda & ~id_freeze | spr_valid;   // probably works with fixed binutils
212
// assign rf_ena = 1'b1;                        // does not work with single-stepping
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//assign rf_ena = ~id_freeze | spr_valid;       // works with broken binutils 
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215
//
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// CS RF B asserted when instruction reads operand B and ID stage
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// is not stalled
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//
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assign rf_enb = rdb & ~id_freeze | spr_valid;
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// assign rf_enb = 1'b1;
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//assign rf_enb = ~id_freeze | spr_valid;       // works with broken binutils 
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223
//
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// Stores operand from RF_A into temp reg when pipeline is frozen
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//
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always @(posedge clk or posedge rst)
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        if (rst) begin
228
                dataa_saved <= #1 33'b0;
229
        end
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        else if (id_freeze & !dataa_saved[32]) begin
231
                dataa_saved <= #1 {1'b1, from_rfa};
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        end
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        else if (!id_freeze)
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                dataa_saved <= #1 33'b0;
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//
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// Stores operand from RF_B into temp reg when pipeline is frozen
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//
239
always @(posedge clk or posedge rst)
240
        if (rst) begin
241
                datab_saved <= #1 33'b0;
242
        end
243
        else if (id_freeze & !datab_saved[32]) begin
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                datab_saved <= #1 {1'b1, from_rfb};
245
        end
246
        else if (!id_freeze)
247
                datab_saved <= #1 33'b0;
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249
`ifdef OR1200_RFRAM_TWOPORT
250
 
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//
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// Instantiation of register file two-port RAM A
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//
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or1200_tpram_32x32 rf_a(
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        // Port A
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        .clk_a(clk),
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        .rst_a(rst),
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        .ce_a(rf_ena),
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        .we_a(1'b0),
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        .oe_a(1'b1),
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        .addr_a(rf_addra),
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        .di_a(32'h0000_0000),
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        .do_a(from_rfa),
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        // Port B
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        .clk_b(clk),
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        .rst_b(rst),
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        .ce_b(rf_we),
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        .we_b(rf_we),
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        .oe_b(1'b0),
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        .addr_b(rf_addrw),
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        .di_b(rf_dataw),
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        .do_b()
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);
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//
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// Instantiation of register file two-port RAM B
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//
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or1200_tpram_32x32 rf_b(
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        // Port A
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        .clk_a(clk),
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        .rst_a(rst),
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        .ce_a(rf_enb),
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        .we_a(1'b0),
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        .oe_a(1'b1),
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        .addr_a(addrb),
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        .di_a(32'h0000_0000),
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        .do_a(from_rfb),
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        // Port B
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        .clk_b(clk),
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        .rst_b(rst),
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        .ce_b(rf_we),
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        .we_b(rf_we),
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        .oe_b(1'b0),
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        .addr_b(rf_addrw),
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        .di_b(rf_dataw),
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        .do_b()
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);
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301
`else
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303
//
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// Instantiation of register file two-port RAM A
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//
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or1200_dpram_32x32 rf_a(
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        // Port A
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        .clk_a(clk),
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        .rst_a(rst),
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        .ce_a(rf_ena),
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        .oe_a(1'b1),
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        .addr_a(rf_addra),
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        .do_a(from_rfa),
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        // Port B
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        .clk_b(clk),
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        .rst_b(rst),
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        .ce_b(rf_we),
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        .we_b(rf_we),
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        .addr_b(rf_addrw),
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        .di_b(rf_dataw)
322
);
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324
//
325
// Instantiation of register file two-port RAM B
326
//
327
or1200_dpram_32x32 rf_b(
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        // Port A
329
        .clk_a(clk),
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        .rst_a(rst),
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        .ce_a(rf_enb),
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        .oe_a(1'b1),
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        .addr_a(addrb),
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        .do_a(from_rfb),
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        // Port B
337
        .clk_b(clk),
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        .rst_b(rst),
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        .ce_b(rf_we),
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        .we_b(rf_we),
341
        .addr_b(rf_addrw),
342
        .di_b(rf_dataw)
343
);
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345
`endif
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endmodule

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