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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs (Altera etc)                         ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8  2001/11/02 18:57:14  lampret
// Modified virtual silicon instantiations.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_2048x8(
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, do
);
 
//
// Default address and data buses width
//
parameter aw = 11;
parameter dw = 8;
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] do;     // output data bus
 
//
// Internal wires and registers
//
 
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_2048x8 #(dw, 1<<aw, aw) artisan_ssp(
`else
art_hssp_2048x8 artisan_ssp(
`endif
        .clk(clk),
        .cen(~ce),
        .wen(~we),
        .a(addr),
        .d(di),
        .oen(~oe),
        .q(do)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .do(do)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(do)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_2048x8 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
vs_hdsp_2048x8 vs_ssp(
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(do)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S2 ramb4_s2_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[1:0]),
        .EN(ce),
        .WE(we),
        .DO(do[1:0])
);
 
//
// Block 1
//
RAMB4_S2 ramb4_s2_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[3:2]),
        .EN(ce),
        .WE(we),
        .DO(do[3:2])
);
 
//
// Block 2
//
RAMB4_S2 ramb4_s2_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[5:4]),
        .EN(ce),
        .WE(we),
        .DO(do[5:4])
);
 
//
// Block 3
//
RAMB4_S2 ramb4_s2_3(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:6]),
        .EN(ce),
        .WE(we),
        .DO(do[7:6])
);
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [dw-1:0] do_reg;                 // RAM data output register
 
//
// Data output drivers
//
assign do = (oe) ? do_reg : {dw{1'bz}};
 
//
// RAM read and write
//
always @(posedge clk)
        if (ce && !we)
                do_reg <= #1 mem[addr];
        else if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_XILINX_RAMB4_S16
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [or1200.old/] [or1200_spram_2048x8.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB4_S16 ////`
26			`//// ////`
27			`//// To Do: ////`
28			`//// - xilinx rams need external tri-state logic ////`
29			`//// - fix avant! two-port ram ////`
30			`//// - add additional RAMs (Altera etc) ////`
31			`//// ////`
32			`//// Author(s): ////`
33			`//// - Damjan Lampret, lampret@opencores.org ////`
34			`//// ////`
35			`//////////////////////////////////////////////////////////////////////`
36			`//// ////`
37			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
38			`//// ////`
39			`//// This source file may be used and distributed without ////`
40			`//// restriction provided that this copyright statement is not ////`
41			`//// removed from the file and that any derivative work contains ////`
42			`//// the original copyright notice and the associated disclaimer. ////`
43			`//// ////`
44			`//// This source file is free software; you can redistribute it ////`
45			`//// and/or modify it under the terms of the GNU Lesser General ////`
46			`//// Public License as published by the Free Software Foundation; ////`
47			`//// either version 2.1 of the License, or (at your option) any ////`
48			`//// later version. ////`
49			`//// ////`
50			`//// This source is distributed in the hope that it will be ////`
51			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
52			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
53			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
54			`//// details. ////`
55			`//// ////`
56			`//// You should have received a copy of the GNU Lesser General ////`
57			`//// Public License along with this source; if not, download it ////`
58			`//// from http://www.opencores.org/lgpl.shtml ////`
59			`//// ////`
60			`//////////////////////////////////////////////////////////////////////`
61			`//`
62			`// CVS Revision History`
63			`//`
64			`// $Log: not supported by cvs2svn $`
65			`// Revision 1.1 2002/01/03 08:16:15 lampret`
66			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
67			`//`
68			`// Revision 1.8 2001/11/02 18:57:14 lampret`
69			`// Modified virtual silicon instantiations.`
70			`//`
71			`// Revision 1.7 2001/10/21 17:57:16 lampret`
72			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
73			`//`
74			`// Revision 1.6 2001/10/14 13:12:09 lampret`
75			`// MP3 version.`
76			`//`
77			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
78			`// no message`
79			`//`
80			`// Revision 1.1 2001/08/09 13:39:33 lampret`
81			`// Major clean-up.`
82			`//`
83			`// Revision 1.2 2001/07/30 05:38:02 lampret`
84			`// Adding empty directories required by HDL coding guidelines`
85			`//`
86			`//`
87
88			`// synopsys translate_off`
89			`include "timescale.v"
90			`// synopsys translate_on`
91			`include "or1200_defines.v"
92
93			`module or1200_spram_2048x8(`
94			`// Generic synchronous single-port RAM interface`
95			`clk, rst, ce, we, oe, addr, di, do`
96			`);`
97
98			`//`
99			`// Default address and data buses width`
100			`//`
101			`parameter aw = 11;`
102			`parameter dw = 8;`
103
104			`//`
105			`// Generic synchronous single-port RAM interface`
106			`//`
107			`input clk; // Clock`
108			`input rst; // Reset`
109			`input ce; // Chip enable input`
110			`input we; // Write enable input`
111			`input oe; // Output enable input`
112			`input [aw-1:0] addr; // address bus inputs`
113			`input [dw-1:0] di; // input data bus`
114			`output [dw-1:0] do; // output data bus`
115
116			`//`
117			`// Internal wires and registers`
118			`//`
119
120
121			`ifdef OR1200_ARTISAN_SSP
122
123			`//`
124			`// Instantiation of ASIC memory:`
125			`//`
126			`// Artisan Synchronous Single-Port RAM (ra1sh)`
127			`//`
128			`ifdef UNUSED
129			`art_hssp_2048x8 #(dw, 1<<aw, aw) artisan_ssp(`
130			`else
131			`art_hssp_2048x8 artisan_ssp(`
132			`endif
133			`.clk(clk),`
134			`.cen(~ce),`
135			`.wen(~we),`
136			`.a(addr),`
137			`.d(di),`
138			`.oen(~oe),`
139			`.q(do)`
140			`);`
141
142			`else
143
144			`ifdef OR1200_AVANT_ATP
145
146			`//`
147			`// Instantiation of ASIC memory:`
148			`//`
149			`// Avant! Asynchronous Two-Port RAM`
150			`//`
151			`avant_atp avant_atp(`
152			`.web(~we),`
153			`.reb(),`
154			`.oeb(~oe),`
155			`.rcsb(),`
156			`.wcsb(),`
157			`.ra(addr),`
158			`.wa(addr),`
159			`.di(di),`
160			`.do(do)`
161			`);`
162
163			`else
164
165			`ifdef OR1200_VIRAGE_SSP
166
167			`//`
168			`// Instantiation of ASIC memory:`
169			`//`
170			`// Virage Synchronous 1-port R/W RAM`
171			`//`
172			`virage_ssp virage_ssp(`
173			`.clk(clk),`
174			`.adr(addr),`
175			`.d(di),`
176			`.we(we),`
177			`.oe(oe),`
178			`.me(ce),`
179			`.q(do)`
180			`);`
181
182			`else
183
184			`ifdef OR1200_VIRTUALSILICON_SSP
185
186			`//`
187			`// Instantiation of ASIC memory:`
188			`//`
189			`// Virtual Silicon Single-Port Synchronous SRAM`
190			`//`
191			`ifdef UNUSED
192			`vs_hdsp_2048x8 #(1<<aw, aw-1, dw-1) vs_ssp(`
193			`else
194			`vs_hdsp_2048x8 vs_ssp(`
195			`endif
196			`.CK(clk),`
197			`.ADR(addr),`
198			`.DI(di),`
199			`.WEN(~we),`
200			`.CEN(~ce),`
201			`.OEN(~oe),`
202			`.DOUT(do)`
203			`);`
204
205			`else
206
207			`ifdef OR1200_XILINX_RAMB4
208
209			`//`
210			`// Instantiation of FPGA memory:`
211			`//`
212			`// Virtex/Spartan2`
213			`//`
214
215			`//`
216			`// Block 0`
217			`//`
218			`RAMB4_S2 ramb4_s2_0(`
219			`.CLK(clk),`
220			`.RST(rst),`
221			`.ADDR(addr),`
222			`.DI(di[1:0]),`
223			`.EN(ce),`
224			`.WE(we),`
225			`.DO(do[1:0])`
226			`);`
227
228			`//`
229			`// Block 1`
230			`//`
231			`RAMB4_S2 ramb4_s2_1(`
232			`.CLK(clk),`
233			`.RST(rst),`
234			`.ADDR(addr),`
235			`.DI(di[3:2]),`
236			`.EN(ce),`
237			`.WE(we),`
238			`.DO(do[3:2])`
239			`);`
240
241			`//`
242			`// Block 2`
243			`//`
244			`RAMB4_S2 ramb4_s2_2(`
245			`.CLK(clk),`
246			`.RST(rst),`
247			`.ADDR(addr),`
248			`.DI(di[5:4]),`
249			`.EN(ce),`
250			`.WE(we),`
251			`.DO(do[5:4])`
252			`);`
253
254			`//`
255			`// Block 3`
256			`//`
257			`RAMB4_S2 ramb4_s2_3(`
258			`.CLK(clk),`
259			`.RST(rst),`
260			`.ADDR(addr),`
261			`.DI(di[7:6]),`
262			`.EN(ce),`
263			`.WE(we),`
264			`.DO(do[7:6])`
265			`);`
266
267			`else
268
269			`//`
270			`// Generic single-port synchronous RAM model`
271			`//`
272
273			`//`
274			`// Generic RAM's registers and wires`
275			`//`
276			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
277			`reg [dw-1:0] do_reg; // RAM data output register`
278
279			`//`
280			`// Data output drivers`
281			`//`
282			`assign do = (oe) ? do_reg : {dw{1'bz}};`
283
284			`//`
285			`// RAM read and write`
286			`//`
287			`always @(posedge clk)`
288			`if (ce && !we)`
289			`do_reg <= #1 mem[addr];`
290			`else if (ce && we)`
291			`mem[addr] <= #1 di;`
292
293			`endif // !OR1200_XILINX_RAMB4_S16
294			`endif // !OR1200_VIRTUALSILICON_SSP
295			`endif // !OR1200_VIRAGE_SSP
296			`endif // !OR1200_AVANT_ATP
297			`endif // !OR1200_ARTISAN_SSP
298
299			`endmodule`