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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [or1200.old/] [or1200_sprs.v] - Blame information for rev 1765

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1 746 lampret
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  OR1200's interface to SPRs                                  ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
9
////  Decoding of SPR addresses and access to SPRs                ////
10
////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46
// $Log: not supported by cvs2svn $
47
// Revision 1.6  2002/03/11 01:26:57  lampret
48
// Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.
49
//
50
// Revision 1.5  2002/02/01 19:56:54  lampret
51
// Fixed combinational loops.
52
//
53
// Revision 1.4  2002/01/23 07:52:36  lampret
54
// Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.
55
//
56
// Revision 1.3  2002/01/19 09:27:49  lampret
57
// SR[TEE] should be zero after reset.
58
//
59
// Revision 1.2  2002/01/18 07:56:00  lampret
60
// No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
61
//
62
// Revision 1.1  2002/01/03 08:16:15  lampret
63
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
64
//
65
// Revision 1.12  2001/11/23 21:42:31  simons
66
// Program counter divided to PPC and NPC.
67
//
68
// Revision 1.11  2001/11/23 08:38:51  lampret
69
// Changed DSR/DRR behavior and exception detection.
70
//
71
// Revision 1.10  2001/11/12 01:45:41  lampret
72
// Moved flag bit into SR. Changed RF enable from constant enable to dynamic enable for read ports.
73
//
74
// Revision 1.9  2001/10/21 17:57:16  lampret
75
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
76
//
77
// Revision 1.8  2001/10/14 13:12:10  lampret
78
// MP3 version.
79
//
80
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
82
//
83
// Revision 1.3  2001/08/13 03:36:20  lampret
84
// Added cfg regs. Moved all defines into one defines.v file. More cleanup.
85
//
86
// Revision 1.2  2001/08/09 13:39:33  lampret
87
// Major clean-up.
88
//
89
// Revision 1.1  2001/07/20 00:46:21  lampret
90
// Development version of RTL. Libraries are missing.
91
//
92
//
93
 
94
// synopsys translate_off
95
`include "timescale.v"
96
// synopsys translate_on
97
`include "or1200_defines.v"
98
 
99
module or1200_sprs(
100
                // Clk & Rst
101
                clk, rst,
102
 
103
                // Internal CPU interface
104
                flagforw, flag_we, flag, addrbase, addrofs, dat_i, alu_op, branch_op,
105
                epcr, eear, esr, except_start, except_started,
106
                to_wbmux, epcr_we, eear_we, esr_we, pc_we, sr,
107
                spr_dat_cfgr, spr_dat_rf, spr_dat_npc, spr_dat_ppc, spr_dat_mac,
108
 
109
                // From/to other RISC units
110
                spr_dat_pic, spr_dat_tt, spr_dat_pm,
111
                spr_dat_dmmu, spr_dat_immu, spr_dat_du,
112
                spr_addr, spr_dat_o, spr_cs, spr_we,
113
 
114
                du_addr, du_dat_du, du_read,
115
                du_write, du_dat_cpu
116
 
117
);
118
 
119
parameter width = `OR1200_OPERAND_WIDTH;
120
 
121
//
122
// I/O Ports
123
//
124
 
125
//
126
// Internal CPU interface
127
//
128
input                           clk;            // Clock
129
input                           rst;            // Reset
130
output                          flag;           // SR[F]
131
input                           flagforw;       // From ALU
132
input                           flag_we;        // From ALU
133
input   [width-1:0]              addrbase;       // SPR base address
134
input   [15:0]                   addrofs;        // SPR offset
135
input   [width-1:0]              dat_i;          // SPR write data
136
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;         // ALU operation
137
input   [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;      // Branch operation
138
input   [width-1:0]              epcr;           // EPCR0
139
input   [width-1:0]              eear;           // EEAR0
140
input   [`OR1200_SR_WIDTH-1:0]   esr;            // ESR0
141
input                           except_start;   // Start of exception
142
input                           except_started; // Exception was started
143
output  [width-1:0]              to_wbmux;       // For l.mfspr
144
output                          epcr_we;        // EPCR0 write enable
145
output                          eear_we;        // EEAR0 write enable
146
output                          esr_we;         // ESR0 write enable
147
output                          pc_we;          // PC write enable
148
output  [`OR1200_SR_WIDTH-1:0]           sr;             // SR
149
input   [31:0]                   spr_dat_cfgr;   // Data from CFGR
150
input   [31:0]                   spr_dat_rf;     // Data from RF
151
input   [31:0]                   spr_dat_npc;    // Data from NPC
152
input   [31:0]                   spr_dat_ppc;    // Data from PPC   
153
input   [31:0]                   spr_dat_mac;    // Data from MAC
154
 
155
//
156
// To/from other RISC units
157
//
158
input   [31:0]                   spr_dat_pic;    // Data from PIC
159
input   [31:0]                   spr_dat_tt;     // Data from TT
160
input   [31:0]                   spr_dat_pm;     // Data from PM
161
input   [31:0]                   spr_dat_dmmu;   // Data from DMMU
162
input   [31:0]                   spr_dat_immu;   // Data from IMMU
163
input   [31:0]                   spr_dat_du;     // Data from DU
164
output  [31:0]                   spr_addr;       // SPR Address
165
output  [31:0]                   spr_dat_o;      // Data to unit
166
output  [31:0]                   spr_cs;         // Unit select
167
output                          spr_we;         // SPR write enable
168
 
169
//
170
// To/from Debug Unit
171
//
172
input   [width-1:0]              du_addr;        // Address
173
input   [width-1:0]              du_dat_du;      // Data from DU to SPRS
174
input                           du_read;        // Read qualifier
175
input                           du_write;       // Write qualifier
176
output  [width-1:0]              du_dat_cpu;     // Data from SPRS to DU
177
 
178
//
179
// Internal regs & wires
180
//
181
reg     [`OR1200_SR_WIDTH-1:0]           sr;             // SR
182
reg                             write_spr;      // Write SPR
183
reg                             read_spr;       // Read SPR
184
reg     [width-1:0]              to_wbmux;       // For l.mfspr
185
wire                            sr_we;          // Write enable SR
186
wire                            cfgr_sel;       // Select for cfg regs
187
wire                            rf_sel;         // Select for RF
188
wire                            npc_sel;        // Select for NPC
189
wire                            ppc_sel;        // Select for PPC
190
wire                            sr_sel;         // Select for SR        
191
wire                            epcr_sel;       // Select for EPCR0
192
wire                            eear_sel;       // Select for EEAR0
193
wire                            esr_sel;        // Select for ESR0
194
wire    [31:0]                   sys_data;       // Read data from system SPRs
195
wire    [`OR1200_SR_WIDTH-1:0]           to_sr;          // Data to SR
196
wire                            du_access;      // Debug unit access
197
wire    [`OR1200_ALUOP_WIDTH-1:0]        sprs_op;        // ALU operation
198
reg     [31:0]                   unqualified_cs; // Unqualified chip selects
199
 
200
//
201
// Decide if it is debug unit access
202
//
203
assign du_access = du_read | du_write;
204
 
205
//
206
// Generate sprs opcode
207
//
208
assign sprs_op = du_write ? `OR1200_ALUOP_MTSR : du_read ? `OR1200_ALUOP_MFSR : alu_op;
209
 
210
//
211
// Generate SPR address from base address and offset
212
// OR from debug unit address
213
//
214
assign spr_addr = du_access ? du_addr : addrbase | {16'h0000, addrofs};
215
 
216
//
217
// SPR is written by debug unit or by l.mtspr
218
//
219
assign spr_dat_o = du_write ? du_dat_du : dat_i;
220
 
221
//
222
// debug unit data input:
223
//  - write into debug unit SPRs by debug unit itself
224
//  - read of SPRS by debug unit
225
//  - write into debug unit SPRs by l.mtspr
226
//
227
assign du_dat_cpu = du_write ? du_dat_du : du_read ? to_wbmux : dat_i;
228
 
229
//
230
// Write into SPRs when l.mtspr
231
//
232
assign spr_we = du_write | write_spr;
233
 
234
//
235
// Qualify chip selects
236
//
237
assign spr_cs = unqualified_cs & {32{read_spr | write_spr}};
238
 
239
//
240
// Decoding of groups
241
//
242
always @(spr_addr)
243
        case (spr_addr[`OR1200_SPR_GROUP_BITS]) // synopsys parallel_case
244
                `OR1200_SPR_GROUP_WIDTH'd00: unqualified_cs = 32'b00000000_00000000_00000000_00000001;
245
                `OR1200_SPR_GROUP_WIDTH'd01: unqualified_cs = 32'b00000000_00000000_00000000_00000010;
246
                `OR1200_SPR_GROUP_WIDTH'd02: unqualified_cs = 32'b00000000_00000000_00000000_00000100;
247
                `OR1200_SPR_GROUP_WIDTH'd03: unqualified_cs = 32'b00000000_00000000_00000000_00001000;
248
                `OR1200_SPR_GROUP_WIDTH'd04: unqualified_cs = 32'b00000000_00000000_00000000_00010000;
249
                `OR1200_SPR_GROUP_WIDTH'd05: unqualified_cs = 32'b00000000_00000000_00000000_00100000;
250
                `OR1200_SPR_GROUP_WIDTH'd06: unqualified_cs = 32'b00000000_00000000_00000000_01000000;
251
                `OR1200_SPR_GROUP_WIDTH'd07: unqualified_cs = 32'b00000000_00000000_00000000_10000000;
252
                `OR1200_SPR_GROUP_WIDTH'd08: unqualified_cs = 32'b00000000_00000000_00000001_00000000;
253
                `OR1200_SPR_GROUP_WIDTH'd09: unqualified_cs = 32'b00000000_00000000_00000010_00000000;
254
                `OR1200_SPR_GROUP_WIDTH'd10: unqualified_cs = 32'b00000000_00000000_00000100_00000000;
255
                `OR1200_SPR_GROUP_WIDTH'd11: unqualified_cs = 32'b00000000_00000000_00001000_00000000;
256
                `OR1200_SPR_GROUP_WIDTH'd12: unqualified_cs = 32'b00000000_00000000_00010000_00000000;
257
                `OR1200_SPR_GROUP_WIDTH'd13: unqualified_cs = 32'b00000000_00000000_00100000_00000000;
258
                `OR1200_SPR_GROUP_WIDTH'd14: unqualified_cs = 32'b00000000_00000000_01000000_00000000;
259
                `OR1200_SPR_GROUP_WIDTH'd15: unqualified_cs = 32'b00000000_00000000_10000000_00000000;
260
                `OR1200_SPR_GROUP_WIDTH'd16: unqualified_cs = 32'b00000000_00000001_00000000_00000000;
261
                `OR1200_SPR_GROUP_WIDTH'd17: unqualified_cs = 32'b00000000_00000010_00000000_00000000;
262
                `OR1200_SPR_GROUP_WIDTH'd18: unqualified_cs = 32'b00000000_00000100_00000000_00000000;
263
                `OR1200_SPR_GROUP_WIDTH'd19: unqualified_cs = 32'b00000000_00001000_00000000_00000000;
264
                `OR1200_SPR_GROUP_WIDTH'd20: unqualified_cs = 32'b00000000_00010000_00000000_00000000;
265
                `OR1200_SPR_GROUP_WIDTH'd21: unqualified_cs = 32'b00000000_00100000_00000000_00000000;
266
                `OR1200_SPR_GROUP_WIDTH'd22: unqualified_cs = 32'b00000000_01000000_00000000_00000000;
267
                `OR1200_SPR_GROUP_WIDTH'd23: unqualified_cs = 32'b00000000_10000000_00000000_00000000;
268
                `OR1200_SPR_GROUP_WIDTH'd24: unqualified_cs = 32'b00000001_00000000_00000000_00000000;
269
                `OR1200_SPR_GROUP_WIDTH'd25: unqualified_cs = 32'b00000010_00000000_00000000_00000000;
270
                `OR1200_SPR_GROUP_WIDTH'd26: unqualified_cs = 32'b00000100_00000000_00000000_00000000;
271
                `OR1200_SPR_GROUP_WIDTH'd27: unqualified_cs = 32'b00001000_00000000_00000000_00000000;
272
                `OR1200_SPR_GROUP_WIDTH'd28: unqualified_cs = 32'b00010000_00000000_00000000_00000000;
273
                `OR1200_SPR_GROUP_WIDTH'd29: unqualified_cs = 32'b00100000_00000000_00000000_00000000;
274
                `OR1200_SPR_GROUP_WIDTH'd30: unqualified_cs = 32'b01000000_00000000_00000000_00000000;
275
                `OR1200_SPR_GROUP_WIDTH'd31: unqualified_cs = 32'b10000000_00000000_00000000_00000000;
276
        endcase
277
 
278
//
279
// SPRs System Group
280
//
281
 
282
//
283
// What to write into SR
284
//
285
assign to_sr = (branch_op == `OR1200_BRANCHOP_RFE) ? esr : {1'b1, spr_dat_o[`OR1200_SR_WIDTH-2:0]};
286
 
287
//
288
// Selects for system SPRs
289
//
290
assign cfgr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:4] == `OR1200_SPR_CFGR));
291
assign rf_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:5] == `OR1200_SPR_RF));
292
assign npc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_NPC));
293
assign ppc_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_PPC));
294
assign sr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_SR));
295
assign epcr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EPCR));
296
assign eear_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_EEAR));
297
assign esr_sel = (spr_cs[`OR1200_SPR_GROUP_SYS] && (spr_addr[10:0] == `OR1200_SPR_ESR));
298
 
299
//
300
// Write enables for system SPRs
301
//
302
assign sr_we = (write_spr && sr_sel) | (branch_op == `OR1200_BRANCHOP_RFE);
303
assign pc_we = (write_spr && (npc_sel | ppc_sel));
304
assign epcr_we = (write_spr && epcr_sel);
305
assign eear_we = (write_spr && eear_sel);
306
assign esr_we = (write_spr && esr_sel);
307
 
308
//
309
// Output from system SPRs
310
//
311
assign sys_data = (spr_dat_cfgr & {32{read_spr & cfgr_sel}}) |
312
                  (spr_dat_rf & {32{read_spr & rf_sel}}) |
313
                  (spr_dat_npc & {32{read_spr & npc_sel}}) |
314
                  (spr_dat_ppc & {32{read_spr & ppc_sel}}) |
315
                  ({{32-`OR1200_SR_WIDTH{1'b0}},sr} & {32{read_spr & sr_sel}}) |
316
                  (epcr & {32{read_spr & epcr_sel}}) |
317
                  (eear & {32{read_spr & eear_sel}}) |
318
                  ({{32-`OR1200_SR_WIDTH{1'b0}},esr} & {32{read_spr & esr_sel}});
319
 
320
//
321
// Flag alias
322
//
323
assign flag = sr[`OR1200_SR_F];
324
 
325
//
326
// Supervision register
327
//
328
always @(posedge clk or posedge rst)
329
        if (rst)
330
                sr <= #1 {1'b1, {`OR1200_SR_WIDTH-2{1'b0}}, 1'b1};
331
        else if (except_started) begin
332
                sr[`OR1200_SR_SM] <= #1 1'b1;
333
                sr[`OR1200_SR_TEE] <= #1 1'b0;
334
                sr[`OR1200_SR_IEE] <= #1 1'b0;
335
                sr[`OR1200_SR_DME] <= #1 1'b0;
336
                sr[`OR1200_SR_IME] <= #1 1'b0;
337
        end
338
        else if (sr_we)
339
                sr <= #1 to_sr[`OR1200_SR_WIDTH-1:0];
340
        else if (flag_we)
341
                sr[`OR1200_SR_F] <= #1 flagforw;
342
 
343
//
344
// MTSPR/MFSPR interface
345
//
346
always @(sprs_op or spr_addr or sys_data or spr_dat_mac or spr_dat_pic or spr_dat_pm or
347
        spr_dat_dmmu or spr_dat_immu or spr_dat_du or spr_dat_tt) begin
348
        case (sprs_op)  // synopsys full_case parallel_case
349
                `OR1200_ALUOP_MTSR : begin
350
                        write_spr = 1'b1;
351
                        read_spr = 1'b0;
352
                        to_wbmux = 32'b0;
353
                end
354
                `OR1200_ALUOP_MFSR : begin
355
                        casex (spr_addr[`OR1200_SPR_GROUP_BITS])
356
                                `OR1200_SPR_GROUP_TT:
357
                                        to_wbmux = spr_dat_tt;
358
                                `OR1200_SPR_GROUP_PIC:
359
                                        to_wbmux = spr_dat_pic;
360
                                `OR1200_SPR_GROUP_PM:
361
                                        to_wbmux = spr_dat_pm;
362
                                `OR1200_SPR_GROUP_DMMU:
363
                                        to_wbmux = spr_dat_dmmu;
364
                                `OR1200_SPR_GROUP_IMMU:
365
                                        to_wbmux = spr_dat_immu;
366
                                `OR1200_SPR_GROUP_MAC:
367
                                        to_wbmux = spr_dat_mac;
368
                                `OR1200_SPR_GROUP_DU:
369
                                        to_wbmux = spr_dat_du;
370
                                `OR1200_SPR_GROUP_SYS:
371
                                        to_wbmux = sys_data;
372
                                default:
373
                                        to_wbmux = 32'b0;
374
                        endcase
375
                        write_spr = 1'b0;
376
                        read_spr = 1'b1;
377
                end
378
                default : begin
379
                        write_spr = 1'b0;
380
                        read_spr = 1'b0;
381
                        to_wbmux = 32'b0;
382
                end
383
        endcase
384
end
385
 
386
endmodule

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