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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [uart16550.old/] [uart_defines.v] - Blame information for rev 1765

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  uart_defines.v                                              ////
////                                                              ////
////                                                              ////
////  This file is part of the "UART 16550 compatible" project    ////
////  http://www.opencores.org/cores/uart16550/                   ////
////                                                              ////
////  Documentation related to this project:                      ////
////  - http://www.opencores.org/cores/uart16550/                 ////
////                                                              ////
////  Projects compatibility:                                     ////
////  - WISHBONE                                                  ////
////  RS232 Protocol                                              ////
////  16550D uart (mostly supported)                              ////
////                                                              ////
////  Overview (main Features):                                   ////
////  Defines of the Core                                         ////
////                                                              ////
////  Known problems (limits):                                    ////
////  None                                                        ////
////                                                              ////
////  To Do:                                                      ////
////  Nothing.                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - gorban@opencores.org                                  ////
////      - Jacob Gorban                                          ////
////      - Igor Mohor (igorm@opencores.org)                      ////
////                                                              ////
////  Created:        2001/05/12                                  ////
////  Last Updated:   2001/05/17                                  ////
////                  (See log for the revision history)          ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000, 2001 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.11  2002/02/19 16:56:05  mohor
// Endian define added. Big Byte Endian is selected by default.
//
// Revision 1.10  2001/12/11 08:55:40  mohor
// Scratch register define added.
//
// Revision 1.9  2001/12/03 21:44:29  gorban
// Updated specification documentation.
// Added full 32-bit data bus interface, now as default.
// Address is 5-bit wide in 32-bit data bus mode.
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
// My small test bench is modified to work with 32-bit mode.
//
// Revision 1.8  2001/11/26 21:38:54  gorban
// Lots of fixes:
// Break condition wasn't handled correctly at all.
// LSR bits could lose their values.
// LSR value after reset was wrong.
// Timing of THRE interrupt signal corrected.
// LSR bit 0 timing corrected.
//
// Revision 1.7  2001/08/24 21:01:12  mohor
// Things connected to parity changed.
// Clock devider changed.
//
// Revision 1.6  2001/08/23 16:05:05  mohor
// Stop bit bug fixed.
// Parity bug fixed.
// WISHBONE read cycle bug fixed,
// OE indicator (Overrun Error) bug fixed.
// PE indicator (Parity Error) bug fixed.
// Register read bug fixed.
//
// Revision 1.5  2001/05/31 20:08:01  gorban
// FIFO changes and other corrections.
//
// Revision 1.4  2001/05/21 19:12:02  gorban
// Corrected some Linter messages.
//
// Revision 1.3  2001/05/17 18:34:18  gorban
// First 'stable' release. Should be sythesizable now. Also added new header.
//
// Revision 1.0  2001-05-17 21:27:11+02  jacob
// Initial revision
//
//
 
// remove comments to restore use to the old version with 8 data bit interface
// in new mode (32bit bus), the wb_sel_i signal is used to pus data in correct place
// also, in 8-bit version there'll be no debugging features included
// `define DATA_BUS_WIDTH_8
 
`define BIG_BYTE_ENDIAN     // Defines endian
 
`ifdef DATA_BUS_WIDTH_8
 `define UART_ADDR_WIDTH 3
 `define UART_DATA_WIDTH 8
`else
 `define UART_ADDR_WIDTH 5
 `define UART_DATA_WIDTH 32
`endif
 
// Register addresses
`define UART_REG_RB     `UART_ADDR_WIDTH'd0     // receiver buffer
`define UART_REG_TR  `UART_ADDR_WIDTH'd0        // transmitter
`define UART_REG_IE     `UART_ADDR_WIDTH'd1     // Interrupt enable
`define UART_REG_II  `UART_ADDR_WIDTH'd2        // Interrupt identification
`define UART_REG_FC  `UART_ADDR_WIDTH'd2        // FIFO control
`define UART_REG_LC     `UART_ADDR_WIDTH'd3     // Line Control
`define UART_REG_MC     `UART_ADDR_WIDTH'd4     // Modem control
`define UART_REG_LS  `UART_ADDR_WIDTH'd5        // Line status
`define UART_REG_MS  `UART_ADDR_WIDTH'd6        // Modem status
`define UART_REG_SR  `UART_ADDR_WIDTH'd7        // Scratch register
`define UART_REG_DL1    `UART_ADDR_WIDTH'd0     // Divisor latch bytes (1-2)
`define UART_REG_DL2    `UART_ADDR_WIDTH'd1
 
// Interrupt Enable register bits
`define UART_IE_RDA     0        // Received Data available interrupt
`define UART_IE_THRE    1       // Transmitter Holding Register empty interrupt
`define UART_IE_RLS     2       // Receiver Line Status Interrupt
`define UART_IE_MS      3       // Modem Status Interrupt
 
// Interrupt Identification register bits
`define UART_II_IP      0        // Interrupt pending when 0
`define UART_II_II      3:1     // Interrupt identification
 
// Interrupt identification values for bits 3:1
`define UART_II_RLS     3'b011  // Receiver Line Status
`define UART_II_RDA     3'b010  // Receiver Data available
`define UART_II_TI      3'b110  // Timeout Indication
`define UART_II_THRE    3'b001  // Transmitter Holding Register empty
`define UART_II_MS      3'b000  // Modem Status
 
// FIFO Control Register bits
`define UART_FC_TL      1:0      // Trigger level
 
// FIFO trigger level values
`define UART_FC_1               2'b00
`define UART_FC_4               2'b01
`define UART_FC_8               2'b10
`define UART_FC_14      2'b11
 
// Line Control register bits
`define UART_LC_BITS    1:0      // bits in character
`define UART_LC_SB      2       // stop bits
`define UART_LC_PE      3       // parity enable
`define UART_LC_EP      4       // even parity
`define UART_LC_SP      5       // stick parity
`define UART_LC_BC      6       // Break control
`define UART_LC_DL      7       // Divisor Latch access bit
 
// Modem Control register bits
`define UART_MC_DTR     0
`define UART_MC_RTS     1
`define UART_MC_OUT1    2
`define UART_MC_OUT2    3
`define UART_MC_LB      4       // Loopback mode
 
// Line Status Register bits
`define UART_LS_DR      0        // Data ready
`define UART_LS_OE      1       // Overrun Error
`define UART_LS_PE      2       // Parity Error
`define UART_LS_FE      3       // Framing Error
`define UART_LS_BI      4       // Break interrupt
`define UART_LS_TFE     5       // Transmit FIFO is empty
`define UART_LS_TE      6       // Transmitter Empty indicator
`define UART_LS_EI      7       // Error indicator
 
// Modem Status Register bits
`define UART_MS_DCTS    0        // Delta signals
`define UART_MS_DDSR    1
`define UART_MS_TERI    2
`define UART_MS_DDCD    3
`define UART_MS_CCTS    4       // Complement signals
`define UART_MS_CDSR    5
`define UART_MS_CRI     6
`define UART_MS_CDCD    7
 
// FIFO parameter defines
 
`define UART_FIFO_WIDTH 8
`define UART_FIFO_DEPTH 16
`define UART_FIFO_POINTER_W     4
`define UART_FIFO_COUNTER_W     5
// receiver fifo has width 11 because it has break, parity and framing error bits
`define UART_FIFO_REC_WIDTH  11
 
 
`define VERBOSE_WB  0           // All activity on the WISHBONE is recorded
`define VERBOSE_LINE_STATUS 0   // Details about the lsr (line status register)
`define FAST_TEST   1           // 64/1024 packets are sent
 
 
 
 
 
 
 

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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [uart16550.old/] [uart_defines.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	746	lampret	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// uart_defines.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the "UART 16550 compatible" project ////`
7			`//// http://www.opencores.org/cores/uart16550/ ////`
8			`//// ////`
9			`//// Documentation related to this project: ////`
10			`//// - http://www.opencores.org/cores/uart16550/ ////`
11			`//// ////`
12			`//// Projects compatibility: ////`
13			`//// - WISHBONE ////`
14			`//// RS232 Protocol ////`
15			`//// 16550D uart (mostly supported) ////`
16			`//// ////`
17			`//// Overview (main Features): ////`
18			`//// Defines of the Core ////`
19			`//// ////`
20			`//// Known problems (limits): ////`
21			`//// None ////`
22			`//// ////`
23			`//// To Do: ////`
24			`//// Nothing. ////`
25			`//// ////`
26			`//// Author(s): ////`
27			`//// - gorban@opencores.org ////`
28			`//// - Jacob Gorban ////`
29			`//// - Igor Mohor (igorm@opencores.org) ////`
30			`//// ////`
31			`//// Created: 2001/05/12 ////`
32			`//// Last Updated: 2001/05/17 ////`
33			`//// (See log for the revision history) ////`
34			`//// ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000, 2001 Authors ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: not supported by cvs2svn $`
66			`// Revision 1.11 2002/02/19 16:56:05 mohor`
67			`// Endian define added. Big Byte Endian is selected by default.`
68			`//`
69			`// Revision 1.10 2001/12/11 08:55:40 mohor`
70			`// Scratch register define added.`
71			`//`
72			`// Revision 1.9 2001/12/03 21:44:29 gorban`
73			`// Updated specification documentation.`
74			`// Added full 32-bit data bus interface, now as default.`
75			`// Address is 5-bit wide in 32-bit data bus mode.`
76			`// Added wb_sel_i input to the core. It's used in the 32-bit mode.`
77			`// Added debug interface with two 32-bit read-only registers in 32-bit mode.`
78			`// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.`
79			`// My small test bench is modified to work with 32-bit mode.`
80			`//`
81			`// Revision 1.8 2001/11/26 21:38:54 gorban`
82			`// Lots of fixes:`
83			`// Break condition wasn't handled correctly at all.`
84			`// LSR bits could lose their values.`
85			`// LSR value after reset was wrong.`
86			`// Timing of THRE interrupt signal corrected.`
87			`// LSR bit 0 timing corrected.`
88			`//`
89			`// Revision 1.7 2001/08/24 21:01:12 mohor`
90			`// Things connected to parity changed.`
91			`// Clock devider changed.`
92			`//`
93			`// Revision 1.6 2001/08/23 16:05:05 mohor`
94			`// Stop bit bug fixed.`
95			`// Parity bug fixed.`
96			`// WISHBONE read cycle bug fixed,`
97			`// OE indicator (Overrun Error) bug fixed.`
98			`// PE indicator (Parity Error) bug fixed.`
99			`// Register read bug fixed.`
100			`//`
101			`// Revision 1.5 2001/05/31 20:08:01 gorban`
102			`// FIFO changes and other corrections.`
103			`//`
104			`// Revision 1.4 2001/05/21 19:12:02 gorban`
105			`// Corrected some Linter messages.`
106			`//`
107			`// Revision 1.3 2001/05/17 18:34:18 gorban`
108			`// First 'stable' release. Should be sythesizable now. Also added new header.`
109			`//`
110			`// Revision 1.0 2001-05-17 21:27:11+02 jacob`
111			`// Initial revision`
112			`//`
113			`//`
114
115			`// remove comments to restore use to the old version with 8 data bit interface`
116			`// in new mode (32bit bus), the wb_sel_i signal is used to pus data in correct place`
117			`// also, in 8-bit version there'll be no debugging features included`
118			// `define DATA_BUS_WIDTH_8
119
120			`define BIG_BYTE_ENDIAN // Defines endian
121
122			`ifdef DATA_BUS_WIDTH_8
123			`define UART_ADDR_WIDTH 3
124			`define UART_DATA_WIDTH 8
125			`else
126			`define UART_ADDR_WIDTH 5
127			`define UART_DATA_WIDTH 32
128			`endif
129
130			`// Register addresses`
131			`define UART_REG_RB `UART_ADDR_WIDTH'd0 // receiver buffer
132			`define UART_REG_TR `UART_ADDR_WIDTH'd0 // transmitter
133			`define UART_REG_IE `UART_ADDR_WIDTH'd1 // Interrupt enable
134			`define UART_REG_II `UART_ADDR_WIDTH'd2 // Interrupt identification
135			`define UART_REG_FC `UART_ADDR_WIDTH'd2 // FIFO control
136			`define UART_REG_LC `UART_ADDR_WIDTH'd3 // Line Control
137			`define UART_REG_MC `UART_ADDR_WIDTH'd4 // Modem control
138			`define UART_REG_LS `UART_ADDR_WIDTH'd5 // Line status
139			`define UART_REG_MS `UART_ADDR_WIDTH'd6 // Modem status
140			`define UART_REG_SR `UART_ADDR_WIDTH'd7 // Scratch register
141			`define UART_REG_DL1 `UART_ADDR_WIDTH'd0 // Divisor latch bytes (1-2)
142			`define UART_REG_DL2 `UART_ADDR_WIDTH'd1
143
144			`// Interrupt Enable register bits`
145			`define UART_IE_RDA 0 // Received Data available interrupt
146			`define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt
147			`define UART_IE_RLS 2 // Receiver Line Status Interrupt
148			`define UART_IE_MS 3 // Modem Status Interrupt
149
150			`// Interrupt Identification register bits`
151			`define UART_II_IP 0 // Interrupt pending when 0
152			`define UART_II_II 3:1 // Interrupt identification
153
154			`// Interrupt identification values for bits 3:1`
155			`define UART_II_RLS 3'b011 // Receiver Line Status
156			`define UART_II_RDA 3'b010 // Receiver Data available
157			`define UART_II_TI 3'b110 // Timeout Indication
158			`define UART_II_THRE 3'b001 // Transmitter Holding Register empty
159			`define UART_II_MS 3'b000 // Modem Status
160
161			`// FIFO Control Register bits`
162			`define UART_FC_TL 1:0 // Trigger level
163
164			`// FIFO trigger level values`
165			`define UART_FC_1 2'b00
166			`define UART_FC_4 2'b01
167			`define UART_FC_8 2'b10
168			`define UART_FC_14 2'b11
169
170			`// Line Control register bits`
171			`define UART_LC_BITS 1:0 // bits in character
172			`define UART_LC_SB 2 // stop bits
173			`define UART_LC_PE 3 // parity enable
174			`define UART_LC_EP 4 // even parity
175			`define UART_LC_SP 5 // stick parity
176			`define UART_LC_BC 6 // Break control
177			`define UART_LC_DL 7 // Divisor Latch access bit
178
179			`// Modem Control register bits`
180			`define UART_MC_DTR 0
181			`define UART_MC_RTS 1
182			`define UART_MC_OUT1 2
183			`define UART_MC_OUT2 3
184			`define UART_MC_LB 4 // Loopback mode
185
186			`// Line Status Register bits`
187			`define UART_LS_DR 0 // Data ready
188			`define UART_LS_OE 1 // Overrun Error
189			`define UART_LS_PE 2 // Parity Error
190			`define UART_LS_FE 3 // Framing Error
191			`define UART_LS_BI 4 // Break interrupt
192			`define UART_LS_TFE 5 // Transmit FIFO is empty
193			`define UART_LS_TE 6 // Transmitter Empty indicator
194			`define UART_LS_EI 7 // Error indicator
195
196			`// Modem Status Register bits`
197			`define UART_MS_DCTS 0 // Delta signals
198			`define UART_MS_DDSR 1
199			`define UART_MS_TERI 2
200			`define UART_MS_DDCD 3
201			`define UART_MS_CCTS 4 // Complement signals
202			`define UART_MS_CDSR 5
203			`define UART_MS_CRI 6
204			`define UART_MS_CDCD 7
205
206			`// FIFO parameter defines`
207
208			`define UART_FIFO_WIDTH 8
209			`define UART_FIFO_DEPTH 16
210			`define UART_FIFO_POINTER_W 4
211			`define UART_FIFO_COUNTER_W 5
212			`// receiver fifo has width 11 because it has break, parity and framing error bits`
213			`define UART_FIFO_REC_WIDTH 11
214
215
216			`define VERBOSE_WB 0 // All activity on the WISHBONE is recorded
217			`define VERBOSE_LINE_STATUS 0 // Details about the lsr (line status register)
218			`define FAST_TEST 1 // 64/1024 packets are sent
219
220
221
222
223
224
225