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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [rtl/] [verilog/] [uart16550.old/] [uart_regs.v] - Blame information for rev 746

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1 746 lampret
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  uart_regs.v                                                 ////
4
////                                                              ////
5
////                                                              ////
6
////  This file is part of the "UART 16550 compatible" project    ////
7
////  http://www.opencores.org/cores/uart16550/                   ////
8
////                                                              ////
9
////  Documentation related to this project:                      ////
10
////  - http://www.opencores.org/cores/uart16550/                 ////
11
////                                                              ////
12
////  Projects compatibility:                                     ////
13
////  - WISHBONE                                                  ////
14
////  RS232 Protocol                                              ////
15
////  16550D uart (mostly supported)                              ////
16
////                                                              ////
17
////  Overview (main Features):                                   ////
18
////  Registers of the uart 16550 core                            ////
19
////                                                              ////
20
////  Known problems (limits):                                    ////
21
////  Inserts 1 wait state in all WISHBONE transfers              ////
22
////                                                              ////
23
////  To Do:                                                      ////
24
////  Nothing or verification.                                    ////
25
////                                                              ////
26
////  Author(s):                                                  ////
27
////      - gorban@opencores.org                                  ////
28
////      - Jacob Gorban                                          ////
29
////      - Igor Mohor (igorm@opencores.org)                      ////
30
////                                                              ////
31
////  Created:        2001/05/12                                  ////
32
////  Last Updated:   (See log for the revision history           ////
33
////                                                              ////
34
////                                                              ////
35
//////////////////////////////////////////////////////////////////////
36
////                                                              ////
37
//// Copyright (C) 2000, 2001 Authors                             ////
38
////                                                              ////
39
//// This source file may be used and distributed without         ////
40
//// restriction provided that this copyright statement is not    ////
41
//// removed from the file and that any derivative work contains  ////
42
//// the original copyright notice and the associated disclaimer. ////
43
////                                                              ////
44
//// This source file is free software; you can redistribute it   ////
45
//// and/or modify it under the terms of the GNU Lesser General   ////
46
//// Public License as published by the Free Software Foundation; ////
47
//// either version 2.1 of the License, or (at your option) any   ////
48
//// later version.                                               ////
49
////                                                              ////
50
//// This source is distributed in the hope that it will be       ////
51
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
52
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
53
//// PURPOSE.  See the GNU Lesser General Public License for more ////
54
//// details.                                                     ////
55
////                                                              ////
56
//// You should have received a copy of the GNU Lesser General    ////
57
//// Public License along with this source; if not, download it   ////
58
//// from http://www.opencores.org/lgpl.shtml                     ////
59
////                                                              ////
60
//////////////////////////////////////////////////////////////////////
61
//
62
// CVS Revision History
63
//
64
// $Log: not supported by cvs2svn $
65
// Revision 1.37  2001/12/27 13:24:09  mohor
66
// lsr[7] was not showing overrun errors.
67
//
68
// Revision 1.36  2001/12/20 13:25:46  mohor
69
// rx push changed to be only one cycle wide.
70
//
71
// Revision 1.35  2001/12/19 08:03:34  mohor
72
// Warnings cleared.
73
//
74
// Revision 1.34  2001/12/19 07:33:54  mohor
75
// Synplicity was having troubles with the comment.
76
//
77
// Revision 1.33  2001/12/17 10:14:43  mohor
78
// Things related to msr register changed. After THRE IRQ occurs, and one
79
// character is written to the transmit fifo, the detection of the THRE bit in the
80
// LSR is delayed for one character time.
81
//
82
// Revision 1.32  2001/12/14 13:19:24  mohor
83
// MSR register fixed.
84
//
85
// Revision 1.31  2001/12/14 10:06:58  mohor
86
// After reset modem status register MSR should be reset.
87
//
88
// Revision 1.30  2001/12/13 10:09:13  mohor
89
// thre irq should be cleared only when being source of interrupt.
90
//
91
// Revision 1.29  2001/12/12 09:05:46  mohor
92
// LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).
93
//
94
// Revision 1.28  2001/12/10 19:52:41  gorban
95
// Scratch register added
96
//
97
// Revision 1.27  2001/12/06 14:51:04  gorban
98
// Bug in LSR[0] is fixed.
99
// All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.
100
//
101
// Revision 1.26  2001/12/03 21:44:29  gorban
102
// Updated specification documentation.
103
// Added full 32-bit data bus interface, now as default.
104
// Address is 5-bit wide in 32-bit data bus mode.
105
// Added wb_sel_i input to the core. It's used in the 32-bit mode.
106
// Added debug interface with two 32-bit read-only registers in 32-bit mode.
107
// Bits 5 and 6 of LSR are now only cleared on TX FIFO write.
108
// My small test bench is modified to work with 32-bit mode.
109
//
110
// Revision 1.25  2001/11/28 19:36:39  gorban
111
// Fixed: timeout and break didn't pay attention to current data format when counting time
112
//
113
// Revision 1.24  2001/11/26 21:38:54  gorban
114
// Lots of fixes:
115
// Break condition wasn't handled correctly at all.
116
// LSR bits could lose their values.
117
// LSR value after reset was wrong.
118
// Timing of THRE interrupt signal corrected.
119
// LSR bit 0 timing corrected.
120
//
121
// Revision 1.23  2001/11/12 21:57:29  gorban
122
// fixed more typo bugs
123
//
124
// Revision 1.22  2001/11/12 15:02:28  mohor
125
// lsr1r error fixed.
126
//
127
// Revision 1.21  2001/11/12 14:57:27  mohor
128
// ti_int_pnd error fixed.
129
//
130
// Revision 1.20  2001/11/12 14:50:27  mohor
131
// ti_int_d error fixed.
132
//
133
// Revision 1.19  2001/11/10 12:43:21  gorban
134
// Logic Synthesis bugs fixed. Some other minor changes
135
//
136
// Revision 1.18  2001/11/08 14:54:23  mohor
137
// Comments in Slovene language deleted, few small fixes for better work of
138
// old tools. IRQs need to be fix.
139
//
140
// Revision 1.17  2001/11/07 17:51:52  gorban
141
// Heavily rewritten interrupt and LSR subsystems.
142
// Many bugs hopefully squashed.
143
//
144
// Revision 1.16  2001/11/02 09:55:16  mohor
145
// no message
146
//
147
// Revision 1.15  2001/10/31 15:19:22  gorban
148
// Fixes to break and timeout conditions
149
//
150
// Revision 1.14  2001/10/29 17:00:46  gorban
151
// fixed parity sending and tx_fifo resets over- and underrun
152
//
153
// Revision 1.13  2001/10/20 09:58:40  gorban
154
// Small synopsis fixes
155
//
156
// Revision 1.12  2001/10/19 16:21:40  gorban
157
// Changes data_out to be synchronous again as it should have been.
158
//
159
// Revision 1.11  2001/10/18 20:35:45  gorban
160
// small fix
161
//
162
// Revision 1.10  2001/08/24 21:01:12  mohor
163
// Things connected to parity changed.
164
// Clock devider changed.
165
//
166
// Revision 1.9  2001/08/23 16:05:05  mohor
167
// Stop bit bug fixed.
168
// Parity bug fixed.
169
// WISHBONE read cycle bug fixed,
170
// OE indicator (Overrun Error) bug fixed.
171
// PE indicator (Parity Error) bug fixed.
172
// Register read bug fixed.
173
//
174
// Revision 1.10  2001/06/23 11:21:48  gorban
175
// DL made 16-bit long. Fixed transmission/reception bugs.
176
//
177
// Revision 1.9  2001/05/31 20:08:01  gorban
178
// FIFO changes and other corrections.
179
//
180
// Revision 1.8  2001/05/29 20:05:04  gorban
181
// Fixed some bugs and synthesis problems.
182
//
183
// Revision 1.7  2001/05/27 17:37:49  gorban
184
// Fixed many bugs. Updated spec. Changed FIFO files structure. See CHANGES.txt file.
185
//
186
// Revision 1.6  2001/05/21 19:12:02  gorban
187
// Corrected some Linter messages.
188
//
189
// Revision 1.5  2001/05/17 18:34:18  gorban
190
// First 'stable' release. Should be sythesizable now. Also added new header.
191
//
192
// Revision 1.0  2001-05-17 21:27:11+02  jacob
193
// Initial revision
194
//
195
//
196
 
197
// synopsys translate_off
198
`include "timescale.v"
199
// synopsys translate_on
200
 
201
`include "uart_defines.v"
202
 
203
`define UART_DL1 7:0
204
`define UART_DL2 15:8
205
 
206
module uart_regs (clk,
207
        wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i,
208
 
209
// additional signals
210
        modem_inputs,
211
        stx_pad_o, srx_pad_i,
212
 
213
`ifdef DATA_BUS_WIDTH_8
214
`else
215
// debug interface signals      enabled
216
ier, iir, fcr, mcr, lcr, msr, lsr, rf_count, tf_count, tstate, rstate,
217
`endif
218
        rts_pad_o, dtr_pad_o, int_o
219
        );
220
 
221
input                                                                   clk;
222
input                                                                   wb_rst_i;
223
input [`UART_ADDR_WIDTH-1:0]             wb_addr_i;
224
input [7:0]                                                      wb_dat_i;
225
output [7:0]                                                     wb_dat_o;
226
input                                                                   wb_we_i;
227
input                                                                   wb_re_i;
228
 
229
output                                                                  stx_pad_o;
230
input                                                                   srx_pad_i;
231
 
232
input [3:0]                                                      modem_inputs;
233
output                                                                  rts_pad_o;
234
output                                                                  dtr_pad_o;
235
output                                                                  int_o;
236
 
237
`ifdef DATA_BUS_WIDTH_8
238
`else
239
// if 32-bit databus and debug interface are enabled
240
output [3:0]                                                     ier;
241
output [3:0]                                                     iir;
242
output [1:0]                                                     fcr;  /// bits 7 and 6 of fcr. Other bits are ignored
243
output [4:0]                                                     mcr;
244
output [7:0]                                                     lcr;
245
output [7:0]                                                     msr;
246
output [7:0]                                                     lsr;
247
output [`UART_FIFO_COUNTER_W-1:0]        rf_count;
248
output [`UART_FIFO_COUNTER_W-1:0]        tf_count;
249
output [2:0]                                                     tstate;
250
output [3:0]                                                     rstate;
251
 
252
`endif
253
 
254
wire [3:0]                                                               modem_inputs;
255
reg                                                                             enable;
256
wire                                                                            stx_pad_o;              // received from transmitter module
257
wire                                                                            srx_pad_i;
258
 
259
reg [7:0]                                                                wb_dat_o;
260
 
261
wire [`UART_ADDR_WIDTH-1:0]              wb_addr_i;
262
wire [7:0]                                                               wb_dat_i;
263
 
264
 
265
reg [3:0]                                                                ier;
266
reg [3:0]                                                                iir;
267
reg [1:0]                                                                fcr;  /// bits 7 and 6 of fcr. Other bits are ignored
268
reg [4:0]                                                                mcr;
269
reg [7:0]                                                                lcr;
270
reg [7:0]                                                                msr;
271
reg [15:0]                                                               dl;  // 32-bit divisor latch
272
reg [7:0]                                                                scratch; // UART scratch register
273
reg                                                                             start_dlc; // activate dlc on writing to UART_DL1
274
reg                                                                             lsr_mask_d; // delay for lsr_mask condition
275
reg                                                                             msi_reset; // reset MSR 4 lower bits indicator
276
//reg                                                                           threi_clear; // THRE interrupt clear flag
277
reg [15:0]                                                               dlc;  // 32-bit divisor latch counter
278
reg                                                                             int_o;
279
 
280
reg [3:0]                                                                trigger_level; // trigger level of the receiver FIFO
281
reg                                                                             rx_reset;
282
reg                                                                             tx_reset;
283
 
284
wire                                                                            dlab;                      // divisor latch access bit
285
wire                                                                            cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i; // modem status bits
286
wire                                                                            loopback;                  // loopback bit (MCR bit 4)
287
wire                                                                            cts, dsr, ri, dcd;         // effective signals
288
wire                    cts_c, dsr_c, ri_c, dcd_c; // Complement effective signals (considering loopback)
289
wire                                                                            rts_pad_o, dtr_pad_o;              // modem control outputs
290
 
291
// LSR bits wires and regs
292
wire [7:0]                                                               lsr;
293
wire                                                                            lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7;
294
reg                                                                             lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r;
295
wire                                                                            lsr_mask; // lsr_mask
296
 
297
//
298
// ASSINGS
299
//
300
 
301
assign                                                                  lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r };
302
 
303
assign                                                                  {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
304
assign                                                                  {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
305
 
306
assign                  {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
307
                                                               : {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
308
 
309
assign                                                                  dlab = lcr[`UART_LC_DL];
310
assign                                                                  loopback = mcr[4];
311
 
312
// assign modem outputs
313
assign                                                                  rts_pad_o = mcr[`UART_MC_RTS];
314
assign                                                                  dtr_pad_o = mcr[`UART_MC_DTR];
315
 
316
// Interrupt signals
317
wire                                                                            rls_int;  // receiver line status interrupt
318
wire                                                                            rda_int;  // receiver data available interrupt
319
wire                                                                            ti_int;   // timeout indicator interrupt
320
wire                                                                            thre_int; // transmitter holding register empty interrupt
321
wire                                                                            ms_int;   // modem status interrupt
322
 
323
// FIFO signals
324
reg                                                                             tf_push;
325
reg                                                                             rf_pop;
326
wire [`UART_FIFO_REC_WIDTH-1:0]  rf_data_out;
327
wire                                                                            rf_error_bit; // an error (parity or framing) is inside the fifo
328
wire [`UART_FIFO_COUNTER_W-1:0]  rf_count;
329
wire [`UART_FIFO_COUNTER_W-1:0]  tf_count;
330
wire [2:0]                                                               tstate;
331
wire [3:0]                                                               rstate;
332
wire [9:0]                                                               counter_t;
333
 
334
wire                      thre_set_en; // THRE status is delayed one character time when a character is written to fifo.
335
reg  [7:0]                block_cnt;   // While counter counts, THRE status is blocked (delayed one character cycle)
336
reg  [7:0]                block_value; // One character length minus stop bit
337
 
338
// Transmitter Instance
339
uart_transmitter transmitter(clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
340
 
341
// Receiver Instance
342
uart_receiver receiver(clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
343
        counter_t, rf_count, rf_data_out, rf_error_bit, rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
344
 
345
 
346
// Asynchronous reading here because the outputs are sampled in uart_wb.v file 
347
always @(dl or dlab or ier or iir or scratch
348
                        or lcr or lsr or msr or rf_data_out or wb_addr_i or wb_re_i)   // asynchrounous reading
349
begin
350
        case (wb_addr_i)
351
                `UART_REG_RB   : wb_dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];
352
                `UART_REG_IE    : wb_dat_o = dlab ? dl[`UART_DL2] : ier;
353
                `UART_REG_II    : wb_dat_o = {4'b1100,iir};
354
                `UART_REG_LC    : wb_dat_o = lcr;
355
                `UART_REG_LS    : wb_dat_o = lsr;
356
                `UART_REG_MS    : wb_dat_o = msr;
357
                `UART_REG_SR    : wb_dat_o = scratch;
358
                default:  wb_dat_o = 8'b0; // ??
359
        endcase // case(wb_addr_i)
360
end // always @ (dl or dlab or ier or iir or scratch...
361
 
362
 
363
// rf_pop signal handling
364
always @(posedge clk or posedge wb_rst_i)
365
begin
366
        if (wb_rst_i)
367
                rf_pop <= #1 0;
368
        else
369
        if (rf_pop)     // restore the signal to 0 after one clock cycle
370
                rf_pop <= #1 0;
371
        else
372
        if (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab)
373
                rf_pop <= #1 1; // advance read pointer
374
end
375
 
376
wire    lsr_mask_condition;
377
wire    iir_read;
378
wire  msr_read;
379
wire    fifo_read;
380
wire    fifo_write;
381
 
382
assign lsr_mask_condition = (wb_re_i && wb_addr_i == `UART_REG_LS && !dlab);
383
assign iir_read = (wb_re_i && wb_addr_i == `UART_REG_II && !dlab);
384
assign msr_read = (wb_re_i && wb_addr_i == `UART_REG_MS && !dlab);
385
assign fifo_read = (wb_re_i && wb_addr_i == `UART_REG_RB && !dlab);
386
assign fifo_write = (wb_we_i && wb_addr_i == `UART_REG_TR && !dlab);
387
 
388
// lsr_mask_d delayed signal handling
389
always @(posedge clk or posedge wb_rst_i)
390
begin
391
        if (wb_rst_i)
392
                lsr_mask_d <= #1 0;
393
        else // reset bits in the Line Status Register
394
                lsr_mask_d <= #1 lsr_mask_condition;
395
end
396
 
397
// lsr_mask is rise detected
398
assign lsr_mask = lsr_mask_condition && ~lsr_mask_d;
399
 
400
// msi_reset signal handling
401
always @(posedge clk or posedge wb_rst_i)
402
begin
403
        if (wb_rst_i)
404
                msi_reset <= #1 1;
405
        else
406
        if (msi_reset)
407
                msi_reset <= #1 0;
408
        else
409
        if (msr_read)
410
                msi_reset <= #1 1; // reset bits in Modem Status Register
411
end
412
 
413
 
414
//
415
//   WRITES AND RESETS   //
416
//
417
// Line Control Register
418
always @(posedge clk or posedge wb_rst_i)
419
        if (wb_rst_i)
420
                lcr <= #1 8'b00000011; // 8n1 setting
421
        else
422
        if (wb_we_i && wb_addr_i==`UART_REG_LC)
423
                lcr <= #1 wb_dat_i;
424
 
425
// Interrupt Enable Register or UART_DL2
426
always @(posedge clk or posedge wb_rst_i)
427
        if (wb_rst_i)
428
        begin
429
                ier <= #1 4'b0000; // no interrupts after reset
430
                dl[`UART_DL2] <= #1 8'b0;
431
        end
432
        else
433
        if (wb_we_i && wb_addr_i==`UART_REG_IE)
434
                if (dlab)
435
                begin
436
                        dl[`UART_DL2] <= #1 wb_dat_i;
437
                end
438
                else
439
                        ier <= #1 wb_dat_i[3:0]; // ier uses only 4 lsb
440
 
441
 
442
// FIFO Control Register and rx_reset, tx_reset signals
443
always @(posedge clk or posedge wb_rst_i)
444
        if (wb_rst_i) begin
445
                fcr <= #1 2'b11;
446
                rx_reset <= #1 0;
447
                tx_reset <= #1 0;
448
        end else
449
        if (wb_we_i && wb_addr_i==`UART_REG_FC) begin
450
                fcr <= #1 wb_dat_i[7:6];
451
                rx_reset <= #1 wb_dat_i[1];
452
                tx_reset <= #1 wb_dat_i[2];
453
        end else begin
454
                rx_reset <= #1 0;
455
                tx_reset <= #1 0;
456
        end
457
 
458
// Modem Control Register
459
always @(posedge clk or posedge wb_rst_i)
460
        if (wb_rst_i)
461
                mcr <= #1 5'b0;
462
        else
463
        if (wb_we_i && wb_addr_i==`UART_REG_MC)
464
                        mcr <= #1 wb_dat_i[4:0];
465
 
466
// Scratch register
467
// Line Control Register
468
always @(posedge clk or posedge wb_rst_i)
469
        if (wb_rst_i)
470
                scratch <= #1 0; // 8n1 setting
471
        else
472
        if (wb_we_i && wb_addr_i==`UART_REG_SR)
473
                scratch <= #1 wb_dat_i;
474
 
475
// TX_FIFO or UART_DL1
476
always @(posedge clk or posedge wb_rst_i)
477
        if (wb_rst_i)
478
        begin
479
                dl[`UART_DL1]  <= #1 8'b0;
480
                tf_push   <= #1 1'b0;
481
                start_dlc <= #1 1'b0;
482
        end
483
        else
484
        if (wb_we_i && wb_addr_i==`UART_REG_TR)
485
                if (dlab)
486
                begin
487
                        dl[`UART_DL1] <= #1 wb_dat_i;
488
                        start_dlc <= #1 1'b1; // enable DL counter
489
                        tf_push <= #1 1'b0;
490
                end
491
                else
492
                begin
493
                        tf_push   <= #1 1'b1;
494
                        start_dlc <= #1 1'b0;
495
                end // else: !if(dlab)
496
        else
497
        begin
498
                start_dlc <= #1 1'b0;
499
                tf_push   <= #1 1'b0;
500
        end // else: !if(dlab)
501
 
502
// Receiver FIFO trigger level selection logic (asynchronous mux)
503
always @(fcr)
504
        case (fcr[`UART_FC_TL])
505
                2'b00 : trigger_level = 1;
506
                2'b01 : trigger_level = 4;
507
                2'b10 : trigger_level = 8;
508
                2'b11 : trigger_level = 14;
509
        endcase // case(fcr[`UART_FC_TL])
510
 
511
//
512
//  STATUS REGISTERS  //
513
//
514
 
515
// Modem Status Register
516
reg [3:0] delayed_modem_signals;
517
always @(posedge clk or posedge wb_rst_i)
518
begin
519
        if (wb_rst_i)
520
          begin
521
                msr <= #1 0;
522
                delayed_modem_signals[3:0] <= #1 0;
523
          end
524
        else begin
525
                msr[`UART_MS_DDCD:`UART_MS_DCTS] <= #1 msi_reset ? 4'b0 :
526
                        msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]);
527
                msr[`UART_MS_CDCD:`UART_MS_CCTS] <= #1 {dcd_c, ri_c, dsr_c, cts_c};
528
                delayed_modem_signals[3:0] <= #1 {dcd, ri, dsr, cts};
529
        end
530
end
531
 
532
 
533
// Line Status Register
534
 
535
// activation conditions
536
assign lsr0 = (rf_count==0 && rf_push_pulse);  // data in receiver fifo available set condition
537
assign lsr1 = rf_overrun;     // Receiver overrun error
538
assign lsr2 = rf_data_out[1]; // parity error bit
539
assign lsr3 = rf_data_out[0]; // framing error bit
540
assign lsr4 = rf_data_out[2]; // break error in the character
541
assign lsr5 = (tf_count==5'b0 && thre_set_en);  // transmitter fifo is empty
542
assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == /*`S_IDLE */ 0)); // transmitter empty
543
assign lsr7 = rf_error_bit | rf_overrun;
544
 
545
// lsr bit0 (receiver data available)
546
reg      lsr0_d;
547
 
548
always @(posedge clk or posedge wb_rst_i)
549
        if (wb_rst_i) lsr0_d <= #1 0;
550
        else lsr0_d <= #1 lsr0;
551
 
552
always @(posedge clk or posedge wb_rst_i)
553
        if (wb_rst_i) lsr0r <= #1 0;
554
        else lsr0r <= #1 (rf_count==1 && fifo_read || rx_reset) ? 0 : // deassert condition
555
                                          lsr0r || (lsr0 && ~lsr0_d); // set on rise of lsr0 and keep asserted until deasserted 
556
 
557
// lsr bit 1 (receiver overrun)
558
reg lsr1_d; // delayed
559
 
560
always @(posedge clk or posedge wb_rst_i)
561
        if (wb_rst_i) lsr1_d <= #1 0;
562
        else lsr1_d <= #1 lsr1;
563
 
564
always @(posedge clk or posedge wb_rst_i)
565
        if (wb_rst_i) lsr1r <= #1 0;
566
        else    lsr1r <= #1     lsr_mask ? 0 : lsr1r || (lsr1 && ~lsr1_d); // set on rise
567
 
568
// lsr bit 2 (parity error)
569
reg lsr2_d; // delayed
570
 
571
always @(posedge clk or posedge wb_rst_i)
572
        if (wb_rst_i) lsr2_d <= #1 0;
573
        else lsr2_d <= #1 lsr2;
574
 
575
always @(posedge clk or posedge wb_rst_i)
576
        if (wb_rst_i) lsr2r <= #1 0;
577
        else lsr2r <= #1 lsr_mask ? 0 : lsr2r || (lsr2 && ~lsr2_d); // set on rise
578
 
579
// lsr bit 3 (framing error)
580
reg lsr3_d; // delayed
581
 
582
always @(posedge clk or posedge wb_rst_i)
583
        if (wb_rst_i) lsr3_d <= #1 0;
584
        else lsr3_d <= #1 lsr3;
585
 
586
always @(posedge clk or posedge wb_rst_i)
587
        if (wb_rst_i) lsr3r <= #1 0;
588
        else lsr3r <= #1 lsr_mask ? 0 : lsr3r || (lsr3 && ~lsr3_d); // set on rise
589
 
590
// lsr bit 4 (break indicator)
591
reg lsr4_d; // delayed
592
 
593
always @(posedge clk or posedge wb_rst_i)
594
        if (wb_rst_i) lsr4_d <= #1 0;
595
        else lsr4_d <= #1 lsr4;
596
 
597
always @(posedge clk or posedge wb_rst_i)
598
        if (wb_rst_i) lsr4r <= #1 0;
599
        else lsr4r <= #1 lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d);
600
 
601
// lsr bit 5 (transmitter fifo is empty)
602
reg lsr5_d;
603
 
604
always @(posedge clk or posedge wb_rst_i)
605
        if (wb_rst_i) lsr5_d <= #1 1;
606
        else lsr5_d <= #1 lsr5;
607
 
608
always @(posedge clk or posedge wb_rst_i)
609
        if (wb_rst_i) lsr5r <= #1 1;
610
        else lsr5r <= #1 (fifo_write) ? 0 :  lsr5r || (lsr5 && ~lsr5_d);
611
 
612
// lsr bit 6 (transmitter empty indicator)
613
reg lsr6_d;
614
 
615
always @(posedge clk or posedge wb_rst_i)
616
        if (wb_rst_i) lsr6_d <= #1 1;
617
        else lsr6_d <= #1 lsr6;
618
 
619
always @(posedge clk or posedge wb_rst_i)
620
        if (wb_rst_i) lsr6r <= #1 1;
621
        else lsr6r <= #1 (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d);
622
 
623
// lsr bit 7 (error in fifo)
624
reg lsr7_d;
625
 
626
always @(posedge clk or posedge wb_rst_i)
627
        if (wb_rst_i) lsr7_d <= #1 0;
628
        else lsr7_d <= #1 lsr7;
629
 
630
always @(posedge clk or posedge wb_rst_i)
631
        if (wb_rst_i) lsr7r <= #1 0;
632
        else lsr7r <= #1 lsr_mask ? 0 : lsr7r || (lsr7 && ~lsr7_d);
633
 
634
// Frequency divider
635
always @(posedge clk or posedge wb_rst_i)
636
begin
637
        if (wb_rst_i)
638
                dlc <= #1 0;
639
        else
640
                if (start_dlc | ~ (|dlc))
641
                        dlc <= #1 dl - 1;               // preset counter
642
                else
643
                        dlc <= #1 dlc - 1;              // decrement counter
644
end
645
 
646
// Enable signal generation logic
647
always @(posedge clk or posedge wb_rst_i)
648
begin
649
        if (wb_rst_i)
650
                enable <= #1 1'b0;
651
        else
652
                if (|dl & ~(|dlc))     // dl>0 & dlc==0
653
                        enable <= #1 1'b1;
654
                else
655
                        enable <= #1 1'b0;
656
end
657
 
658
// Delaying THRE status for one character cycle after a character is written to an empty fifo.
659
always @(lcr)
660
  case (lcr[3:0])
661
    4'b0000                             : block_value =  95; // 6 bits
662
    4'b0100                             : block_value = 103; // 6.5 bits
663
    4'b0001, 4'b1000                    : block_value = 111; // 7 bits
664
    4'b1100                             : block_value = 119; // 7.5 bits
665
    4'b0010, 4'b0101, 4'b1001           : block_value = 127; // 8 bits
666
    4'b0011, 4'b0110, 4'b1010, 4'b1101  : block_value = 143; // 9 bits
667
    4'b0111, 4'b1011, 4'b1110           : block_value = 159; // 10 bits
668
    4'b1111                             : block_value = 175; // 11 bits
669
  endcase // case(lcr[3:0])
670
 
671
// Counting time of one character minus stop bit
672
always @(posedge clk or posedge wb_rst_i)
673
begin
674
  if (wb_rst_i)
675
    block_cnt <= #1 8'd0;
676
  else
677
  if(lsr5r & fifo_write)  // THRE bit set & write to fifo occured
678
    block_cnt <= #1 block_value;
679
  else
680
  if (enable & block_cnt != 8'b0)  // only work on enable times
681
    block_cnt <= #1 block_cnt - 1;  // decrement break counter
682
end // always of break condition detection
683
 
684
// Generating THRE status enable signal
685
assign thre_set_en = ~(|block_cnt);
686
 
687
 
688
//
689
//      INTERRUPT LOGIC
690
//
691
 
692
assign rls_int  = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]);
693
assign rda_int  = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level});
694
assign thre_int = ier[`UART_IE_THRE] && lsr[`UART_LS_TFE];
695
assign ms_int   = ier[`UART_IE_MS] && (| msr[3:0]);
696
assign ti_int   = ier[`UART_IE_RDA] && (counter_t == 10'b0);
697
 
698
reg      rls_int_d;
699
reg      thre_int_d;
700
reg      ms_int_d;
701
reg      ti_int_d;
702
reg      rda_int_d;
703
 
704
// delay lines
705
always  @(posedge clk or posedge wb_rst_i)
706
        if (wb_rst_i) rls_int_d <= #1 0;
707
        else rls_int_d <= #1 rls_int;
708
 
709
always  @(posedge clk or posedge wb_rst_i)
710
        if (wb_rst_i) rda_int_d <= #1 0;
711
        else rda_int_d <= #1 rda_int;
712
 
713
always  @(posedge clk or posedge wb_rst_i)
714
        if (wb_rst_i) thre_int_d <= #1 0;
715
        else thre_int_d <= #1 thre_int;
716
 
717
always  @(posedge clk or posedge wb_rst_i)
718
        if (wb_rst_i) ms_int_d <= #1 0;
719
        else ms_int_d <= #1 ms_int;
720
 
721
always  @(posedge clk or posedge wb_rst_i)
722
        if (wb_rst_i) ti_int_d <= #1 0;
723
        else ti_int_d <= #1 ti_int;
724
 
725
// rise detection signals
726
 
727
wire     rls_int_rise;
728
wire     thre_int_rise;
729
wire     ms_int_rise;
730
wire     ti_int_rise;
731
wire     rda_int_rise;
732
 
733
assign rda_int_rise    = rda_int & ~rda_int_d;
734
assign rls_int_rise       = rls_int & ~rls_int_d;
735
assign thre_int_rise   = thre_int & ~thre_int_d;
736
assign ms_int_rise        = ms_int & ~ms_int_d;
737
assign ti_int_rise        = ti_int & ~ti_int_d;
738
 
739
// interrupt pending flags
740
reg     rls_int_pnd;
741
reg     rda_int_pnd;
742
reg     thre_int_pnd;
743
reg     ms_int_pnd;
744
reg     ti_int_pnd;
745
 
746
// interrupt pending flags assignments
747
always  @(posedge clk or posedge wb_rst_i)
748
        if (wb_rst_i) rls_int_pnd <= #1 0;
749
        else
750
                rls_int_pnd <= #1 lsr_mask ? 0 :                                                 // reset condition
751
                                                        rls_int_rise ? 1 :                                              // latch condition
752
                                                        rls_int_pnd && ier[`UART_IE_RLS];       // default operation: remove if masked
753
 
754
always  @(posedge clk or posedge wb_rst_i)
755
        if (wb_rst_i) rda_int_pnd <= #1 0;
756
        else
757
                rda_int_pnd <= #1 ((rf_count == {1'b0,trigger_level}) && fifo_read) ? 0 :        // reset condition
758
                                                        rda_int_rise ? 1 :                                              // latch condition
759
                                                        rda_int_pnd && ier[`UART_IE_RDA];       // default operation: remove if masked
760
 
761
always  @(posedge clk or posedge wb_rst_i)
762
        if (wb_rst_i) thre_int_pnd <= #1 0;
763
        else
764
                thre_int_pnd <= #1 fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 0 :
765
                                                        thre_int_rise ? 1 :
766
                                                        thre_int_pnd && ier[`UART_IE_THRE];
767
 
768
always  @(posedge clk or posedge wb_rst_i)
769
        if (wb_rst_i) ms_int_pnd <= #1 0;
770
        else
771
                ms_int_pnd <= #1 msr_read ? 0 :
772
                                                        ms_int_rise ? 1 :
773
                                                        ms_int_pnd && ier[`UART_IE_MS];
774
 
775
always  @(posedge clk or posedge wb_rst_i)
776
        if (wb_rst_i) ti_int_pnd <= #1 0;
777
        else
778
                ti_int_pnd <= #1 fifo_read ? 0 :
779
                                                        ti_int_rise ? 1 :
780
                                                        ti_int_pnd && ier[`UART_IE_RDA];
781
// end of pending flags
782
 
783
// INT_O logic
784
always @(posedge clk or posedge wb_rst_i)
785
begin
786
        if (wb_rst_i)
787
                int_o <= #1 1'b0;
788
        else
789
                int_o <= #1
790
                                        rls_int_pnd             ?       ~lsr_mask                                       :
791
                                        rda_int_pnd             ? 1                                                             :
792
                                        ti_int_pnd              ? ~fifo_read                                    :
793
                                        thre_int_pnd    ? !(fifo_write & iir_read) :
794
                                        ms_int_pnd              ? ~msr_read                                             :
795
                                        0;       // if no interrupt are pending
796
end
797
 
798
 
799
// Interrupt Identification register
800
always @(posedge clk or posedge wb_rst_i)
801
begin
802
        if (wb_rst_i)
803
                iir <= #1 1;
804
        else
805
        if (rls_int_pnd)  // interrupt is pending
806
        begin
807
                iir[`UART_II_II] <= #1 `UART_II_RLS;    // set identification register to correct value
808
                iir[`UART_II_IP] <= #1 1'b0;            // and clear the IIR bit 0 (interrupt pending)
809
        end else // the sequence of conditions determines priority of interrupt identification
810
        if (rda_int)
811
        begin
812
                iir[`UART_II_II] <= #1 `UART_II_RDA;
813
                iir[`UART_II_IP] <= #1 1'b0;
814
        end
815
        else if (ti_int_pnd)
816
        begin
817
                iir[`UART_II_II] <= #1 `UART_II_TI;
818
                iir[`UART_II_IP] <= #1 1'b0;
819
        end
820
        else if (thre_int_pnd)
821
        begin
822
                iir[`UART_II_II] <= #1 `UART_II_THRE;
823
                iir[`UART_II_IP] <= #1 1'b0;
824
        end
825
        else if (ms_int_pnd)
826
        begin
827
                iir[`UART_II_II] <= #1 `UART_II_MS;
828
                iir[`UART_II_IP] <= #1 1'b0;
829
        end else        // no interrupt is pending
830
        begin
831
                iir[`UART_II_II] <= #1 0;
832
                iir[`UART_II_IP] <= #1 1'b1;
833
        end
834
end
835
 
836
endmodule

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