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URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [sim/] [bin/] [orp_soc.do] - Blame information for rev 1777

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Line No. Rev Author Line
1 983 lampret
// Signalscan Version 6.7p1
2
 
3
 
4
define bookmarks \
5
    xess_top.i_xess_fpga.risc.or1200_cpu \
6
    xess_top.i_xess_fpga.risc \
7
 
8
define noactivityindicator
9
define analog waveform lines
10
define add variable default overlay off
11
define waveform window analogheight 1
12
define terminal automatic
13
define buttons control \
14
  1 opensimmulationfile \
15
  2 executedofile \
16
  3 designbrowser \
17
  4 waveform \
18
  5 source \
19
  6 breakpoints \
20
  7 definesourcessearchpath \
21
  8 exit \
22
  9 createbreakpoint \
23
  10 creategroup \
24
  11 createmarker \
25
  12 closesimmulationfile \
26
  13 renamesimmulationfile \
27
  14 replacesimulationfiledata \
28
  15 listopensimmulationfiles \
29
  16 savedofile
30
define buttons waveform \
31
  1 undo \
32
  2 cut \
33
  3 copy \
34
  4 paste \
35
  5 delete \
36
  6 zoomin \
37
  7 zoomout \
38
  8 zoomoutfull \
39
  9 expand \
40
  10 createmarker \
41
  11 designbrowser:1 \
42
  12 variableradixbinary \
43
  13 variableradixoctal \
44
  14 variableradixdecimal \
45
  15 variableradixhexadecimal \
46
  16 variableradixascii
47
define buttons designbrowser \
48
  1 undo \
49
  2 cut \
50
  3 copy \
51
  4 paste \
52
  5 delete \
53
  6 cdupscope \
54
  7 getallvariables \
55
  8 getdeepallvariables \
56
  9 addvariables \
57
  10 addvarsandclosewindow \
58
  11 closewindow \
59
  12 scopefiltermodule \
60
  13 scopefiltertask \
61
  14 scopefilterfunction \
62
  15 scopefilterblock \
63
  16 scopefilterprimitive
64
define buttons event \
65
  1 undo \
66
  2 cut \
67
  3 copy \
68
  4 paste \
69
  5 delete \
70
  6 move \
71
  7 closewindow \
72
  8 duplicate \
73
  9 defineasrisingedge \
74
  10 defineasfallingedge \
75
  11 defineasanyedge \
76
  12 variableradixbinary \
77
  13 variableradixoctal \
78
  14 variableradixdecimal \
79
  15 variableradixhexadecimal \
80
  16 variableradixascii
81
define buttons source \
82
  1 undo \
83
  2 cut \
84
  3 copy \
85
  4 paste \
86
  5 delete \
87
  6 createbreakpoint \
88
  7 creategroup \
89
  8 createmarker \
90
  9 createevent \
91
  10 createregisterpage \
92
  11 closewindow \
93
  12 opensimmulationfile \
94
  13 closesimmulationfile \
95
  14 renamesimmulationfile \
96
  15 replacesimulationfiledata \
97
  16 listopensimmulationfiles
98
define buttons register \
99
  1 undo \
100
  2 cut \
101
  3 copy \
102
  4 paste \
103
  5 delete \
104
  6 createregisterpage \
105
  7 closewindow \
106
  8 continuefor \
107
  9 continueuntil \
108
  10 continueforever \
109
  11 stop \
110
  12 previous \
111
  13 next \
112
  14 variableradixbinary \
113
  15 variableradixhexadecimal \
114
  16 variableradixascii
115
define show related transactions
116
define exit prompt
117
define event search direction forward
118
define variable nofullhierarchy
119
define variable nofilenames
120
define variable nofullpathfilenames
121
include bookmark with filenames
122
include scope history without filenames
123 1105 lampret
define waveform window listpane 10.92
124
define waveform window namepane 24.95
125 983 lampret
define multivalueindication
126
define pattern curpos dot
127
define pattern cursor1 dot
128
define pattern cursor2 dot
129
define pattern marker dot
130
define print designer root
131
define print border
132
define print color blackonwhite
133
define print command "/usr/ucb/lpr -P%P"
134
define print printer  lp
135
define print range visible
136
define print variable visible
137
define rise fall time low threshold percentage 10
138
define rise fall time high threshold percentage 90
139
define rise fall time low value 0
140
define rise fall time high value 3.3
141
define sendmail command "/usr/lib/sendmail"
142
define sequence time width 30.00
143
define snap
144
 
145
define source noprompt
146
define time units default
147
define userdefinedbussymbol
148
define user guide directory "/usr/local/designacc/signalscan-6.5s2/doc/html"
149
define waveform window grid off
150
define waveform window waveheight 14
151
define waveform window wavespace 6
152
define web browser command netscape
153
define zoom outfull on initial add off
154
add group \
155
    "risc.dwb" \
156 1087 lampret
      xess_top.i_xess_fpga.or1200_top.dwb_biu.aborted \
157
      xess_top.i_xess_fpga.or1200_top.dwb_biu.aborted_r \
158 983 lampret
      xess_top.i_xess_fpga.or1200_top.dwb_biu.biu_ack_o \
159
      xess_top.i_xess_fpga.or1200_top.dwb_biu.biu_adr_i[31:0]'h \
160
      xess_top.i_xess_fpga.or1200_top.dwb_biu.biu_cab_i \
161
      xess_top.i_xess_fpga.or1200_top.dwb_biu.biu_cyc_i \
162
      xess_top.i_xess_fpga.or1200_top.dwb_biu.biu_dat_i[31:0]'h \
163
      xess_top.i_xess_fpga.or1200_top.dwb_biu.biu_dat_o[31:0]'h \
164
      xess_top.i_xess_fpga.or1200_top.dwb_biu.biu_err_o \
165
      xess_top.i_xess_fpga.or1200_top.dwb_biu.biu_sel_i[3:0]'h \
166
      xess_top.i_xess_fpga.or1200_top.dwb_biu.biu_stb_i \
167
      xess_top.i_xess_fpga.or1200_top.dwb_biu.biu_we_i \
168
      xess_top.i_xess_fpga.or1200_top.dwb_biu.clk \
169
      xess_top.i_xess_fpga.or1200_top.dwb_biu.clmode[1:0]'h \
170
      xess_top.i_xess_fpga.or1200_top.dwb_biu.long_ack_o \
171
      xess_top.i_xess_fpga.or1200_top.dwb_biu.long_err_o \
172
      xess_top.i_xess_fpga.or1200_top.dwb_biu.rst \
173
      xess_top.i_xess_fpga.or1200_top.dwb_biu.valid_div[1:0]'h \
174 1105 lampret
      xess_top.i_xess_fpga.or1200_top.dwb_biu.burst_len[1:0]'h \
175
      xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_cti_o[2:0]'h \
176 983 lampret
      xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_ack_i \
177
      xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_adr_o[31:0]'h \
178
      xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_cab_o \
179
      xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_clk_i \
180
      xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_cyc_o \
181
      xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_dat_i[31:0]'h \
182
      xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_dat_o[31:0]'h \
183
      xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_err_i \
184
      xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_rst_i \
185
      xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_rty_i \
186
      xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_sel_o[3:0]'h \
187
      xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_stb_o \
188
      xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_we_o \
189
 
190
add group \
191
    "risc.except" \
192
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.abort_ex \
193
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.branch_taken \
194
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.clk \
195
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.datain[31:0]'h \
196
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.dcpu_ack_i \
197
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.dcpu_err_i \
198
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.delayed1_ex_dslot \
199
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.delayed2_ex_dslot \
200
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.delayed_iee[2:0]'h \
201
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.delayed_tee[2:0]'h \
202
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.du_dsr[13:0]'h \
203
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.eear[31:0]'h \
204
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.eear_we \
205
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.epcr[31:0]'h \
206
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.epcr_we \
207
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.esr[15:0]'h \
208
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.esr_we \
209
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.ex_dslot \
210
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.ex_exceptflags[2:0]'h \
211
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.ex_freeze \
212
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.ex_pc[31:0]'h \
213
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.ex_void \
214
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.except_flushpipe \
215
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.except_start \
216
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.except_started \
217
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.except_stop[12:0]'h \
218
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.except_trig[12:0]'h \
219
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.except_type[3:0]'h \
220
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.extend_flush \
221
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.extend_flush_last \
222
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.flushpipe \
223
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.genpc_freeze \
224
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.icpu_ack_i \
225
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.icpu_err_i \
226
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.id_exceptflags[2:0]'h \
227
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.id_freeze \
228
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.id_pc[31:0]'h \
229
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.if_pc[31:0]'h \
230
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.if_stall \
231
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.int_pending \
232
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.lr_sav[31:2]'h \
233
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.lsu_addr[31:0]'h \
234
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.pc_we \
235
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.rst \
236
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.sig_align \
237
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.sig_dbuserr \
238
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.sig_dmmufault \
239
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.sig_dtlbmiss \
240
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.sig_ibuserr \
241
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.sig_illegal \
242
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.sig_immufault \
243
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.sig_int \
244
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.sig_itlbmiss \
245
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.sig_range \
246
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.sig_syscall \
247
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.sig_tick \
248
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.sig_trap \
249
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.spr_dat_npc[31:0]'h \
250
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.spr_dat_ppc[31:0]'h \
251
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.sr[15:0]'h \
252
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.state[2:0]'h \
253
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.tick_pending \
254
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.wb_freeze \
255
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_except.wb_pc[31:0]'h \
256
 
257
add group \
258
    "risc.ctrl" \
259
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.alu_op[3:0]'h \
260
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.branch_addrofs[31:2]'h \
261
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.branch_op[2:0]'h \
262
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.branch_taken \
263
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.clk \
264
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.comp_op[3:0]'h \
265
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.ex_freeze \
266
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.ex_insn[31:0]'h \
267
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.ex_macrc_op \
268
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.ex_void \
269
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.except_illegal \
270
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.flushpipe \
271
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.force_dslot_fetch \
272
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.id_freeze \
273
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.id_insn[31:0]'h \
274
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.id_macrc_op \
275
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.id_void \
276
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.if_insn[31:0]'h \
277
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.imm_signextend \
278
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.lsu_addrofs[31:0]'h \
279
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.lsu_op[3:0]'h \
280
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.mac_op[1:0]'h \
281
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.multicycle[1:0]'h \
282
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.no_more_dslot \
283
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.pre_branch_op[2:0]'h \
284
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.rf_addra[4:0]'h \
285
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.rf_addrb[4:0]'h \
286
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.rf_addrw[4:0]'h \
287
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.rf_rda \
288
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.rf_rdb \
289
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.rfe \
290
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.rfwb_op[2:0]'h \
291
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.rst \
292
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.sel_a[1:0]'h \
293
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.sel_b[1:0]'h \
294
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.sel_imm \
295
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.shrot_op[1:0]'h \
296
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.sig_syscall \
297
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.sig_trap \
298
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.simm[31:0]'h \
299
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.spr_addrimm[15:0]'h \
300
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.wb_freeze \
301
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.wb_insn[31:0]'h \
302
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.wb_rfaddrw[4:0]'h \
303
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_ctrl.wbforw_valid \
304
 
305
add group \
306
    "risc.monitor" \
307
      or1200_monitor.iwb_progress_addr[31:0]'h \
308
      or1200_monitor.dwb_progress'h \
309
      or1200_monitor.fexe'h \
310
      or1200_monitor.fspr'h \
311
      or1200_monitor.insns'h \
312
      or1200_monitor.iwb_progress'h \
313
      or1200_monitor.r3'h \
314
      or1200_monitor.ref[23:0]'h \
315
 
316
add group \
317
    "risc.iwb" \
318 1087 lampret
      xess_top.i_xess_fpga.or1200_top.iwb_biu.aborted \
319
      xess_top.i_xess_fpga.or1200_top.iwb_biu.aborted_r \
320 983 lampret
      xess_top.i_xess_fpga.or1200_top.iwb_biu.biu_ack_o \
321
      xess_top.i_xess_fpga.or1200_top.iwb_biu.biu_adr_i[31:0]'h \
322
      xess_top.i_xess_fpga.or1200_top.iwb_biu.biu_cab_i \
323
      xess_top.i_xess_fpga.or1200_top.iwb_biu.biu_cyc_i \
324
      xess_top.i_xess_fpga.or1200_top.iwb_biu.biu_dat_i[31:0]'h \
325
      xess_top.i_xess_fpga.or1200_top.iwb_biu.biu_dat_o[31:0]'h \
326
      xess_top.i_xess_fpga.or1200_top.iwb_biu.biu_err_o \
327
      xess_top.i_xess_fpga.or1200_top.iwb_biu.biu_sel_i[3:0]'h \
328
      xess_top.i_xess_fpga.or1200_top.iwb_biu.biu_stb_i \
329
      xess_top.i_xess_fpga.or1200_top.iwb_biu.biu_we_i \
330 1105 lampret
      xess_top.i_xess_fpga.or1200_top.iwb_biu.burst_len[1:0]'h \
331 983 lampret
      xess_top.i_xess_fpga.or1200_top.iwb_biu.clk \
332
      xess_top.i_xess_fpga.or1200_top.iwb_biu.clmode[1:0]'h \
333
      xess_top.i_xess_fpga.or1200_top.iwb_biu.long_ack_o \
334
      xess_top.i_xess_fpga.or1200_top.iwb_biu.long_err_o \
335
      xess_top.i_xess_fpga.or1200_top.iwb_biu.rst \
336
      xess_top.i_xess_fpga.or1200_top.iwb_biu.valid_div[1:0]'h \
337 1105 lampret
      xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_bte_o[1:0]'h \
338 983 lampret
      xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_cab_o \
339
      xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_clk_i \
340 1105 lampret
      xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_cti_o[2:0]'h \
341 983 lampret
      xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_dat_i[31:0]'h \
342
      xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_dat_o[31:0]'h \
343
      xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_err_i \
344
      xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_rst_i \
345
      xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_rty_i \
346
      xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_sel_o[3:0]'h \
347
      xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_ack_i \
348
      xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_adr_o[31:0]'h \
349
      xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_stb_o \
350
      xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_cyc_o \
351
      xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_we_o \
352
 
353
add group \
354
    "risc.genpc" \
355
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.binsn_addr[31:2]'h \
356
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.branch_addrofs[31:2]'h \
357
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.branch_op[2:0]'h \
358
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.clk \
359
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.epcr[31:0]'h \
360
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.except_prefix \
361
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.except_start \
362
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.except_type[3:0]'h \
363
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.flag \
364
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.genpc_freeze \
365
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.genpc_refetch \
366
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.icpu_adr_i[31:0]'h \
367
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.icpu_adr_o[31:0]'h \
368
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.icpu_cycstb_o \
369
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.icpu_rty_i \
370
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.icpu_sel_o[3:0]'h \
371
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.icpu_tag_o[3:0]'h \
372
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.lr_restor[31:0]'h \
373
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.no_more_dslot \
374
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.pc[31:0]'h \
375
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.pcreg[31:2]'h \
376
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.rst \
377
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.spr_dat_i[31:0]'h \
378
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.spr_pc_we \
379
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_genpc.taken \
380
 
381
add group \
382
    "risc.ic_top" \
383
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.clk \
384
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.from_icram[31:0]'h \
385
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.ic_addr[31:0]'h \
386
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.ic_en \
387
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.ic_inv \
388
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icbiu_ack_i \
389
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icbiu_adr_o[31:0]'h \
390
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icbiu_cab_o \
391
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icbiu_cyc_o \
392
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icbiu_dat_i[31:0]'h \
393
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icbiu_dat_o[31:0]'h \
394
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icbiu_err_i \
395
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icbiu_sel_o[3:0]'h \
396
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icbiu_stb_o \
397
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icbiu_we_o \
398
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icfsm_biu_read \
399
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icfsm_burst \
400
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icfsm_first_hit_ack \
401
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icfsm_first_miss_ack \
402
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icfsm_first_miss_err \
403
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icfsm_tag_we \
404
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icimmu_adr_i[31:0]'h \
405
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icimmu_ci_i \
406
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icimmu_cycstb_i \
407
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icimmu_err_o \
408
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icimmu_rty_o \
409
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icimmu_tag_o[3:0]'h \
410
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icpu_ack_o \
411
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icpu_dat_o[31:0]'h \
412
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icpu_sel_i[3:0]'h \
413
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icpu_tag_i[3:0]'h \
414
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.icram_we[3:0]'h \
415
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.ictag_addr[11:4]'h \
416
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.ictag_en \
417
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.ictag_v \
418
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.ictag_we \
419
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.rst \
420
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.saved_addr[31:0]'h \
421
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.spr_cs \
422
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.spr_dat_i[31:0]'h \
423
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.spr_write \
424
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.tag[19:0]'h \
425
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.tag_v \
426
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.tagcomp_miss \
427
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.to_icram[31:0]'h \
428
 
429
add group \
430
    "risc.ic_fsm" \
431
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.biu_read \
432
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.biudata_error \
433
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.biudata_valid \
434
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.burst \
435
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.cache_inhibit \
436
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.clk \
437
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.cnt[2:0]'h \
438
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.first_hit_ack \
439
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.first_miss_ack \
440
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.first_miss_err \
441
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.hitmiss_eval \
442
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.ic_en \
443
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.icimmu_ci_i \
444
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.icimmu_cycstb_i \
445
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.icram_we[3:0]'h \
446
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.load \
447
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.rst \
448
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.saved_addr[31:0]'h \
449
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.saved_addr_r[31:0]'h \
450
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.start_addr[31:0]'h \
451
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.state[1:0]'h \
452
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.tag_we \
453
      xess_top.i_xess_fpga.or1200_top.or1200_ic_top.or1200_ic_fsm.tagcomp_miss \
454
 
455
add group \
456
    "risc.sprs" \
457
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.addrbase[31:0]'h \
458
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.addrofs[15:0]'h \
459
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.alu_op[3:0]'h \
460
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.branch_op[2:0]'h \
461
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.cfgr_sel \
462
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.clk \
463
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.dat_i[31:0]'h \
464
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.du_access \
465
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.du_addr[31:0]'h \
466
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.du_dat_cpu[31:0]'h \
467
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.du_dat_du[31:0]'h \
468
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.du_read \
469
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.du_write \
470
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.eear[31:0]'h \
471
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.eear_sel \
472
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.eear_we \
473
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.epcr[31:0]'h \
474
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.epcr_sel \
475
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.epcr_we \
476
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.esr[15:0]'h \
477
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.esr_sel \
478
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.esr_we \
479
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.except_started \
480
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.flag \
481
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.flag_we \
482
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.flagforw \
483
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.npc_sel \
484
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.pc_we \
485
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.ppc_sel \
486
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.read_spr \
487
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.rf_sel \
488
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.rst \
489
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.spr_addr[31:0]'h \
490
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.spr_cs[31:0]'h \
491
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.spr_dat_cfgr[31:0]'h \
492
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.spr_dat_dmmu[31:0]'h \
493
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.spr_dat_du[31:0]'h \
494
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.spr_dat_immu[31:0]'h \
495
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.spr_dat_mac[31:0]'h \
496
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.spr_dat_npc[31:0]'h \
497
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.spr_dat_o[31:0]'h \
498
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.spr_dat_pic[31:0]'h \
499
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.spr_dat_pm[31:0]'h \
500
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.spr_dat_ppc[31:0]'h \
501
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.spr_dat_rf[31:0]'h \
502
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.spr_dat_tt[31:0]'h \
503
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.spr_we \
504
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.sprs_op[3:0]'h \
505
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.sr[15:0]'h \
506
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.sr_sel \
507
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.sr_we \
508
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.sys_data[31:0]'h \
509
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.to_sr[15:0]'h \
510
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.to_wbmux[31:0]'h \
511
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.unqualified_cs[31:0]'h \
512
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_sprs.write_spr \
513
 
514
add group \
515
    "risc.immu_top" \
516
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.clk \
517
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.fault \
518
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.ic_en \
519
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.icimmu_adr_o[31:0]'h \
520
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.icimmu_ci_o \
521
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.icimmu_cycstb_o \
522
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.icimmu_err_i \
523
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.icimmu_rty_i \
524
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.icimmu_tag_i[3:0]'h \
525
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.icpu_adr_i[31:0]'h \
526
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.icpu_adr_o[31:0]'h \
527
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.icpu_cycstb_i \
528
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.icpu_err_o \
529
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.icpu_rty_o \
530
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.icpu_tag_o[3:0]'h \
531
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.icpu_vpn_r[31:13]'h \
532
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.immu_en \
533
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.itlb_ci \
534
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.itlb_dat_o[31:0]'h \
535
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.itlb_done \
536
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.itlb_en \
537
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.itlb_en_r \
538
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.itlb_hit \
539
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.itlb_ppn[31:13]'h \
540
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.dis_spr_access \
541
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.page_cross \
542
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.itlb_spr_access \
543
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.itlb_sxe \
544
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.itlb_uxe \
545
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.miss \
546
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.rst \
547
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.spr_addr[31:0]'h \
548
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.spr_cs \
549
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.spr_dat_i[31:0]'h \
550
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.spr_dat_o[31:0]'h \
551
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.spr_write \
552
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.supv \
553
 
554
add group \
555
    "risc.immu_tlb" \
556
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.ci \
557
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.clk \
558
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.hit \
559
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.ppn[31:13]'h \
560
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.rst \
561
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.spr_addr[31:0]'h \
562
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.spr_cs \
563
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.spr_dat_i[31:0]'h \
564
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.spr_dat_o[31:0]'h \
565
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.spr_write \
566
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.sxe \
567
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.tlb_en \
568
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.tlb_index[5:0]'h \
569
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.tlb_mr_en \
570
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.tlb_mr_ram_in[13:0]'h \
571
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.tlb_mr_ram_out[13:0]'h \
572
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.tlb_mr_we \
573
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.tlb_tr_en \
574
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.tlb_tr_ram_in[21:0]'h \
575
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.tlb_tr_ram_out[21:0]'h \
576
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.tlb_tr_we \
577
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.uxe \
578
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.v \
579
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.vaddr[31:0]'h \
580
      xess_top.i_xess_fpga.or1200_top.or1200_immu_top.or1200_immu_tlb.vpn[31:19]'h \
581
 
582
add group \
583
    "risc.mult" \
584
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.a[31:0]'h \
585
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.alu_op[3:0]'h \
586
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.b[31:0]'h \
587
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.clk \
588
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.ex_freeze \
589
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.id_macrc_op \
590
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.mac_op[1:0]'h \
591
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.mac_op_r1[1:0]'h \
592
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.mac_op_r2[1:0]'h \
593
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.mac_op_r3[1:0]'h \
594
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.mac_r[63:0]'h \
595
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.mac_stall_r \
596
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.macrc_op \
597
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.mul_prod[63:0]'h \
598
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.mul_prod_r[63:0]'h \
599
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.result[31:0]'h \
600
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.rst \
601
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.spr_addr[31:0]'h \
602
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.spr_cs \
603
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.spr_dat_i[31:0]'h \
604
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.spr_dat_o[31:0]'h \
605
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.spr_machi_we \
606
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.spr_maclo_we \
607
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.spr_write \
608
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.x[31:0]'h \
609
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_mult_mac.y[31:0]'h \
610
 
611
add group \
612
    "risc.rf" \
613
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.addra[4:0]'h \
614
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.addrb[4:0]'h \
615
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.addrw[4:0]'h \
616
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.clk \
617
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.dataa[31:0]'h \
618
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.dataa_saved[32:0]'h \
619
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.datab[31:0]'h \
620
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.datab_saved[32:0]'h \
621
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.dataw[31:0]'h \
622
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.flushpipe \
623
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.from_rfa[31:0]'h \
624
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.from_rfb[31:0]'h \
625
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.id_freeze \
626
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.rda \
627
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.rdb \
628
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.rf_addra[4:0]'h \
629
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.rf_addrw[4:0]'h \
630
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.rf_dataw[31:0]'h \
631
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.rf_ena \
632
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.rf_enb \
633
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.rf_we \
634
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.rf_we_allow \
635
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.rst \
636
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.spr_addr[31:0]'h \
637
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.spr_cs \
638
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.spr_dat_i[31:0]'h \
639
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.spr_dat_o[31:0]'h \
640
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.spr_valid \
641
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.spr_write \
642
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.supv \
643
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.wb_freeze \
644
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_rf.we \
645
 
646
add group \
647
    "risc.gmult" \
648
 
649
add group \
650
    "risc.amult" \
651
 
652
add group \
653
    "risc.if" \
654
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.addr_saved[31:0]'h \
655
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.clk \
656
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.except_ibuserr \
657
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.except_immufault \
658
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.except_itlbmiss \
659
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.flushpipe \
660
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.genpc_refetch \
661
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.icpu_ack_i \
662
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.icpu_adr_i[31:0]'h \
663
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.icpu_dat_i[31:0]'h \
664
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.icpu_err_i \
665
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.icpu_tag_i[3:0]'h \
666
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.if_freeze \
667
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.if_insn[31:0]'h \
668
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.if_pc[31:0]'h \
669
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.if_stall \
670
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.insn_saved[31:0]'h \
671
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.no_more_dslot \
672
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.rfe \
673
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.rst \
674
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_if.saved \
675
 
676
add group \
677
    "risc.freeze" \
678
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.abort_ex \
679
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.clk \
680
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.du_stall \
681
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.ex_freeze \
682
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.extend_flush \
683
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.flushpipe \
684
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.flushpipe_r \
685
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.force_dslot_fetch \
686
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.genpc_freeze \
687
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.icpu_ack_i \
688
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.icpu_err_i \
689
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.id_freeze \
690
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.if_freeze \
691
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.if_stall \
692
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.lsu_stall \
693
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.lsu_unstall \
694
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.mac_stall \
695
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.multicycle[1:0]'h \
696
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.multicycle_cnt[1:0]'h \
697
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.multicycle_freeze \
698
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.rst \
699
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_freeze.wb_freeze \
700
 
701
add group \
702
    flash_if \
703
      xess_top.i_xess_fpga.flash_top.a[20:0]'h \
704
      xess_top.i_xess_fpga.flash_top.a_oe \
705
      xess_top.i_xess_fpga.flash_top.adr[31:0]'h \
706
      xess_top.i_xess_fpga.flash_top.cen \
707
      xess_top.i_xess_fpga.flash_top.d[7:0]'h \
708
      xess_top.i_xess_fpga.flash_top.delay[1:0]'h \
709
      xess_top.i_xess_fpga.flash_top.fflash'h \
710
      xess_top.i_xess_fpga.flash_top.flash_rstn \
711
      xess_top.i_xess_fpga.flash_top.oen \
712
      xess_top.i_xess_fpga.flash_top.rdy \
713
      xess_top.i_xess_fpga.flash_top.wb_ack_o \
714
      xess_top.i_xess_fpga.flash_top.wb_adr_i[31:0]'h \
715
      xess_top.i_xess_fpga.flash_top.wb_clk_i \
716
      xess_top.i_xess_fpga.flash_top.wb_cyc_i \
717
      xess_top.i_xess_fpga.flash_top.wb_dat_i[31:0]'h \
718
      xess_top.i_xess_fpga.flash_top.wb_dat_o[31:0]'h \
719
      xess_top.i_xess_fpga.flash_top.wb_err \
720
      xess_top.i_xess_fpga.flash_top.wb_err_o \
721
      xess_top.i_xess_fpga.flash_top.wb_rst_i \
722
      xess_top.i_xess_fpga.flash_top.wb_sel_i[3:0]'h \
723
      xess_top.i_xess_fpga.flash_top.wb_stb_i \
724
      xess_top.i_xess_fpga.flash_top.wb_we_i \
725
      xess_top.i_xess_fpga.flash_top.wen \
726
 
727
add group \
728
    "risc.sb" \
729
      xess_top.i_xess_fpga.or1200_top.or1200_sb.clk \
730
      xess_top.i_xess_fpga.or1200_top.or1200_sb.dcsb_ack_o \
731
      xess_top.i_xess_fpga.or1200_top.or1200_sb.dcsb_adr_i[31:0]'h \
732
      xess_top.i_xess_fpga.or1200_top.or1200_sb.dcsb_cab_i \
733
      xess_top.i_xess_fpga.or1200_top.or1200_sb.dcsb_cyc_i \
734
      xess_top.i_xess_fpga.or1200_top.or1200_sb.dcsb_dat_i[31:0]'h \
735
      xess_top.i_xess_fpga.or1200_top.or1200_sb.dcsb_dat_o[31:0]'h \
736
      xess_top.i_xess_fpga.or1200_top.or1200_sb.dcsb_err_o \
737
      xess_top.i_xess_fpga.or1200_top.or1200_sb.dcsb_sel_i[3:0]'h \
738
      xess_top.i_xess_fpga.or1200_top.or1200_sb.dcsb_stb_i \
739
      xess_top.i_xess_fpga.or1200_top.or1200_sb.dcsb_we_i \
740
      xess_top.i_xess_fpga.or1200_top.or1200_sb.rst \
741
      xess_top.i_xess_fpga.or1200_top.or1200_sb.sbbiu_ack_i \
742
      xess_top.i_xess_fpga.or1200_top.or1200_sb.sbbiu_adr_o[31:0]'h \
743
      xess_top.i_xess_fpga.or1200_top.or1200_sb.sbbiu_cab_o \
744
      xess_top.i_xess_fpga.or1200_top.or1200_sb.sbbiu_cyc_o \
745
      xess_top.i_xess_fpga.or1200_top.or1200_sb.sbbiu_dat_i[31:0]'h \
746
      xess_top.i_xess_fpga.or1200_top.or1200_sb.sbbiu_dat_o[31:0]'h \
747
      xess_top.i_xess_fpga.or1200_top.or1200_sb.sbbiu_err_i \
748
      xess_top.i_xess_fpga.or1200_top.or1200_sb.sbbiu_sel_o[3:0]'h \
749
      xess_top.i_xess_fpga.or1200_top.or1200_sb.sbbiu_stb_o \
750
      xess_top.i_xess_fpga.or1200_top.or1200_sb.sbbiu_we_o \
751
 
752
add group \
753
    "risc.sb_fifo" \
754
 
755 1087 lampret
add group \
756
    "risc.lsu" \
757
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.addrbase[31:0]'h \
758
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.addrofs[31:0]'h \
759
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.dcpu_ack_i \
760
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.dcpu_adr_o[31:0]'h \
761
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.dcpu_cycstb_o \
762
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.dcpu_dat_i[31:0]'h \
763
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.dcpu_dat_o[31:0]'h \
764
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.dcpu_err_i \
765
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.dcpu_rty_i \
766
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.dcpu_sel_o[3:0]'h \
767
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.dcpu_tag_i[3:0]'h \
768
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.dcpu_tag_o[3:0]'h \
769
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.dcpu_we_o \
770
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.du_stall \
771
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.except_align \
772
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.except_dbuserr \
773
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.except_dmmufault \
774
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.except_dtlbmiss \
775
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.lsu_datain[31:0]'h \
776
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.lsu_dataout[31:0]'h \
777
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.lsu_op[3:0]'h \
778
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.lsu_stall \
779
      xess_top.i_xess_fpga.or1200_top.or1200_cpu.or1200_lsu.lsu_unstall \
780 983 lampret
 
781 1087 lampret
add group \
782
    sram_if \
783
      xess_top.i_xess_fpga.sram_top.adr[31:0]'h \
784
      xess_top.i_xess_fpga.sram_top.d_oe \
785
      xess_top.i_xess_fpga.sram_top.delay[1:0]'h \
786
      xess_top.i_xess_fpga.sram_top.fsram'h \
787
      xess_top.i_xess_fpga.sram_top.l0_wen \
788
      xess_top.i_xess_fpga.sram_top.l1_wen \
789
      xess_top.i_xess_fpga.sram_top.l_a[18:0]'h \
790
      xess_top.i_xess_fpga.sram_top.l_cen \
791
      xess_top.i_xess_fpga.sram_top.l_d_i[15:0]'h \
792
      xess_top.i_xess_fpga.sram_top.l_d_o[15:0]'h \
793
      xess_top.i_xess_fpga.sram_top.l_oen \
794
      xess_top.i_xess_fpga.sram_top.r0_wen \
795
      xess_top.i_xess_fpga.sram_top.r1_wen \
796
      xess_top.i_xess_fpga.sram_top.r_a[18:0]'h \
797
      xess_top.i_xess_fpga.sram_top.r_cen \
798
      xess_top.i_xess_fpga.sram_top.r_d_i[15:0]'h \
799
      xess_top.i_xess_fpga.sram_top.r_d_o[15:0]'h \
800
      xess_top.i_xess_fpga.sram_top.r_oen \
801
      xess_top.i_xess_fpga.sram_top.wb_ack_o \
802
      xess_top.i_xess_fpga.sram_top.wb_adr_i[31:0]'h \
803
      xess_top.i_xess_fpga.sram_top.wb_clk_i \
804
      xess_top.i_xess_fpga.sram_top.wb_cyc_i \
805
      xess_top.i_xess_fpga.sram_top.wb_dat_i[31:0]'h \
806
      xess_top.i_xess_fpga.sram_top.wb_dat_o[31:0]'h \
807
      xess_top.i_xess_fpga.sram_top.wb_err \
808
      xess_top.i_xess_fpga.sram_top.wb_err_o \
809
      xess_top.i_xess_fpga.sram_top.wb_rst_i \
810
      xess_top.i_xess_fpga.sram_top.wb_sel_i[3:0]'h \
811
      xess_top.i_xess_fpga.sram_top.wb_stb_i \
812
      xess_top.i_xess_fpga.sram_top.wb_we_i \
813
 
814
 
815 983 lampret
deselect all
816 1105 lampret
open window designbrowser 1 geometry 56 121 855 550
817 983 lampret
open window waveform 1 geometry 10 62 1016 709
818 1105 lampret
zoom at 1021653.388(0)ns 0.00016725 0.00000000

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