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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [sim/] [bin/] [run_rtl_regression] - Blame information for rev 1777

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#!/bin/csh -f
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set iter = 1;
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set failed = 0;
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set all_tests = 0;
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# List all test cases
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#set simpletests=(buserr-nocache immu-nocache dmmu-nocache basic-nocache mul-nocache-O2 syscall-nocache cbasic-nocache-O2 ints1-nocache ints2-nocache \
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#               buserr-icdc immu-icdc dmmu-icdc basic-icdc mul-icdc-O2 syscall-icdc cbasic-icdc-O2 ints1-icdc ints2-icdc)
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#set simpletests=(basic-nocache mul-nocache-O2 cbasic-nocache-O2 ints1-nocache ints2-nocache \
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#               basic-icdc mul-icdc-O2 cbasic-icdc-O2 ints1-icdc ints2-icdc)
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#set simpletests=(icm-icdc icm-nocache dhry-nocache-O2 dhry-icdc-O2 mmu-nocache mmu-icdc basic-icdc basic-nocache mul-nocache-O2 mul-icdc-O2 basic-ic basic-dc)
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#set simpletests=(crc32-icdc-O0 minimad dhry-nocache-O2 dhry-icdc-O2 mmu-nocache mmu-icdc basic-icdc basic-nocache mul-nocache-O2 mul-icdc-O2 basic-ic basic-dc)
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#set complextests=(buserr-ic immu-ic dmmu-ic basic-ic mul-ic-O2 syscall-ic cbasic-ic-O2 ints1-ic ints2-ic \
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#               buserr-dc immu-dc dmmu-dc basic-dc mul-dc-O2 syscall-dc cbasic-dc-O2 ints1-dc ints2-dc \
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#               mul-nocache-O0 cbasic-nocache-O0 \
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#               mul-icdc-O0 cbasic-icdc-O0 \
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#               mul-ic-O0 cbasic-ic-O0 \
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#               mul-dc-O0 cbasic-dc-O0)
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#set complextests=(except-nocache except-icdc cbasic-nocache-O2 cbasic-icdc-O0 tick-nocache tick-icdc \
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#               syscall-nocache syscall-icdc uart-nocache uart-icdc debug-nocache debug-dc )
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set simpletests=`cat ../bin/tests`
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set complextests=()
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set simpletimes=(500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 500 )
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set complextimes=(40 40 \
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                 400 140 \
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                  100 40 \
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                  40 40 \
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                  40 40 )
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set iterations=( \
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                "DBG_IF_MODEL+SRAM_GENERIC_REGISTERED+OR1200_CLMODE_1TO2" \
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                "DBG_IF_MODEL+OR1200_CLMODE_1TO2" \
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                "DBG_IF_MODEL+FLASH_GENERIC" \
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                "DBG_IF_MODEL" \
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                "DBG_IF_MODEL+FLASH_GENERIC+FLASH_GENERIC_REGISTERED" \
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                "DBG_IF_MODEL+FLASH_GENERIC+FLASH_GENERIC_REGISTERED+SRAM_GENERIC_REGISTERED" \
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                "DBG_IF_MODEL+FLASH_GENERIC+FLASH_GENERIC_REGISTERED+OR1200_CLMODE_1TO2" \
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                "DBG_IF_MODEL+FLASH_GENERIC+FLASH_GENERIC_REGISTERED+SRAM_GENERIC_REGISTERED+OR1200_CLMODE_1TO2" \
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                "DBG_IF_MODEL+SRAM_GENERIC_REGISTERED" \
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                "")
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# Process arguments
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if ($1 == "simple") then
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        set tests=(${simpletests})
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        set maxtimes=(${simpletimes})
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else
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        set tests=(${simpletests} ${complextests})
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        set maxtimes=(${simpletimes} ${complextimes})
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endif
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if ($1 == "single") then
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        set tests=(${simpletests} ${complextests})
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        set maxtimes=(${simpletimes} ${complextimes})
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        set tests=${tests[$2]}
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        set maxtimes=${maxtimes[$2]}
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endif
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if ($1 == "clean") then
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        rm -rf ../log/*
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        rm -rf ../out/wave/*
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        exit 0;
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else if ($1 == "sim") then
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        goto sim;
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endif
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# Print HW clock
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/sbin/hwclock
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# List all selected tests
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set i = 0;
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foreach test ($tests)
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        @ i += 1;
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        /bin/echo -n -e " Test ${i}: ${test}, $maxtimes[$i] ms\t"
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        if ((${i} % 2) == 0) then
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                /bin/echo -e ""
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        endif
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end
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/bin/echo -e ""
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set i = 1;
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while ($iterations[$i] != "")
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        /bin/echo -e " Iteration ${i}: ${iterations[$i]}\t"
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        @ i += 1;
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end
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# Prepare all .args files
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iteration:
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/bin/echo -e ""
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/bin/echo -e "<<<"
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/bin/echo -e "<<< Iteration ${iter}: ${iterations[$iter]}"
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/bin/echo -e "<<<"
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if (${iterations[$iter]} != "") then
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        ncprep +define+${iterations[$iter]} -f ../bin/nc.scr > ncprep.out
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else
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        ncprep -f ../bin/nc.scr > ncprep.out
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endif
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if (`tail -1 ncprep.out | grep Failed` != "") then
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  /bin/echo -e ""
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  cat ncprep.out
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  exit
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endif
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# Run NC-Verilog compiler
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/bin/echo -e ""
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/bin/echo -e "\t@@@"
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/bin/echo -e "\t@@@ Compiling sources"
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/bin/echo -e "\t@@@"
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ncvlog -NOCOPYRIGHT -f ncvlog.args > ncvlog.out
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if ($status != 0) then
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  /bin/echo -e "\t@@@ FAILED"
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  /bin/echo -e ""
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  cat ncvlog.out
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  exit
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else
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  /bin/echo -e "\t@@@ Passed"
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endif
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# Run the NC-Verilog elaborator (build the design hierarchy)
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/bin/echo -e ""
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/bin/echo -e "\t@@@"
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/bin/echo -e "\t@@@ Building design hierarchy (elaboration)"
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/bin/echo -e "\t@@@"
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ncelab -NOTIMINGCHECKS -NOCOPYRIGHT -f ncelab.args > ncelab.out
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if ($status != 0) then
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  /bin/echo -e "\t@@@ FAILED"
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  /bin/echo -e ""
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  cat ncelab.out
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  exit
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else
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  /bin/echo -e "\t@@@ Passed"
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endif
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# Run the NC-Verilog simulator (simulate the design)
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sim:
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set i = 0;
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foreach test ($tests)
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        @ i += 1;
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        /bin/echo -e ""
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        /bin/echo -e "\t###"
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        /bin/echo -e "\t### Running test ${i}: ${test}, $maxtimes[$i] ms"
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        /bin/echo -e "\t###"
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        /bin/echo -e "database -open waves -into ../out/wave/i${iter}-${test} -default" > sim.tcl
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        /bin/echo -e "probe -create -shm xess_top -all -variables -depth all" >> sim.tcl
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        /bin/echo -e "probe -create -shm or1200_monitor -all -variables -depth all" >> sim.tcl
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        /bin/echo -e "stop -create -time $maxtimes[$i]ms -relative" >> sim.tcl
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        /bin/echo -e "run" >> sim.tcl
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        /bin/echo -e "quit" >> sim.tcl
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        cp ../src/${test}.hex ../src/flash.in
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        ncsim -NOCOPYRIGHT -f ncsim.args > ncsim.out
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        if ($status != 0) then
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          cat ncsim.out
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          exit
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        else
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          set magic=`grep report general.log | tail -1 | cut -d'(' -f2 | cut -d')' -f1 | cut -d' ' -f1`
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          set magictime=`tail -1 general.log | cut -d'n' -f1`
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          if ($magic == "deaddead") then
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                /bin/echo -e "\t### Passed (@time $magictime)"
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                @ all_tests += 1;
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          else
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                /bin/echo -e "\t### FAILED (@time $magictime, magic# 0x$magic)"
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                /bin/echo ../log/i${iter}-${test}-general.log:
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                cat general.log
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                @ failed += 1;
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                @ all_tests += 1;
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          endif
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          mv flash.log ../log/i${iter}-${test}-flash.log
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          mv executed.log ../log/i${iter}-${test}-executed.log
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          mv sram.log ../log/i${iter}-${test}-sram.log
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          mv sprs.log ../log/i${iter}-${test}-sprs.log
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          mv general.log ../log/i${iter}-${test}-general.log
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          mv lookup.log ../log/i${iter}-${test}-lookup.log
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        endif
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end
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@ iter += 1;
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if ($iterations[$iter] != "") then
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        goto iteration
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else
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        /bin/echo -e ""
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        /bin/echo -e "<<<"
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        /bin/echo -e "<<< End of Regression Iterations"
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        /bin/echo -e "<<<"
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        /bin/echo -e "<<< Failed $failed out of $all_tests"
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        /bin/echo -e "<<<"
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endif

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