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lampret |
// Signalscan Version 6.7p1
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define bookmarks \
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xess_top.i_xess_fpga.risc.or1200_cpu \
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xess_top.i_xess_fpga.risc \
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define noactivityindicator
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define analog waveform lines
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define add variable default overlay off
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define waveform window analogheight 1
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define terminal automatic
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define buttons control \
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1 opensimmulationfile \
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2 executedofile \
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3 designbrowser \
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4 waveform \
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5 source \
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6 breakpoints \
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7 definesourcessearchpath \
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8 exit \
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9 createbreakpoint \
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10 creategroup \
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11 createmarker \
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12 closesimmulationfile \
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13 renamesimmulationfile \
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14 replacesimulationfiledata \
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15 listopensimmulationfiles \
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16 savedofile
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define buttons waveform \
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1 undo \
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2 cut \
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3 copy \
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4 paste \
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5 delete \
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6 zoomin \
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7 zoomout \
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8 zoomoutfull \
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9 expand \
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10 createmarker \
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11 designbrowser:1 \
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12 variableradixbinary \
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13 variableradixoctal \
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14 variableradixdecimal \
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15 variableradixhexadecimal \
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16 variableradixascii
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define buttons designbrowser \
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1 undo \
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2 cut \
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3 copy \
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4 paste \
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5 delete \
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6 cdupscope \
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7 getallvariables \
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8 getdeepallvariables \
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9 addvariables \
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10 addvarsandclosewindow \
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11 closewindow \
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12 scopefiltermodule \
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13 scopefiltertask \
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14 scopefilterfunction \
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15 scopefilterblock \
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16 scopefilterprimitive
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define buttons event \
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1 undo \
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2 cut \
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3 copy \
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4 paste \
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5 delete \
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6 move \
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7 closewindow \
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8 duplicate \
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9 defineasrisingedge \
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10 defineasfallingedge \
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11 defineasanyedge \
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12 variableradixbinary \
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13 variableradixoctal \
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14 variableradixdecimal \
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15 variableradixhexadecimal \
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16 variableradixascii
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define buttons source \
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1 undo \
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2 cut \
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3 copy \
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4 paste \
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5 delete \
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6 createbreakpoint \
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7 creategroup \
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8 createmarker \
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9 createevent \
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10 createregisterpage \
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11 closewindow \
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12 opensimmulationfile \
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13 closesimmulationfile \
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14 renamesimmulationfile \
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15 replacesimulationfiledata \
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16 listopensimmulationfiles
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define buttons register \
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1 undo \
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2 cut \
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3 copy \
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4 paste \
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5 delete \
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6 createregisterpage \
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7 closewindow \
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8 continuefor \
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9 continueuntil \
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10 continueforever \
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11 stop \
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12 previous \
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13 next \
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14 variableradixbinary \
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15 variableradixhexadecimal \
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16 variableradixascii
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define show related transactions
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define exit prompt
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define event search direction forward
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define variable nofullhierarchy
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define variable nofilenames
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define variable nofullpathfilenames
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include bookmark with filenames
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include scope history without filenames
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define waveform window listpane 8.92
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define waveform window namepane 28.56
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define multivalueindication
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define pattern curpos dot
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define pattern cursor1 dot
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define pattern cursor2 dot
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define pattern marker dot
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define print designer root
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define print border
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define print color blackonwhite
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define print command "/usr/ucb/lpr -P%P"
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define print printer lp
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define print range visible
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define print variable visible
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define rise fall time low threshold percentage 10
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define rise fall time high threshold percentage 90
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define rise fall time low value 0
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define rise fall time high value 3.3
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define sendmail command "/usr/lib/sendmail"
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define sequence time width 30.00
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define snap
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define source noprompt
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define time units default
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define userdefinedbussymbol
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define user guide directory "/usr/local/designacc/signalscan-6.5s2/doc/html"
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define waveform window grid off
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define waveform window waveheight 14
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define waveform window wavespace 6
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define web browser command netscape
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define zoom outfull on initial add off
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add group \
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iwb \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.biu_ack_o \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.biu_adr_i[31:0]'h \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.biu_cab_i \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.biu_cyc_i \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.biu_dat_i[31:0]'h \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.biu_dat_o[31:0]'h \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.biu_err_o \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.biu_sel_i[3:0]'h \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.biu_stb_i \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.biu_we_i \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.clk \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.clmode[1:0]'h \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.long_ack_o \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.long_err_o \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.rst \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.valid_div[1:0]'h \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_ack_i \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_adr_o[31:0]'h \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_cab_o \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_clk_i \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_cyc_o \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_dat_i[31:0]'h \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_dat_o[31:0]'h \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_err_i \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_rst_i \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_rty_i \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_sel_o[3:0]'h \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_stb_o \
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xess_top.i_xess_fpga.or1200_top.iwb_biu.wb_we_o \
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add group \
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ctrl \
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add group \
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except \
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add group \
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wb_master \
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add group \
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sprs \
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add group \
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du \
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add group \
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alu \
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add group \
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mul \
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add group \
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wbmux \
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add group \
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tcop \
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xess_top.i_xess_fpga.tc_top.i0_wb_ack_o \
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xess_top.i_xess_fpga.tc_top.i0_wb_adr_i[31:0]'h \
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xess_top.i_xess_fpga.tc_top.i0_wb_cab_i \
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xess_top.i_xess_fpga.tc_top.i0_wb_cyc_i \
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| 216 |
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xess_top.i_xess_fpga.tc_top.i0_wb_dat_i[31:0]'h \
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xess_top.i_xess_fpga.tc_top.i0_wb_dat_o[31:0]'h \
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xess_top.i_xess_fpga.tc_top.i0_wb_err_o \
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| 219 |
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xess_top.i_xess_fpga.tc_top.i0_wb_sel_i[3:0]'h \
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xess_top.i_xess_fpga.tc_top.i0_wb_stb_i \
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| 221 |
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xess_top.i_xess_fpga.tc_top.i0_wb_we_i \
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| 222 |
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xess_top.i_xess_fpga.tc_top.i1_wb_ack_o \
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| 223 |
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xess_top.i_xess_fpga.tc_top.i1_wb_adr_i[31:0]'h \
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| 224 |
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xess_top.i_xess_fpga.tc_top.i1_wb_cab_i \
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| 225 |
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xess_top.i_xess_fpga.tc_top.i1_wb_cyc_i \
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| 226 |
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xess_top.i_xess_fpga.tc_top.i1_wb_dat_i[31:0]'h \
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| 227 |
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xess_top.i_xess_fpga.tc_top.i1_wb_dat_o[31:0]'h \
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| 228 |
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xess_top.i_xess_fpga.tc_top.i1_wb_err_o \
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| 229 |
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xess_top.i_xess_fpga.tc_top.i1_wb_sel_i[3:0]'h \
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| 230 |
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xess_top.i_xess_fpga.tc_top.i1_wb_stb_i \
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| 231 |
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xess_top.i_xess_fpga.tc_top.i1_wb_we_i \
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| 232 |
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xess_top.i_xess_fpga.tc_top.i2_wb_ack_o \
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| 233 |
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xess_top.i_xess_fpga.tc_top.i2_wb_adr_i[31:0]'h \
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| 234 |
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xess_top.i_xess_fpga.tc_top.i2_wb_cab_i \
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| 235 |
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xess_top.i_xess_fpga.tc_top.i2_wb_cyc_i \
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| 236 |
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xess_top.i_xess_fpga.tc_top.i2_wb_dat_i[31:0]'h \
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| 237 |
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xess_top.i_xess_fpga.tc_top.i2_wb_dat_o[31:0]'h \
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| 238 |
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xess_top.i_xess_fpga.tc_top.i2_wb_err_o \
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| 239 |
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xess_top.i_xess_fpga.tc_top.i2_wb_sel_i[3:0]'h \
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| 240 |
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xess_top.i_xess_fpga.tc_top.i2_wb_stb_i \
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| 241 |
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xess_top.i_xess_fpga.tc_top.i2_wb_we_i \
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| 242 |
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xess_top.i_xess_fpga.tc_top.i3_wb_ack_o \
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| 243 |
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xess_top.i_xess_fpga.tc_top.i3_wb_adr_i[31:0]'h \
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| 244 |
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xess_top.i_xess_fpga.tc_top.i3_wb_cab_i \
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| 245 |
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xess_top.i_xess_fpga.tc_top.i3_wb_cyc_i \
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| 246 |
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xess_top.i_xess_fpga.tc_top.i3_wb_dat_i[31:0]'h \
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| 247 |
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xess_top.i_xess_fpga.tc_top.i3_wb_dat_o[31:0]'h \
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| 248 |
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xess_top.i_xess_fpga.tc_top.i3_wb_err_o \
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| 249 |
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xess_top.i_xess_fpga.tc_top.i3_wb_sel_i[3:0]'h \
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| 250 |
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xess_top.i_xess_fpga.tc_top.i3_wb_stb_i \
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| 251 |
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xess_top.i_xess_fpga.tc_top.i3_wb_we_i \
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| 252 |
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xess_top.i_xess_fpga.tc_top.i4_wb_ack_o \
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| 253 |
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xess_top.i_xess_fpga.tc_top.i4_wb_adr_i[31:0]'h \
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| 254 |
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xess_top.i_xess_fpga.tc_top.i4_wb_cab_i \
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| 255 |
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xess_top.i_xess_fpga.tc_top.i4_wb_cyc_i \
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| 256 |
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xess_top.i_xess_fpga.tc_top.i4_wb_dat_i[31:0]'h \
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| 257 |
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xess_top.i_xess_fpga.tc_top.i4_wb_dat_o[31:0]'h \
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| 258 |
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xess_top.i_xess_fpga.tc_top.i4_wb_err_o \
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| 259 |
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xess_top.i_xess_fpga.tc_top.i4_wb_sel_i[3:0]'h \
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| 260 |
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xess_top.i_xess_fpga.tc_top.i4_wb_stb_i \
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| 261 |
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xess_top.i_xess_fpga.tc_top.i4_wb_we_i \
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| 262 |
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xess_top.i_xess_fpga.tc_top.i5_wb_ack_o \
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| 263 |
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xess_top.i_xess_fpga.tc_top.i5_wb_adr_i[31:0]'h \
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| 264 |
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xess_top.i_xess_fpga.tc_top.i5_wb_cab_i \
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| 265 |
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xess_top.i_xess_fpga.tc_top.i5_wb_cyc_i \
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| 266 |
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xess_top.i_xess_fpga.tc_top.i5_wb_dat_i[31:0]'h \
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| 267 |
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xess_top.i_xess_fpga.tc_top.i5_wb_dat_o[31:0]'h \
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| 268 |
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xess_top.i_xess_fpga.tc_top.i5_wb_err_o \
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| 269 |
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xess_top.i_xess_fpga.tc_top.i5_wb_sel_i[3:0]'h \
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| 270 |
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xess_top.i_xess_fpga.tc_top.i5_wb_stb_i \
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| 271 |
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xess_top.i_xess_fpga.tc_top.i5_wb_we_i \
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| 272 |
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xess_top.i_xess_fpga.tc_top.i6_wb_ack_o \
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| 273 |
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xess_top.i_xess_fpga.tc_top.i6_wb_adr_i[31:0]'h \
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| 274 |
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xess_top.i_xess_fpga.tc_top.i6_wb_cab_i \
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| 275 |
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xess_top.i_xess_fpga.tc_top.i6_wb_cyc_i \
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| 276 |
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xess_top.i_xess_fpga.tc_top.i6_wb_dat_i[31:0]'h \
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| 277 |
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xess_top.i_xess_fpga.tc_top.i6_wb_dat_o[31:0]'h \
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| 278 |
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xess_top.i_xess_fpga.tc_top.i6_wb_err_o \
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| 279 |
|
|
xess_top.i_xess_fpga.tc_top.i6_wb_sel_i[3:0]'h \
|
| 280 |
|
|
xess_top.i_xess_fpga.tc_top.i6_wb_stb_i \
|
| 281 |
|
|
xess_top.i_xess_fpga.tc_top.i6_wb_we_i \
|
| 282 |
|
|
xess_top.i_xess_fpga.tc_top.i7_wb_ack_o \
|
| 283 |
|
|
xess_top.i_xess_fpga.tc_top.i7_wb_adr_i[31:0]'h \
|
| 284 |
|
|
xess_top.i_xess_fpga.tc_top.i7_wb_cab_i \
|
| 285 |
|
|
xess_top.i_xess_fpga.tc_top.i7_wb_cyc_i \
|
| 286 |
|
|
xess_top.i_xess_fpga.tc_top.i7_wb_dat_i[31:0]'h \
|
| 287 |
|
|
xess_top.i_xess_fpga.tc_top.i7_wb_dat_o[31:0]'h \
|
| 288 |
|
|
xess_top.i_xess_fpga.tc_top.i7_wb_err_o \
|
| 289 |
|
|
xess_top.i_xess_fpga.tc_top.i7_wb_sel_i[3:0]'h \
|
| 290 |
|
|
xess_top.i_xess_fpga.tc_top.i7_wb_stb_i \
|
| 291 |
|
|
xess_top.i_xess_fpga.tc_top.i7_wb_we_i \
|
| 292 |
|
|
xess_top.i_xess_fpga.tc_top.t0_wb_ack_i \
|
| 293 |
|
|
xess_top.i_xess_fpga.tc_top.t0_wb_adr_o[31:0]'h \
|
| 294 |
|
|
xess_top.i_xess_fpga.tc_top.t0_wb_cab_o \
|
| 295 |
|
|
xess_top.i_xess_fpga.tc_top.t0_wb_cyc_o \
|
| 296 |
|
|
xess_top.i_xess_fpga.tc_top.t0_wb_dat_i[31:0]'h \
|
| 297 |
|
|
xess_top.i_xess_fpga.tc_top.t0_wb_dat_o[31:0]'h \
|
| 298 |
|
|
xess_top.i_xess_fpga.tc_top.t0_wb_err_i \
|
| 299 |
|
|
xess_top.i_xess_fpga.tc_top.t0_wb_sel_o[3:0]'h \
|
| 300 |
|
|
xess_top.i_xess_fpga.tc_top.t0_wb_stb_o \
|
| 301 |
|
|
xess_top.i_xess_fpga.tc_top.t0_wb_we_o \
|
| 302 |
|
|
xess_top.i_xess_fpga.tc_top.t1_wb_ack_i \
|
| 303 |
|
|
xess_top.i_xess_fpga.tc_top.t1_wb_adr_o[31:0]'h \
|
| 304 |
|
|
xess_top.i_xess_fpga.tc_top.t1_wb_cab_o \
|
| 305 |
|
|
xess_top.i_xess_fpga.tc_top.t1_wb_cyc_o \
|
| 306 |
|
|
xess_top.i_xess_fpga.tc_top.t1_wb_dat_i[31:0]'h \
|
| 307 |
|
|
xess_top.i_xess_fpga.tc_top.t1_wb_dat_o[31:0]'h \
|
| 308 |
|
|
xess_top.i_xess_fpga.tc_top.t1_wb_err_i \
|
| 309 |
|
|
xess_top.i_xess_fpga.tc_top.t1_wb_sel_o[3:0]'h \
|
| 310 |
|
|
xess_top.i_xess_fpga.tc_top.t1_wb_stb_o \
|
| 311 |
|
|
xess_top.i_xess_fpga.tc_top.t1_wb_we_o \
|
| 312 |
|
|
xess_top.i_xess_fpga.tc_top.t2_wb_ack_i \
|
| 313 |
|
|
xess_top.i_xess_fpga.tc_top.t2_wb_adr_o[31:0]'h \
|
| 314 |
|
|
xess_top.i_xess_fpga.tc_top.t2_wb_cab_o \
|
| 315 |
|
|
xess_top.i_xess_fpga.tc_top.t2_wb_cyc_o \
|
| 316 |
|
|
xess_top.i_xess_fpga.tc_top.t2_wb_dat_i[31:0]'h \
|
| 317 |
|
|
xess_top.i_xess_fpga.tc_top.t2_wb_dat_o[31:0]'h \
|
| 318 |
|
|
xess_top.i_xess_fpga.tc_top.t2_wb_err_i \
|
| 319 |
|
|
xess_top.i_xess_fpga.tc_top.t2_wb_sel_o[3:0]'h \
|
| 320 |
|
|
xess_top.i_xess_fpga.tc_top.t2_wb_stb_o \
|
| 321 |
|
|
xess_top.i_xess_fpga.tc_top.t2_wb_we_o \
|
| 322 |
|
|
xess_top.i_xess_fpga.tc_top.t3_wb_ack_i \
|
| 323 |
|
|
xess_top.i_xess_fpga.tc_top.t3_wb_adr_o[31:0]'h \
|
| 324 |
|
|
xess_top.i_xess_fpga.tc_top.t3_wb_cab_o \
|
| 325 |
|
|
xess_top.i_xess_fpga.tc_top.t3_wb_cyc_o \
|
| 326 |
|
|
xess_top.i_xess_fpga.tc_top.t3_wb_dat_i[31:0]'h \
|
| 327 |
|
|
xess_top.i_xess_fpga.tc_top.t3_wb_dat_o[31:0]'h \
|
| 328 |
|
|
xess_top.i_xess_fpga.tc_top.t3_wb_err_i \
|
| 329 |
|
|
xess_top.i_xess_fpga.tc_top.t3_wb_sel_o[3:0]'h \
|
| 330 |
|
|
xess_top.i_xess_fpga.tc_top.t3_wb_stb_o \
|
| 331 |
|
|
xess_top.i_xess_fpga.tc_top.t3_wb_we_o \
|
| 332 |
|
|
xess_top.i_xess_fpga.tc_top.t4_wb_ack_i \
|
| 333 |
|
|
xess_top.i_xess_fpga.tc_top.t4_wb_adr_o[31:0]'h \
|
| 334 |
|
|
xess_top.i_xess_fpga.tc_top.t4_wb_cab_o \
|
| 335 |
|
|
xess_top.i_xess_fpga.tc_top.t4_wb_cyc_o \
|
| 336 |
|
|
xess_top.i_xess_fpga.tc_top.t4_wb_dat_i[31:0]'h \
|
| 337 |
|
|
xess_top.i_xess_fpga.tc_top.t4_wb_dat_o[31:0]'h \
|
| 338 |
|
|
xess_top.i_xess_fpga.tc_top.t4_wb_err_i \
|
| 339 |
|
|
xess_top.i_xess_fpga.tc_top.t4_wb_sel_o[3:0]'h \
|
| 340 |
|
|
xess_top.i_xess_fpga.tc_top.t4_wb_stb_o \
|
| 341 |
|
|
xess_top.i_xess_fpga.tc_top.t4_wb_we_o \
|
| 342 |
|
|
xess_top.i_xess_fpga.tc_top.t5_wb_ack_i \
|
| 343 |
|
|
xess_top.i_xess_fpga.tc_top.t5_wb_adr_o[31:0]'h \
|
| 344 |
|
|
xess_top.i_xess_fpga.tc_top.t5_wb_cab_o \
|
| 345 |
|
|
xess_top.i_xess_fpga.tc_top.t5_wb_cyc_o \
|
| 346 |
|
|
xess_top.i_xess_fpga.tc_top.t5_wb_dat_i[31:0]'h \
|
| 347 |
|
|
xess_top.i_xess_fpga.tc_top.t5_wb_dat_o[31:0]'h \
|
| 348 |
|
|
xess_top.i_xess_fpga.tc_top.t5_wb_err_i \
|
| 349 |
|
|
xess_top.i_xess_fpga.tc_top.t5_wb_sel_o[3:0]'h \
|
| 350 |
|
|
xess_top.i_xess_fpga.tc_top.t5_wb_stb_o \
|
| 351 |
|
|
xess_top.i_xess_fpga.tc_top.t5_wb_we_o \
|
| 352 |
|
|
xess_top.i_xess_fpga.tc_top.t6_wb_ack_i \
|
| 353 |
|
|
xess_top.i_xess_fpga.tc_top.t6_wb_adr_o[31:0]'h \
|
| 354 |
|
|
xess_top.i_xess_fpga.tc_top.t6_wb_cab_o \
|
| 355 |
|
|
xess_top.i_xess_fpga.tc_top.t6_wb_cyc_o \
|
| 356 |
|
|
xess_top.i_xess_fpga.tc_top.t6_wb_dat_i[31:0]'h \
|
| 357 |
|
|
xess_top.i_xess_fpga.tc_top.t6_wb_dat_o[31:0]'h \
|
| 358 |
|
|
xess_top.i_xess_fpga.tc_top.t6_wb_err_i \
|
| 359 |
|
|
xess_top.i_xess_fpga.tc_top.t6_wb_sel_o[3:0]'h \
|
| 360 |
|
|
xess_top.i_xess_fpga.tc_top.t6_wb_stb_o \
|
| 361 |
|
|
xess_top.i_xess_fpga.tc_top.t6_wb_we_o \
|
| 362 |
|
|
xess_top.i_xess_fpga.tc_top.t7_wb_ack_i \
|
| 363 |
|
|
xess_top.i_xess_fpga.tc_top.t7_wb_adr_o[31:0]'h \
|
| 364 |
|
|
xess_top.i_xess_fpga.tc_top.t7_wb_cab_o \
|
| 365 |
|
|
xess_top.i_xess_fpga.tc_top.t7_wb_cyc_o \
|
| 366 |
|
|
xess_top.i_xess_fpga.tc_top.t7_wb_dat_i[31:0]'h \
|
| 367 |
|
|
xess_top.i_xess_fpga.tc_top.t7_wb_dat_o[31:0]'h \
|
| 368 |
|
|
xess_top.i_xess_fpga.tc_top.t7_wb_err_i \
|
| 369 |
|
|
xess_top.i_xess_fpga.tc_top.t7_wb_sel_o[3:0]'h \
|
| 370 |
|
|
xess_top.i_xess_fpga.tc_top.t7_wb_stb_o \
|
| 371 |
|
|
xess_top.i_xess_fpga.tc_top.t7_wb_we_o \
|
| 372 |
|
|
xess_top.i_xess_fpga.tc_top.t8_wb_ack_i \
|
| 373 |
|
|
xess_top.i_xess_fpga.tc_top.t8_wb_adr_o[31:0]'h \
|
| 374 |
|
|
xess_top.i_xess_fpga.tc_top.t8_wb_cab_o \
|
| 375 |
|
|
xess_top.i_xess_fpga.tc_top.t8_wb_cyc_o \
|
| 376 |
|
|
xess_top.i_xess_fpga.tc_top.t8_wb_dat_i[31:0]'h \
|
| 377 |
|
|
xess_top.i_xess_fpga.tc_top.t8_wb_dat_o[31:0]'h \
|
| 378 |
|
|
xess_top.i_xess_fpga.tc_top.t8_wb_err_i \
|
| 379 |
|
|
xess_top.i_xess_fpga.tc_top.t8_wb_sel_o[3:0]'h \
|
| 380 |
|
|
xess_top.i_xess_fpga.tc_top.t8_wb_stb_o \
|
| 381 |
|
|
xess_top.i_xess_fpga.tc_top.t8_wb_we_o \
|
| 382 |
|
|
xess_top.i_xess_fpga.tc_top.wb_clk_i \
|
| 383 |
|
|
xess_top.i_xess_fpga.tc_top.wb_rst_i \
|
| 384 |
|
|
xess_top.i_xess_fpga.tc_top.xi0_wb_ack_o \
|
| 385 |
|
|
xess_top.i_xess_fpga.tc_top.xi0_wb_dat_o[31:0]'h \
|
| 386 |
|
|
xess_top.i_xess_fpga.tc_top.xi0_wb_err_o \
|
| 387 |
|
|
xess_top.i_xess_fpga.tc_top.xi1_wb_ack_o \
|
| 388 |
|
|
xess_top.i_xess_fpga.tc_top.xi1_wb_dat_o[31:0]'h \
|
| 389 |
|
|
xess_top.i_xess_fpga.tc_top.xi1_wb_err_o \
|
| 390 |
|
|
xess_top.i_xess_fpga.tc_top.xi2_wb_ack_o \
|
| 391 |
|
|
xess_top.i_xess_fpga.tc_top.xi2_wb_dat_o[31:0]'h \
|
| 392 |
|
|
xess_top.i_xess_fpga.tc_top.xi2_wb_err_o \
|
| 393 |
|
|
xess_top.i_xess_fpga.tc_top.xi3_wb_ack_o \
|
| 394 |
|
|
xess_top.i_xess_fpga.tc_top.xi3_wb_dat_o[31:0]'h \
|
| 395 |
|
|
xess_top.i_xess_fpga.tc_top.xi3_wb_err_o \
|
| 396 |
|
|
xess_top.i_xess_fpga.tc_top.xi4_wb_ack_o \
|
| 397 |
|
|
xess_top.i_xess_fpga.tc_top.xi4_wb_dat_o[31:0]'h \
|
| 398 |
|
|
xess_top.i_xess_fpga.tc_top.xi4_wb_err_o \
|
| 399 |
|
|
xess_top.i_xess_fpga.tc_top.xi5_wb_ack_o \
|
| 400 |
|
|
xess_top.i_xess_fpga.tc_top.xi5_wb_dat_o[31:0]'h \
|
| 401 |
|
|
xess_top.i_xess_fpga.tc_top.xi5_wb_err_o \
|
| 402 |
|
|
xess_top.i_xess_fpga.tc_top.xi6_wb_ack_o \
|
| 403 |
|
|
xess_top.i_xess_fpga.tc_top.xi6_wb_dat_o[31:0]'h \
|
| 404 |
|
|
xess_top.i_xess_fpga.tc_top.xi6_wb_err_o \
|
| 405 |
|
|
xess_top.i_xess_fpga.tc_top.xi7_wb_ack_o \
|
| 406 |
|
|
xess_top.i_xess_fpga.tc_top.xi7_wb_dat_o[31:0]'h \
|
| 407 |
|
|
xess_top.i_xess_fpga.tc_top.xi7_wb_err_o \
|
| 408 |
|
|
xess_top.i_xess_fpga.tc_top.yi0_wb_ack_o \
|
| 409 |
|
|
xess_top.i_xess_fpga.tc_top.yi0_wb_dat_o[31:0]'h \
|
| 410 |
|
|
xess_top.i_xess_fpga.tc_top.yi0_wb_err_o \
|
| 411 |
|
|
xess_top.i_xess_fpga.tc_top.yi1_wb_ack_o \
|
| 412 |
|
|
xess_top.i_xess_fpga.tc_top.yi1_wb_dat_o[31:0]'h \
|
| 413 |
|
|
xess_top.i_xess_fpga.tc_top.yi1_wb_err_o \
|
| 414 |
|
|
xess_top.i_xess_fpga.tc_top.yi2_wb_ack_o \
|
| 415 |
|
|
xess_top.i_xess_fpga.tc_top.yi2_wb_dat_o[31:0]'h \
|
| 416 |
|
|
xess_top.i_xess_fpga.tc_top.yi2_wb_err_o \
|
| 417 |
|
|
xess_top.i_xess_fpga.tc_top.yi3_wb_ack_o \
|
| 418 |
|
|
xess_top.i_xess_fpga.tc_top.yi3_wb_dat_o[31:0]'h \
|
| 419 |
|
|
xess_top.i_xess_fpga.tc_top.yi3_wb_err_o \
|
| 420 |
|
|
xess_top.i_xess_fpga.tc_top.yi4_wb_ack_o \
|
| 421 |
|
|
xess_top.i_xess_fpga.tc_top.yi4_wb_dat_o[31:0]'h \
|
| 422 |
|
|
xess_top.i_xess_fpga.tc_top.yi4_wb_err_o \
|
| 423 |
|
|
xess_top.i_xess_fpga.tc_top.yi5_wb_ack_o \
|
| 424 |
|
|
xess_top.i_xess_fpga.tc_top.yi5_wb_dat_o[31:0]'h \
|
| 425 |
|
|
xess_top.i_xess_fpga.tc_top.yi5_wb_err_o \
|
| 426 |
|
|
xess_top.i_xess_fpga.tc_top.yi6_wb_ack_o \
|
| 427 |
|
|
xess_top.i_xess_fpga.tc_top.yi6_wb_dat_o[31:0]'h \
|
| 428 |
|
|
xess_top.i_xess_fpga.tc_top.yi6_wb_err_o \
|
| 429 |
|
|
xess_top.i_xess_fpga.tc_top.yi7_wb_ack_o \
|
| 430 |
|
|
xess_top.i_xess_fpga.tc_top.yi7_wb_dat_o[31:0]'h \
|
| 431 |
|
|
xess_top.i_xess_fpga.tc_top.yi7_wb_err_o \
|
| 432 |
|
|
xess_top.i_xess_fpga.tc_top.z_wb_ack_t \
|
| 433 |
|
|
xess_top.i_xess_fpga.tc_top.z_wb_adr_i[31:0]'h \
|
| 434 |
|
|
xess_top.i_xess_fpga.tc_top.z_wb_cab_i \
|
| 435 |
|
|
xess_top.i_xess_fpga.tc_top.z_wb_cyc_i \
|
| 436 |
|
|
xess_top.i_xess_fpga.tc_top.z_wb_dat_i[31:0]'h \
|
| 437 |
|
|
xess_top.i_xess_fpga.tc_top.z_wb_dat_t[31:0]'h \
|
| 438 |
|
|
xess_top.i_xess_fpga.tc_top.z_wb_err_t \
|
| 439 |
|
|
xess_top.i_xess_fpga.tc_top.z_wb_sel_i[3:0]'h \
|
| 440 |
|
|
xess_top.i_xess_fpga.tc_top.z_wb_stb_i \
|
| 441 |
|
|
xess_top.i_xess_fpga.tc_top.z_wb_we_i \
|
| 442 |
|
|
|
| 443 |
|
|
add group \
|
| 444 |
|
|
"tc_top.t0_ch" \
|
| 445 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i0_in[71:0]'h \
|
| 446 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i0_out[33:0]'h \
|
| 447 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i0_wb_ack_o \
|
| 448 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i0_wb_adr_i[31:0]'h \
|
| 449 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i0_wb_cab_i \
|
| 450 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i0_wb_cyc_i \
|
| 451 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i0_wb_dat_i[31:0]'h \
|
| 452 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i0_wb_dat_o[31:0]'h \
|
| 453 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i0_wb_err_o \
|
| 454 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i0_wb_sel_i[3:0]'h \
|
| 455 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i0_wb_stb_i \
|
| 456 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i0_wb_we_i \
|
| 457 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i1_in[71:0]'h \
|
| 458 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i1_out[33:0]'h \
|
| 459 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i1_wb_ack_o \
|
| 460 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i1_wb_adr_i[31:0]'h \
|
| 461 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i1_wb_cab_i \
|
| 462 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i1_wb_cyc_i \
|
| 463 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i1_wb_dat_i[31:0]'h \
|
| 464 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i1_wb_dat_o[31:0]'h \
|
| 465 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i1_wb_err_o \
|
| 466 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i1_wb_sel_i[3:0]'h \
|
| 467 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i1_wb_stb_i \
|
| 468 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i1_wb_we_i \
|
| 469 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i2_in[71:0]'h \
|
| 470 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i2_out[33:0]'h \
|
| 471 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i2_wb_ack_o \
|
| 472 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i2_wb_adr_i[31:0]'h \
|
| 473 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i2_wb_cab_i \
|
| 474 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i2_wb_cyc_i \
|
| 475 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i2_wb_dat_i[31:0]'h \
|
| 476 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i2_wb_dat_o[31:0]'h \
|
| 477 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i2_wb_err_o \
|
| 478 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i2_wb_sel_i[3:0]'h \
|
| 479 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i2_wb_stb_i \
|
| 480 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i2_wb_we_i \
|
| 481 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i3_in[71:0]'h \
|
| 482 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i3_out[33:0]'h \
|
| 483 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i3_wb_ack_o \
|
| 484 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i3_wb_adr_i[31:0]'h \
|
| 485 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i3_wb_cab_i \
|
| 486 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i3_wb_cyc_i \
|
| 487 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i3_wb_dat_i[31:0]'h \
|
| 488 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i3_wb_dat_o[31:0]'h \
|
| 489 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i3_wb_err_o \
|
| 490 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i3_wb_sel_i[3:0]'h \
|
| 491 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i3_wb_stb_i \
|
| 492 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i3_wb_we_i \
|
| 493 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i4_in[71:0]'h \
|
| 494 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i4_out[33:0]'h \
|
| 495 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i4_wb_ack_o \
|
| 496 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i4_wb_adr_i[31:0]'h \
|
| 497 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i4_wb_cab_i \
|
| 498 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i4_wb_cyc_i \
|
| 499 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i4_wb_dat_i[31:0]'h \
|
| 500 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i4_wb_dat_o[31:0]'h \
|
| 501 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i4_wb_err_o \
|
| 502 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i4_wb_sel_i[3:0]'h \
|
| 503 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i4_wb_stb_i \
|
| 504 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i4_wb_we_i \
|
| 505 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i5_in[71:0]'h \
|
| 506 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i5_out[33:0]'h \
|
| 507 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i5_wb_ack_o \
|
| 508 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i5_wb_adr_i[31:0]'h \
|
| 509 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i5_wb_cab_i \
|
| 510 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i5_wb_cyc_i \
|
| 511 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i5_wb_dat_i[31:0]'h \
|
| 512 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i5_wb_dat_o[31:0]'h \
|
| 513 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i5_wb_err_o \
|
| 514 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i5_wb_sel_i[3:0]'h \
|
| 515 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i5_wb_stb_i \
|
| 516 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i5_wb_we_i \
|
| 517 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i6_in[71:0]'h \
|
| 518 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i6_out[33:0]'h \
|
| 519 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i6_wb_ack_o \
|
| 520 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i6_wb_adr_i[31:0]'h \
|
| 521 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i6_wb_cab_i \
|
| 522 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i6_wb_cyc_i \
|
| 523 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i6_wb_dat_i[31:0]'h \
|
| 524 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i6_wb_dat_o[31:0]'h \
|
| 525 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i6_wb_err_o \
|
| 526 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i6_wb_sel_i[3:0]'h \
|
| 527 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i6_wb_stb_i \
|
| 528 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i6_wb_we_i \
|
| 529 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i7_in[71:0]'h \
|
| 530 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i7_out[33:0]'h \
|
| 531 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i7_wb_ack_o \
|
| 532 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i7_wb_adr_i[31:0]'h \
|
| 533 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i7_wb_cab_i \
|
| 534 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i7_wb_cyc_i \
|
| 535 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i7_wb_dat_i[31:0]'h \
|
| 536 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i7_wb_dat_o[31:0]'h \
|
| 537 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i7_wb_err_o \
|
| 538 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i7_wb_sel_i[3:0]'h \
|
| 539 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i7_wb_stb_i \
|
| 540 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.i7_wb_we_i \
|
| 541 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.req_cont \
|
| 542 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.req_i[7:0]'h \
|
| 543 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.req_r[2:0]'h \
|
| 544 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.req_won[2:0]'h \
|
| 545 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.t0_in[33:0]'h \
|
| 546 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.t0_out[71:0]'h \
|
| 547 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.t0_wb_ack_i \
|
| 548 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.t0_wb_adr_o[31:0]'h \
|
| 549 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.t0_wb_cab_o \
|
| 550 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.t0_wb_cyc_o \
|
| 551 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.t0_wb_dat_i[31:0]'h \
|
| 552 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.t0_wb_dat_o[31:0]'h \
|
| 553 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.t0_wb_err_i \
|
| 554 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.t0_wb_sel_o[3:0]'h \
|
| 555 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.t0_wb_stb_o \
|
| 556 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.t0_wb_we_o \
|
| 557 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.wb_clk_i \
|
| 558 |
|
|
xess_top.i_xess_fpga.tc_top.t0_ch.wb_rst_i \
|
| 559 |
|
|
|
| 560 |
|
|
add group \
|
| 561 |
|
|
"tc_top.t18_ch_upper" \
|
| 562 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i0_in[71:0]'h \
|
| 563 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i0_out[33:0]'h \
|
| 564 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i0_wb_ack_o \
|
| 565 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i0_wb_adr_i[31:0]'h \
|
| 566 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i0_wb_cab_i \
|
| 567 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i0_wb_cyc_i \
|
| 568 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i0_wb_dat_i[31:0]'h \
|
| 569 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i0_wb_dat_o[31:0]'h \
|
| 570 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i0_wb_err_o \
|
| 571 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i0_wb_sel_i[3:0]'h \
|
| 572 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i0_wb_stb_i \
|
| 573 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i0_wb_we_i \
|
| 574 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i1_in[71:0]'h \
|
| 575 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i1_out[33:0]'h \
|
| 576 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i1_wb_ack_o \
|
| 577 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i1_wb_adr_i[31:0]'h \
|
| 578 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i1_wb_cab_i \
|
| 579 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i1_wb_cyc_i \
|
| 580 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i1_wb_dat_i[31:0]'h \
|
| 581 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i1_wb_dat_o[31:0]'h \
|
| 582 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i1_wb_err_o \
|
| 583 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i1_wb_sel_i[3:0]'h \
|
| 584 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i1_wb_stb_i \
|
| 585 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i1_wb_we_i \
|
| 586 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i2_in[71:0]'h \
|
| 587 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i2_out[33:0]'h \
|
| 588 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i2_wb_ack_o \
|
| 589 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i2_wb_adr_i[31:0]'h \
|
| 590 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i2_wb_cab_i \
|
| 591 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i2_wb_cyc_i \
|
| 592 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i2_wb_dat_i[31:0]'h \
|
| 593 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i2_wb_dat_o[31:0]'h \
|
| 594 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i2_wb_err_o \
|
| 595 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i2_wb_sel_i[3:0]'h \
|
| 596 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i2_wb_stb_i \
|
| 597 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i2_wb_we_i \
|
| 598 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i3_in[71:0]'h \
|
| 599 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i3_out[33:0]'h \
|
| 600 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i3_wb_ack_o \
|
| 601 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i3_wb_adr_i[31:0]'h \
|
| 602 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i3_wb_cab_i \
|
| 603 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i3_wb_cyc_i \
|
| 604 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i3_wb_dat_i[31:0]'h \
|
| 605 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i3_wb_dat_o[31:0]'h \
|
| 606 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i3_wb_err_o \
|
| 607 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i3_wb_sel_i[3:0]'h \
|
| 608 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i3_wb_stb_i \
|
| 609 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i3_wb_we_i \
|
| 610 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i4_in[71:0]'h \
|
| 611 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i4_out[33:0]'h \
|
| 612 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i4_wb_ack_o \
|
| 613 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i4_wb_adr_i[31:0]'h \
|
| 614 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i4_wb_cab_i \
|
| 615 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i4_wb_cyc_i \
|
| 616 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i4_wb_dat_i[31:0]'h \
|
| 617 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i4_wb_dat_o[31:0]'h \
|
| 618 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i4_wb_err_o \
|
| 619 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i4_wb_sel_i[3:0]'h \
|
| 620 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i4_wb_stb_i \
|
| 621 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i4_wb_we_i \
|
| 622 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i5_in[71:0]'h \
|
| 623 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i5_out[33:0]'h \
|
| 624 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i5_wb_ack_o \
|
| 625 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i5_wb_adr_i[31:0]'h \
|
| 626 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i5_wb_cab_i \
|
| 627 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i5_wb_cyc_i \
|
| 628 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i5_wb_dat_i[31:0]'h \
|
| 629 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i5_wb_dat_o[31:0]'h \
|
| 630 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i5_wb_err_o \
|
| 631 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i5_wb_sel_i[3:0]'h \
|
| 632 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i5_wb_stb_i \
|
| 633 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i5_wb_we_i \
|
| 634 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i6_in[71:0]'h \
|
| 635 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i6_out[33:0]'h \
|
| 636 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i6_wb_ack_o \
|
| 637 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i6_wb_adr_i[31:0]'h \
|
| 638 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i6_wb_cab_i \
|
| 639 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i6_wb_cyc_i \
|
| 640 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i6_wb_dat_i[31:0]'h \
|
| 641 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i6_wb_dat_o[31:0]'h \
|
| 642 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i6_wb_err_o \
|
| 643 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i6_wb_sel_i[3:0]'h \
|
| 644 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i6_wb_stb_i \
|
| 645 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i6_wb_we_i \
|
| 646 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i7_in[71:0]'h \
|
| 647 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i7_out[33:0]'h \
|
| 648 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i7_wb_ack_o \
|
| 649 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i7_wb_adr_i[31:0]'h \
|
| 650 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i7_wb_cab_i \
|
| 651 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i7_wb_cyc_i \
|
| 652 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i7_wb_dat_i[31:0]'h \
|
| 653 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i7_wb_dat_o[31:0]'h \
|
| 654 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i7_wb_err_o \
|
| 655 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i7_wb_sel_i[3:0]'h \
|
| 656 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i7_wb_stb_i \
|
| 657 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.i7_wb_we_i \
|
| 658 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.req_cont \
|
| 659 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.req_i[7:0]'h \
|
| 660 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.req_r[2:0]'h \
|
| 661 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.req_won[2:0]'h \
|
| 662 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.t0_in[33:0]'h \
|
| 663 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.t0_out[71:0]'h \
|
| 664 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.t0_wb_ack_i \
|
| 665 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.t0_wb_adr_o[31:0]'h \
|
| 666 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.t0_wb_cab_o \
|
| 667 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.t0_wb_cyc_o \
|
| 668 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.t0_wb_dat_i[31:0]'h \
|
| 669 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.t0_wb_dat_o[31:0]'h \
|
| 670 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.t0_wb_err_i \
|
| 671 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.t0_wb_sel_o[3:0]'h \
|
| 672 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.t0_wb_stb_o \
|
| 673 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.t0_wb_we_o \
|
| 674 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.wb_clk_i \
|
| 675 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_upper.wb_rst_i \
|
| 676 |
|
|
|
| 677 |
|
|
add group \
|
| 678 |
|
|
"tc_top.t18_ch_lower" \
|
| 679 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.i0_in[71:0]'h \
|
| 680 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.i0_out[33:0]'h \
|
| 681 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.i0_wb_ack_o \
|
| 682 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.i0_wb_adr_i[31:0]'h \
|
| 683 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.i0_wb_cab_i \
|
| 684 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.i0_wb_cyc_i \
|
| 685 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.i0_wb_dat_i[31:0]'h \
|
| 686 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.i0_wb_dat_o[31:0]'h \
|
| 687 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.i0_wb_err_o \
|
| 688 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.i0_wb_sel_i[3:0]'h \
|
| 689 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.i0_wb_stb_i \
|
| 690 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.i0_wb_we_i \
|
| 691 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.req_t[7:0]'h \
|
| 692 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t0_in[33:0]'h \
|
| 693 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t0_out[71:0]'h \
|
| 694 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t0_wb_ack_i \
|
| 695 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t0_wb_adr_o[31:0]'h \
|
| 696 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t0_wb_cab_o \
|
| 697 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t0_wb_cyc_o \
|
| 698 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t0_wb_dat_i[31:0]'h \
|
| 699 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t0_wb_dat_o[31:0]'h \
|
| 700 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t0_wb_err_i \
|
| 701 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t0_wb_sel_o[3:0]'h \
|
| 702 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t0_wb_stb_o \
|
| 703 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t0_wb_we_o \
|
| 704 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t1_in[33:0]'h \
|
| 705 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t1_out[71:0]'h \
|
| 706 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t1_wb_ack_i \
|
| 707 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t1_wb_adr_o[31:0]'h \
|
| 708 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t1_wb_cab_o \
|
| 709 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t1_wb_cyc_o \
|
| 710 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t1_wb_dat_i[31:0]'h \
|
| 711 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t1_wb_dat_o[31:0]'h \
|
| 712 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t1_wb_err_i \
|
| 713 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t1_wb_sel_o[3:0]'h \
|
| 714 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t1_wb_stb_o \
|
| 715 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t1_wb_we_o \
|
| 716 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t2_in[33:0]'h \
|
| 717 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t2_out[71:0]'h \
|
| 718 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t2_wb_ack_i \
|
| 719 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t2_wb_adr_o[31:0]'h \
|
| 720 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t2_wb_cab_o \
|
| 721 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t2_wb_cyc_o \
|
| 722 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t2_wb_dat_i[31:0]'h \
|
| 723 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t2_wb_dat_o[31:0]'h \
|
| 724 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t2_wb_err_i \
|
| 725 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t2_wb_sel_o[3:0]'h \
|
| 726 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t2_wb_stb_o \
|
| 727 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t2_wb_we_o \
|
| 728 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t3_in[33:0]'h \
|
| 729 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t3_out[71:0]'h \
|
| 730 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t3_wb_ack_i \
|
| 731 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t3_wb_adr_o[31:0]'h \
|
| 732 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t3_wb_cab_o \
|
| 733 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t3_wb_cyc_o \
|
| 734 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t3_wb_dat_i[31:0]'h \
|
| 735 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t3_wb_dat_o[31:0]'h \
|
| 736 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t3_wb_err_i \
|
| 737 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t3_wb_sel_o[3:0]'h \
|
| 738 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t3_wb_stb_o \
|
| 739 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t3_wb_we_o \
|
| 740 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t4_in[33:0]'h \
|
| 741 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t4_out[71:0]'h \
|
| 742 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t4_wb_ack_i \
|
| 743 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t4_wb_adr_o[31:0]'h \
|
| 744 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t4_wb_cab_o \
|
| 745 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t4_wb_cyc_o \
|
| 746 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t4_wb_dat_i[31:0]'h \
|
| 747 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t4_wb_dat_o[31:0]'h \
|
| 748 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t4_wb_err_i \
|
| 749 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t4_wb_sel_o[3:0]'h \
|
| 750 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t4_wb_stb_o \
|
| 751 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t4_wb_we_o \
|
| 752 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t5_in[33:0]'h \
|
| 753 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t5_out[71:0]'h \
|
| 754 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t5_wb_ack_i \
|
| 755 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t5_wb_adr_o[31:0]'h \
|
| 756 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t5_wb_cab_o \
|
| 757 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t5_wb_cyc_o \
|
| 758 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t5_wb_dat_i[31:0]'h \
|
| 759 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t5_wb_dat_o[31:0]'h \
|
| 760 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t5_wb_err_i \
|
| 761 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t5_wb_sel_o[3:0]'h \
|
| 762 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t5_wb_stb_o \
|
| 763 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t5_wb_we_o \
|
| 764 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t6_in[33:0]'h \
|
| 765 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t6_out[71:0]'h \
|
| 766 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t6_wb_ack_i \
|
| 767 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t6_wb_adr_o[31:0]'h \
|
| 768 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t6_wb_cab_o \
|
| 769 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t6_wb_cyc_o \
|
| 770 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t6_wb_dat_i[31:0]'h \
|
| 771 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t6_wb_dat_o[31:0]'h \
|
| 772 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t6_wb_err_i \
|
| 773 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t6_wb_sel_o[3:0]'h \
|
| 774 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t6_wb_stb_o \
|
| 775 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t6_wb_we_o \
|
| 776 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t7_in[33:0]'h \
|
| 777 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t7_out[71:0]'h \
|
| 778 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t7_wb_ack_i \
|
| 779 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t7_wb_adr_o[31:0]'h \
|
| 780 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t7_wb_cab_o \
|
| 781 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t7_wb_cyc_o \
|
| 782 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t7_wb_dat_i[31:0]'h \
|
| 783 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t7_wb_dat_o[31:0]'h \
|
| 784 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t7_wb_err_i \
|
| 785 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t7_wb_sel_o[3:0]'h \
|
| 786 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t7_wb_stb_o \
|
| 787 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.t7_wb_we_o \
|
| 788 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.wb_clk_i \
|
| 789 |
|
|
xess_top.i_xess_fpga.tc_top.t18_ch_lower.wb_rst_i \
|
| 790 |
|
|
|
| 791 |
|
|
add group \
|
| 792 |
|
|
rf \
|
| 793 |
|
|
|
| 794 |
|
|
add group \
|
| 795 |
|
|
if \
|
| 796 |
|
|
|
| 797 |
|
|
add group \
|
| 798 |
|
|
freeze \
|
| 799 |
|
|
|
| 800 |
|
|
add group \
|
| 801 |
|
|
tt \
|
| 802 |
|
|
|
| 803 |
|
|
add group \
|
| 804 |
|
|
dwb \
|
| 805 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.biu_ack_o \
|
| 806 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.biu_adr_i[31:0]'h \
|
| 807 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.biu_cab_i \
|
| 808 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.biu_cyc_i \
|
| 809 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.biu_dat_i[31:0]'h \
|
| 810 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.biu_dat_o[31:0]'h \
|
| 811 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.biu_err_o \
|
| 812 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.biu_sel_i[3:0]'h \
|
| 813 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.biu_stb_i \
|
| 814 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.biu_we_i \
|
| 815 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.clk \
|
| 816 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.clmode[1:0]'h \
|
| 817 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.long_ack_o \
|
| 818 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.long_err_o \
|
| 819 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.rst \
|
| 820 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.valid_div[1:0]'h \
|
| 821 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_ack_i \
|
| 822 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_adr_o[31:0]'h \
|
| 823 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_cab_o \
|
| 824 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_clk_i \
|
| 825 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_cyc_o \
|
| 826 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_dat_i[31:0]'h \
|
| 827 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_dat_o[31:0]'h \
|
| 828 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_err_i \
|
| 829 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_rst_i \
|
| 830 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_rty_i \
|
| 831 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_sel_o[3:0]'h \
|
| 832 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_stb_o \
|
| 833 |
|
|
xess_top.i_xess_fpga.or1200_top.dwb_biu.wb_we_o \
|
| 834 |
|
|
|
| 835 |
|
|
add group \
|
| 836 |
|
|
fl \
|
| 837 |
|
|
xess_top.i_xess_fpga.flash_top.a[20:0]'h \
|
| 838 |
|
|
xess_top.i_xess_fpga.flash_top.a_oe \
|
| 839 |
|
|
xess_top.i_xess_fpga.flash_top.ack \
|
| 840 |
|
|
xess_top.i_xess_fpga.flash_top.cen \
|
| 841 |
|
|
xess_top.i_xess_fpga.flash_top.counter[4:0]'h \
|
| 842 |
|
|
xess_top.i_xess_fpga.flash_top.d[7:0]'h \
|
| 843 |
|
|
xess_top.i_xess_fpga.flash_top.fflash'h \
|
| 844 |
|
|
xess_top.i_xess_fpga.flash_top.flash_rstn \
|
| 845 |
|
|
xess_top.i_xess_fpga.flash_top.middle_tphqv[3:0]'h \
|
| 846 |
|
|
xess_top.i_xess_fpga.flash_top.oen \
|
| 847 |
|
|
xess_top.i_xess_fpga.flash_top.rdy \
|
| 848 |
|
|
xess_top.i_xess_fpga.flash_top.wb_ack_o \
|
| 849 |
|
|
xess_top.i_xess_fpga.flash_top.wb_adr_i[31:0]'h \
|
| 850 |
|
|
xess_top.i_xess_fpga.flash_top.wb_clk_i \
|
| 851 |
|
|
xess_top.i_xess_fpga.flash_top.wb_cyc_i \
|
| 852 |
|
|
xess_top.i_xess_fpga.flash_top.wb_dat_i[31:0]'h \
|
| 853 |
|
|
xess_top.i_xess_fpga.flash_top.wb_dat_o[31:0]'h \
|
| 854 |
|
|
xess_top.i_xess_fpga.flash_top.wb_err_o \
|
| 855 |
|
|
xess_top.i_xess_fpga.flash_top.wb_rst_i \
|
| 856 |
|
|
xess_top.i_xess_fpga.flash_top.wb_sel_i[3:0]'h \
|
| 857 |
|
|
xess_top.i_xess_fpga.flash_top.wb_stb_i \
|
| 858 |
|
|
xess_top.i_xess_fpga.flash_top.wb_we_i \
|
| 859 |
|
|
xess_top.i_xess_fpga.flash_top.wen \
|
| 860 |
|
|
|
| 861 |
|
|
add group \
|
| 862 |
|
|
sr \
|
| 863 |
|
|
xess_top.i_xess_fpga.sram_top.LatchedAddr[18:0]'h \
|
| 864 |
|
|
xess_top.i_xess_fpga.sram_top.Mux \
|
| 865 |
|
|
xess_top.i_xess_fpga.sram_top.ack_we \
|
| 866 |
|
|
xess_top.i_xess_fpga.sram_top.d_oe \
|
| 867 |
|
|
xess_top.i_xess_fpga.sram_top.fsram'h \
|
| 868 |
|
|
xess_top.i_xess_fpga.sram_top.l0_wen \
|
| 869 |
|
|
xess_top.i_xess_fpga.sram_top.l1_wen \
|
| 870 |
|
|
xess_top.i_xess_fpga.sram_top.l_a[18:0]'h \
|
| 871 |
|
|
xess_top.i_xess_fpga.sram_top.l_cen \
|
| 872 |
|
|
xess_top.i_xess_fpga.sram_top.l_d_i[15:0]'h \
|
| 873 |
|
|
xess_top.i_xess_fpga.sram_top.l_d_o[15:0]'h \
|
| 874 |
|
|
xess_top.i_xess_fpga.sram_top.l_data[15:0]'h \
|
| 875 |
|
|
xess_top.i_xess_fpga.sram_top.l_mux[15:0]'h \
|
| 876 |
|
|
xess_top.i_xess_fpga.sram_top.l_oe \
|
| 877 |
|
|
xess_top.i_xess_fpga.sram_top.l_oen \
|
| 878 |
|
|
xess_top.i_xess_fpga.sram_top.l_read[15:0]'h \
|
| 879 |
|
|
xess_top.i_xess_fpga.sram_top.latch_data[31:0]'h \
|
| 880 |
|
|
xess_top.i_xess_fpga.sram_top.r0_wen \
|
| 881 |
|
|
xess_top.i_xess_fpga.sram_top.r1_wen \
|
| 882 |
|
|
xess_top.i_xess_fpga.sram_top.r_a[18:0]'h \
|
| 883 |
|
|
xess_top.i_xess_fpga.sram_top.r_ack \
|
| 884 |
|
|
xess_top.i_xess_fpga.sram_top.r_cen \
|
| 885 |
|
|
xess_top.i_xess_fpga.sram_top.r_d_i[15:0]'h \
|
| 886 |
|
|
xess_top.i_xess_fpga.sram_top.r_d_o[15:0]'h \
|
| 887 |
|
|
xess_top.i_xess_fpga.sram_top.r_data[15:0]'h \
|
| 888 |
|
|
xess_top.i_xess_fpga.sram_top.r_mux[15:0]'h \
|
| 889 |
|
|
xess_top.i_xess_fpga.sram_top.r_oe \
|
| 890 |
|
|
xess_top.i_xess_fpga.sram_top.r_oen \
|
| 891 |
|
|
xess_top.i_xess_fpga.sram_top.r_read[15:0]'h \
|
| 892 |
|
|
xess_top.i_xess_fpga.sram_top.wb_ack_o \
|
| 893 |
|
|
xess_top.i_xess_fpga.sram_top.wb_adr_i[31:0]'h \
|
| 894 |
|
|
xess_top.i_xess_fpga.sram_top.wb_clk_i \
|
| 895 |
|
|
xess_top.i_xess_fpga.sram_top.wb_cyc_i \
|
| 896 |
|
|
xess_top.i_xess_fpga.sram_top.wb_dat_i[31:0]'h \
|
| 897 |
|
|
xess_top.i_xess_fpga.sram_top.wb_dat_o[31:0]'h \
|
| 898 |
|
|
xess_top.i_xess_fpga.sram_top.wb_err_o \
|
| 899 |
|
|
xess_top.i_xess_fpga.sram_top.wb_rst_i \
|
| 900 |
|
|
xess_top.i_xess_fpga.sram_top.wb_sel_i[3:0]'h \
|
| 901 |
|
|
xess_top.i_xess_fpga.sram_top.wb_stb_i \
|
| 902 |
|
|
xess_top.i_xess_fpga.sram_top.wb_we_i \
|
| 903 |
|
|
|
| 904 |
|
|
add group \
|
| 905 |
|
|
dmmu_tlb \
|
| 906 |
|
|
|
| 907 |
|
|
add group \
|
| 908 |
|
|
dmmu_top \
|
| 909 |
|
|
|
| 910 |
|
|
add group \
|
| 911 |
|
|
dc_top \
|
| 912 |
|
|
|
| 913 |
|
|
add group \
|
| 914 |
|
|
dc_fsm \
|
| 915 |
|
|
|
| 916 |
|
|
add group \
|
| 917 |
|
|
ic_top \
|
| 918 |
|
|
|
| 919 |
|
|
add group \
|
| 920 |
|
|
ic_fsm \
|
| 921 |
|
|
|
| 922 |
|
|
add group \
|
| 923 |
|
|
immu_tlb \
|
| 924 |
|
|
|
| 925 |
|
|
add group \
|
| 926 |
|
|
immu_top \
|
| 927 |
|
|
|
| 928 |
|
|
add group \
|
| 929 |
|
|
dbg_if_model \
|
| 930 |
|
|
|
| 931 |
|
|
add group \
|
| 932 |
|
|
genpc \
|
| 933 |
|
|
|
| 934 |
|
|
add group \
|
| 935 |
|
|
lsu \
|
| 936 |
|
|
|
| 937 |
|
|
add group \
|
| 938 |
|
|
mem2reg \
|
| 939 |
|
|
|
| 940 |
|
|
|
| 941 |
|
|
deselect all
|
| 942 |
|
|
open window designbrowser 1 geometry 56 117 855 550
|
| 943 |
|
|
open window waveform 1 geometry 10 62 1016 709
|
| 944 |
|
|
zoom at 5563903.368(0)ns 0.00018673 0.00000000
|
