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[/] [or1k/] [trunk/] [orp/] [orp_soc/] [sw/] [orp_mon/] [eth.c] - Blame information for rev 749

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Line No. Rev Author Line
1 748 lampret 
#include "board.h"
2 
#include "uart.h"
3 
#include "eth.h"
4 
#include "spr_defs.h"
5 
 
6 
extern void lolev_ie(void);
7 
extern void lolev_idis(void);
8 
 
9 
int tx_pointer_index = 0;
10 
unsigned long dest_mac_addr[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
11 
 
12 
unsigned long strtoul(char *s)
13 
{
14 
  int base = 10;
15 
  char *ptmp;
16 
  unsigned long val = 0;
17 
  unsigned long digit = 1;
18 
 
19 
  ptmp = s;
20 
  while (*ptmp != '\0')
21 
    if (*ptmp++ == 'x')
22 
      base = 16;
23 
 
24 
  while (ptmp-- != s)
25 
    if ((*ptmp >= '0') &&
26 
        (*ptmp <= '9'))
27 
    {
28 
        val += (*ptmp - '0') * digit;
29 
        digit *= base;
30 
    }
31 
    else
32 
    if ((*ptmp >= 'a') &&
33 
        (*ptmp <= 'f'))
34 
    {
35 
        val += (*ptmp - 'a' + 10) * digit;
36 
        digit *= base;
37 
    }
38 
 
39 
  return val;
40 
}
41 
 
42 
int strcmp (const char *s1, const char *s2)
43 
{
44 
 
45 
  while (*s1 != '\0' && *s1 == *s2)
46 
  {
47 
    s1++;
48 
    s2++;
49 
  }
50 
 
51 
  return (*(unsigned char *) s1) - (*(unsigned char *) s2);
52 
}
53 
 
54 
void eth_init(void)
55 
{
56 
  /* Reset ethernet core */
57 
  REG32(ETH_REG_BASE + ETH_MODER) = 0x0;              /* 0 */
58 
  REG32(ETH_REG_BASE + ETH_MODER) |= ETH_MODER_RST;   /* Reset ON */
59 
  REG32(ETH_REG_BASE + ETH_MODER) &= ~ETH_MODER_RST;  /* Reset OFF */
60 
 
61 
  /* Setting RX_BD base to 0x80 */
62 
  REG32(ETH_REG_BASE + ETH_RX_BD_NUM) = 0x00000080;
63 
 
64 
  /* RxEn, TxEn, Promisc, IFG, CRCEn */
65 
  REG32(ETH_REG_BASE + ETH_MODER) |= ETH_MODER_RXEN | ETH_MODER_TXEN | ETH_MODER_PRO | ETH_MODER_CRCEN | ETH_MODER_PAD;
66 
 
67 
  /* Set local MAC address */
68 
  REG32(ETH_REG_BASE + ETH_MAC_ADDR1) = ETH_MACADDR0 << 8 |
69 
                                        ETH_MACADDR1;
70 
  REG32(ETH_REG_BASE + ETH_MAC_ADDR0) = ETH_MACADDR2 << 24 |
71 
                                        ETH_MACADDR3 << 16 |
72 
                                        ETH_MACADDR4 << 8 |
73 
                                        ETH_MACADDR5;
74 
 
75 
  return;
76 
}
77 
 
78 
void init_tx_bd_pool(int max)
79 
{
80 
 
81 
  int cnt, i;
82 
 
83 
  for(i=0; i<=max; i++){
84 
 
85 
    /* Set Tx BD status */
86 
    REG32( ETH_BD_BASE + ((i*2) << 2) ) = ETH_TX_BD_PAD | ETH_TX_BD_CRC | ETH_RX_BD_IRQ;
87 
 
88 
    if(i==max)
89 
      REG32( ETH_BD_BASE + ((i*2) << 2) ) |= ETH_TX_BD_WRAP; // Last Tx BD - Wrap
90 
 
91 
    /* Initialize Tx BD pointer */
92 
    REG32( ETH_BD_BASE + ((1+i*2) << 2) ) = ETH_DATA_BASE + i * ETH_MAXBUF_LEN;
93 
  }
94 
}
95 
 
96 
 
97 
 
98 
void show_tx_bd(int start, int max)
99 
{
100 
 
101 
  int cnt, i;
102 
 
103 
  for(i=start; i<=max; i++){
104 
 
105 
    /* Read Tx BD */
106 
    uart_print_str("LEN:");
107 
    uart_print_short(REG32(ETH_BD_BASE + (i << 3)) >> 16);
108 
    uart_print_str(" RD:");
109 
    uart_print_short((REG32(ETH_BD_BASE + (i << 3)) >> 15) & 0x1);
110 
    uart_print_str(" IRQ:");
111 
    uart_print_short((REG32(ETH_BD_BASE + (i << 3)) >> 14) & 0x1);
112 
    uart_print_str(" WR:");
113 
    uart_print_short((REG32(ETH_BD_BASE + (i << 3)) >> 13) & 0x1);
114 
    uart_print_str(" PAD:");
115 
    uart_print_short((REG32(ETH_BD_BASE + (i << 3)) >> 12) & 0x1);
116 
    uart_print_str(" CRC:");
117 
    uart_print_short((REG32(ETH_BD_BASE + (i << 3)) >> 11) & 0x1);
118 
    uart_print_str(" UR:");
119 
    uart_print_short((REG32(ETH_BD_BASE + (i << 3)) >> 8) & 0x1);
120 
    uart_print_str(" RTRY:");
121 
    uart_print_short((REG32(ETH_BD_BASE + (i << 3)) >> 4) & 0xf);
122 
    uart_print_str(" RL:");
123 
    uart_print_short((REG32(ETH_BD_BASE + (i << 3)) >> 3) & 0x1);
124 
    uart_print_str(" LC:");
125 
    uart_print_short((REG32(ETH_BD_BASE + (i << 3)) >> 2) & 0x1);
126 
    uart_print_str(" DF:");
127 
    uart_print_short((REG32(ETH_BD_BASE + (i << 3)) >> 1) & 0x1);
128 
    uart_print_str(" CS:");
129 
    uart_print_short((REG32(ETH_BD_BASE + (i << 3)) >> 0) & 0x1);
130 
    uart_print_str("\nTx Buffer Pointer: ");
131 
    uart_print_long(REG32(ETH_BD_BASE + (i << 3) + 4));
132 
    uart_print_str("\n");
133 
  }
134 
}
135 
 
136 
 
137 
 
138 
 
139 
void show_rx_bd(int start, int max)
140 
{
141 
 
142 
  int cnt, i;
143 
 
144 
  unsigned long rx_bd_base, rx_bd_num;
145 
 
146 
  rx_bd_num =  REG32(ETH_REG_BASE + ETH_RX_BD_NUM);
147 
  rx_bd_base = ETH_BD_BASE + (rx_bd_num << 2);
148 
 
149 
  for(i=start; i<=max; i++){
150 
 
151 
    /* Read Rx BD */
152 
    uart_print_str("LEN:");
153 
    uart_print_short(REG32(rx_bd_base + (i << 3)) >> 16);
154 
    uart_print_str(" E:");
155 
    uart_print_short((REG32(rx_bd_base + (i << 3)) >> 15) & 0x1);
156 
    uart_print_str(" IRQ:");
157 
    uart_print_short((REG32(rx_bd_base + (i << 3)) >> 14) & 0x1);
158 
    uart_print_str(" WR:");
159 
    uart_print_short((REG32(rx_bd_base + (i << 3)) >> 13) & 0x1);
160 
    uart_print_str(" M:");
161 
    uart_print_short((REG32(rx_bd_base + (i << 3)) >> 7) & 0x1);
162 
    uart_print_str(" OR:");
163 
    uart_print_short((REG32(rx_bd_base + (i << 3)) >> 6) & 0x1);
164 
    uart_print_str(" IS:");
165 
    uart_print_short((REG32(rx_bd_base + (i << 3)) >> 5) & 0x1);
166 
    uart_print_str(" DN:");
167 
    uart_print_short((REG32(rx_bd_base + (i << 3)) >> 4) & 0x1);
168 
    uart_print_str(" TL:");
169 
    uart_print_short((REG32(rx_bd_base + (i << 3)) >> 3) & 0x1);
170 
    uart_print_str(" SF:");
171 
    uart_print_short((REG32(rx_bd_base + (i << 3)) >> 2) & 0x1);
172 
    uart_print_str(" CRC:");
173 
    uart_print_short((REG32(rx_bd_base + (i << 3)) >> 1) & 0x1);
174 
    uart_print_str(" LC:");
175 
    uart_print_short((REG32(rx_bd_base + (i << 3)) >> 0) & 0x1);
176 
    uart_print_str("\nRx Buffer Pointer: ");
177 
    uart_print_long(REG32(rx_bd_base + (i << 3) + 4));
178 
    uart_print_str("\n");
179 
  }
180 
}
181 
 
182 
void show_mem(int start, int stop)
183 
{
184 
 
185 
  unsigned long i;
186 
 
187 
  if (((i = start) & 0xf) != 0x0)
188 
    {
189 
      uart_print_str("\n");
190 
      uart_print_long(i);
191 
      uart_print_str(": ");
192 
    }
193 
  for(; i<=stop; i += 4){
194 
    if ((i & 0xf) == 0x0)
195 
    {
196 
      uart_print_str("\n");
197 
      uart_print_long(i);
198 
      uart_print_str(": ");
199 
    }
200 
 
201 
    /* Read one word */
202 
    uart_print_long(REG32(i));
203 
    uart_print_str(" ");
204 
  }
205 
  uart_print_str("\n");
206 
}
207 
 
208 
void ic_enable()
209 
{
210 
        unsigned long addr;
211 
        unsigned long sr;
212 
 
213 
        /* Invalidate IC */
214 
        for (addr = 0; addr < 8192; addr += 16)
215 
                asm("l.mtspr r0,%0,%1": : "r" (addr), "i" (SPR_ICBIR));
216 
 
217 
        /* Enable IC */
218 
        asm("l.mfspr %0,r0,%1": "=r" (sr) : "i" (SPR_SR));
219 
        sr |= SPR_SR_ICE;
220 
        asm("l.mtspr r0,%0,%1": : "r" (sr), "i" (SPR_SR));
221 
        asm("l.nop");
222 
        asm("l.nop");
223 
        asm("l.nop");
224 
        asm("l.nop");
225 
}
226 
 
227 
void ic_disable()
228 
{
229 
        unsigned long addr;
230 
        unsigned long sr;
231 
 
232 
  /* Disable IC */
233 
        asm("l.mfspr %0,r0,%1": "=r" (sr) : "i" (SPR_SR));
234 
        sr &= ~SPR_SR_ICE;
235 
        asm("l.mtspr r0,%0,%1": : "r" (sr), "i" (SPR_SR));
236 
        asm("l.nop");
237 
        asm("l.nop");
238 
        asm("l.nop");
239 
        asm("l.nop");
240 
}
241 
 
242 
 
243 
void dc_enable()
244 
{
245 
        unsigned long addr;
246 
        unsigned long sr;
247 
 
248 
        /* Invalidate DC */
249 
        for (addr = 0; addr < 8192; addr += 16)
250 
                asm("l.mtspr r0,%0,%1": : "r" (addr), "i" (SPR_DCBIR));
251 
 
252 
        /* Enable DC */
253 
        asm("l.mfspr %0,r0,%1": "=r" (sr) : "i" (SPR_SR));
254 
        sr |= SPR_SR_DCE;
255 
        asm("l.mtspr r0,%0,%1": : "r" (sr), "i" (SPR_SR));
256 
        asm("l.nop");
257 
        asm("l.nop");
258 
        asm("l.nop");
259 
        asm("l.nop");
260 
}
261 
 
262 
void dc_disable()
263 
{
264 
        unsigned long addr;
265 
        unsigned long sr;
266 
 
267 
  /* Disable DC */
268 
        asm("l.mfspr %0,r0,%1": "=r" (sr) : "i" (SPR_SR));
269 
        sr &= ~SPR_SR_DCE;
270 
        asm("l.mtspr r0,%0,%1": : "r" (sr), "i" (SPR_SR));
271 
        asm("l.nop");
272 
        asm("l.nop");
273 
        asm("l.nop");
274 
        asm("l.nop");
275 
}
276 
 
277 
void cmd_mfspr(unsigned long addr)
278 
{
279 
  unsigned long val;
280 
 
281 
  /* Read SPR */
282 
  asm("l.mfspr %0,%1,0": "=r" (val) : "r" (addr));
283 
 
284 
  uart_print_str("\nSPR ");
285 
  uart_print_short(addr);
286 
  uart_print_str(": ");
287 
  uart_print_long(val);
288 
}
289 
 
290 
void cmd_mtspr(unsigned long addr, unsigned long val)
291 
{
292 
 
293 
  /* Write SPR */
294 
  asm("l.mtspr %0,%1,0": : "r" (addr), "r" (val));
295 
  cmd_mfspr(addr);
296 
}
297 
 
298 
 
299 
void init_rx_bd_pool(int max)
300 
{
301 
 
302 
  int cnt, i;
303 
  unsigned long rx_bd_base, rx_bd_num;
304 
 
305 
  rx_bd_num =  REG32(ETH_REG_BASE + ETH_RX_BD_NUM);
306 
  rx_bd_base = ETH_BD_BASE + (rx_bd_num << 2);
307 
 
308 
  for(i=0; i<=max; i++){
309 
 
310 
    /* Initialize Rx BD pointer */
311 
    REG32( rx_bd_base + ((1+i*2) << 2) ) = ETH_DATA_BASE + (rx_bd_num + i) * ETH_MAXBUF_LEN;
312 
 
313 
     /* Set Rx BD status */
314 
    REG32( rx_bd_base + ((i*2) << 2) ) = ETH_RX_BD_IRQ;
315 
 
316 
    if(i==max)
317 
      REG32( rx_bd_base + ((i*2) << 2) ) |= ETH_RX_BD_WRAP; // Last Rx BD - Wrap
318 
 
319 
    REG32( rx_bd_base + ((i*2) << 2) ) |= ETH_RX_BD_EMPTY;  // Empty
320 
 
321 
  }
322 
}
323 
 
324 
 
325 
void show_buffer(unsigned long start_addr, unsigned long len)
326 
{
327 
  show_mem(start_addr, start_addr + len - 1);
328 
}
329 
 
330 
void show_rx_buffs(int max, int show_all)
331 
{
332 
 
333 
  int i;
334 
  unsigned long rx_bd_base, rx_bd_num;
335 
 
336 
  rx_bd_num =  REG32(ETH_REG_BASE + ETH_RX_BD_NUM);
337 
  rx_bd_base = ETH_BD_BASE + (rx_bd_num << 2);
338 
 
339 
  for(i=0; i<=max; i++)
340 
  {
341 
    if (!(REG32(rx_bd_base + (i << 3)) & ETH_RX_BD_EMPTY) || show_all)
342 
    {
343 
      uart_print_str("Rx BD No. ");
344 
      uart_print_short(i);
345 
      uart_print_str(" located at ");
346 
      uart_print_long(rx_bd_base + (i << 3));
347 
      uart_print_str("\n");
348 
      show_rx_bd(i, i);
349 
      show_buffer(REG32(rx_bd_base + (i << 3) + 4), REG32(rx_bd_base + (i << 3)) >> 16);
350 
      uart_print_str("\n");
351 
    }
352 
    if (REG32(rx_bd_base + (i << 3)) & ETH_RX_BD_WRAP)
353 
      return;
354 
  }
355 
}
356 
 
357 
 
358 
 
359 
void show_tx_buffs(int max)
360 
{
361 
 
362 
  int i;
363 
 
364 
  for(i=0; i<=max; i++)
365 
  {
366 
    if (1)
367 
    {
368 
      uart_print_str("Tx BD No. ");
369 
      uart_print_short(i);
370 
      uart_print_str(" located at ");
371 
      uart_print_long(ETH_BD_BASE + (i << 3));
372 
      uart_print_str("\n");
373 
      show_tx_bd(i, i);
374 
      show_buffer(REG32(ETH_BD_BASE + (i << 3) + 4), REG32(ETH_BD_BASE + (i << 3)) >> 16);
375 
      uart_print_str("\n");
376 
    }
377 
    if (REG32(ETH_BD_BASE + (i << 3)) & ETH_TX_BD_WRAP)
378 
      return;
379 
  }
380 
}
381 
 
382 
 
383 
 
384 
 
385 
void send_packet (unsigned long len, unsigned long start_data)
386 
{
387 
  unsigned long i, TxBD, data;
388 
 
389 
  /* Set dest & src address */
390 
  data = dest_mac_addr[0] << 24 |
391 
         dest_mac_addr[1] << 16 |
392 
         dest_mac_addr[2] << 8  |
393 
         dest_mac_addr[3] << 0;
394 
  REG32(ETH_DATA_BASE + 0 + ETH_MAXBUF_LEN * tx_pointer_index) = data;
395 
  data = dest_mac_addr[4] << 24 |
396 
         dest_mac_addr[5] << 16 |
397 
         ETH_MACADDR0     << 8  |
398 
         ETH_MACADDR1     << 0;
399 
  REG32(ETH_DATA_BASE + 4 + ETH_MAXBUF_LEN * tx_pointer_index) = data;
400 
  data = ETH_MACADDR2     << 24 |
401 
         ETH_MACADDR3     << 16 |
402 
         ETH_MACADDR4     << 8  |
403 
         ETH_MACADDR5     << 0;
404 
  REG32(ETH_DATA_BASE + 8 + ETH_MAXBUF_LEN * tx_pointer_index) = data;
405 
 
406 
  /* Write data to buffer */
407 
  for(i=12; i<len; i+=4){
408 
 
409 
    data = (i+start_data-12)<<24 | (i+start_data+1-12)<<16 |
410 
        (i+start_data+2-12)<<8 | (i+start_data+3-12);
411 
    REG32(ETH_DATA_BASE + i + ETH_MAXBUF_LEN * tx_pointer_index) = data;
412 
  }
413 
 
414 
  /* Set BD status */
415 
  TxBD = REG32(ETH_BD_BASE + (tx_pointer_index<<3)) & 0xffff;
416 
  REG32(ETH_BD_BASE + (tx_pointer_index<<3)) = (len<<16) | TxBD | ETH_TX_BD_READY;
417 
 
418 
  if(TxBD & ETH_TX_BD_WRAP)    // Wrap ?
419 
    tx_pointer_index = 0;
420 
  else
421 
    tx_pointer_index++;
422 
}
423 
 
424 
 
425 
void show_mac_regs (void)
426 
{
427 
 
428 
  uart_print_str("\n ");
429 
  uart_print_long(ETH_REG_BASE + ETH_MODER);
430 
  uart_print_str(" MODER: ");
431 
  uart_print_long(REG32(ETH_REG_BASE + ETH_MODER));
432 
 
433 
  uart_print_str("\n ");
434 
  uart_print_long(ETH_REG_BASE + ETH_INT);
435 
  uart_print_str(" INT: ");
436 
  uart_print_long(REG32(ETH_REG_BASE + ETH_INT));
437 
 
438 
  uart_print_str("\n ");
439 
  uart_print_long(ETH_REG_BASE + ETH_INT_MASK);
440 
  uart_print_str(" INT_MASK: ");
441 
  uart_print_long(REG32(ETH_REG_BASE + ETH_INT_MASK));
442 
 
443 
  uart_print_str("\n ");
444 
  uart_print_long(ETH_REG_BASE + ETH_IPGT);
445 
  uart_print_str(" IPGT: ");
446 
  uart_print_long(REG32(ETH_REG_BASE + ETH_IPGT));
447 
 
448 
  uart_print_str("\n ");
449 
  uart_print_long(ETH_REG_BASE + ETH_IPGR1);
450 
  uart_print_str(" IPGR1: ");
451 
  uart_print_long(REG32(ETH_REG_BASE + ETH_IPGR1));
452 
 
453 
  uart_print_str("\n ");
454 
  uart_print_long(ETH_REG_BASE + ETH_IPGR2);
455 
  uart_print_str(" IPGR2: ");
456 
  uart_print_long(REG32(ETH_REG_BASE + ETH_IPGR2));
457 
 
458 
  uart_print_str("\n ");
459 
  uart_print_long(ETH_REG_BASE + ETH_PACKETLEN);
460 
  uart_print_str(" PACKETLEN: ");
461 
  uart_print_long(REG32(ETH_REG_BASE + ETH_PACKETLEN));
462 
 
463 
  uart_print_str("\n ");
464 
  uart_print_long(ETH_REG_BASE + ETH_COLLCONF);
465 
  uart_print_str(" COLLCONF: ");
466 
  uart_print_long(REG32(ETH_REG_BASE + ETH_COLLCONF));
467 
 
468 
  uart_print_str("\n ");
469 
  uart_print_long(ETH_REG_BASE + ETH_RX_BD_NUM);
470 
  uart_print_str(" RX_BD_NUM: ");
471 
  uart_print_long(REG32(ETH_REG_BASE + ETH_RX_BD_NUM));
472 
 
473 
  uart_print_str("\n ");
474 
  uart_print_long(ETH_REG_BASE + ETH_CTRLMODER);
475 
  uart_print_str(" CTRLMODER: ");
476 
  uart_print_long(REG32(ETH_REG_BASE + ETH_CTRLMODER));
477 
 
478 
  uart_print_str("\n ");
479 
  uart_print_long(ETH_REG_BASE + ETH_MIIMODER);
480 
  uart_print_str(" MIIMODER: ");
481 
  uart_print_long(REG32(ETH_REG_BASE + ETH_MIIMODER));
482 
 
483 
  uart_print_str("\n ");
484 
  uart_print_long(ETH_REG_BASE + ETH_MIICOMMAND);
485 
  uart_print_str(" MIICOMMAND: ");
486 
  uart_print_long(REG32(ETH_REG_BASE + ETH_MIICOMMAND));
487 
 
488 
  uart_print_str("\n ");
489 
  uart_print_long(ETH_REG_BASE + ETH_MIIADDRESS);
490 
  uart_print_str(" MIIADDRESS: ");
491 
  uart_print_long(REG32(ETH_REG_BASE + ETH_MIIADDRESS));
492 
 
493 
  uart_print_str("\n ");
494 
  uart_print_long(ETH_REG_BASE + ETH_MIITX_DATA);
495 
  uart_print_str(" MIITX_DATA: ");
496 
  uart_print_long(REG32(ETH_REG_BASE + ETH_MIITX_DATA));
497 
 
498 
  uart_print_str("\n ");
499 
  uart_print_long(ETH_REG_BASE + ETH_MIIRX_DATA);
500 
  uart_print_str(" MIIRX_DATA: ");
501 
  uart_print_long(REG32(ETH_REG_BASE + ETH_MIIRX_DATA));
502 
 
503 
  uart_print_str("\n ");
504 
  uart_print_long(ETH_REG_BASE + ETH_MIISTATUS);
505 
  uart_print_str(" MIISTATUS: ");
506 
  uart_print_long(REG32(ETH_REG_BASE + ETH_MIISTATUS));
507 
 
508 
  uart_print_str("\n ");
509 
  uart_print_long(ETH_REG_BASE + ETH_MAC_ADDR0);
510 
  uart_print_str(" MAC_ADDR0: ");
511 
  uart_print_long(REG32(ETH_REG_BASE + ETH_MAC_ADDR0));
512 
 
513 
  uart_print_str("\n ");
514 
  uart_print_long(ETH_REG_BASE + ETH_MAC_ADDR1);
515 
  uart_print_str(" MAC_ADDR1: ");
516 
  uart_print_long(REG32(ETH_REG_BASE + ETH_MAC_ADDR1));
517 
 
518 
  uart_print_str("\n ");
519 
  uart_print_long(ETH_REG_BASE + ETH_HASH_ADDR0);
520 
  uart_print_str(" ETH_HASH_ADDR0: ");
521 
  uart_print_long(REG32(ETH_REG_BASE + ETH_HASH_ADDR0));
522 
 
523 
  uart_print_str("\n ");
524 
  uart_print_long(ETH_REG_BASE + ETH_HASH_ADDR1);
525 
  uart_print_str(" ETH_HASH_ADDR1: ");
526 
  uart_print_long(REG32(ETH_REG_BASE + ETH_HASH_ADDR1));
527 
 
528 
  uart_print_str("\n");
529 
}
530 
 
531 
 
532 
 
533 
void show_phy_reg (unsigned long start_addr, unsigned long stop_addr)
534 
{
535 
 
536 
  unsigned long addr;
537 
 
538 
  if (start_addr == stop_addr)
539 
  {
540 
    uart_print_str("\nSet MII RGAD ADDRESS to ");
541 
    uart_print_long(start_addr);
542 
    uart_print_str("\nMII Command = Read Status\n");
543 
  }
544 
 
545 
  for (addr = start_addr; addr <= stop_addr; addr++)
546 
  {
547 
    REG32(ETH_REG_BASE + ETH_MIIADDRESS) = addr<<8;
548 
    REG32(ETH_REG_BASE + ETH_MIICOMMAND) = ETH_MIICOMMAND_RSTAT;
549 
 
550 
    uart_print_str("\nMII RX_DATA: ");
551 
    uart_print_long(REG32(ETH_REG_BASE + ETH_MIIRX_DATA));
552 
 
553 
    uart_print_str("\n");
554 
  }
555 
}
556 
 
557 
void set_phy_reg (unsigned long addr, unsigned long val)
558 
{
559 
  uart_print_str("\nSet MII RGAD ADDRESS to ");
560 
  uart_print_long(addr);
561 
 
562 
  REG32(ETH_REG_BASE + ETH_MIIADDRESS) = addr<<8;
563 
 
564 
  uart_print_str("\nMII Command = Write Control Data\n");
565 
  REG32(ETH_REG_BASE + ETH_MIICOMMAND) = ETH_MIICOMMAND_WCTRLDATA;
566 
 
567 
  REG32(ETH_REG_BASE + ETH_MIITX_DATA) = val;
568 
 
569 
  show_phy_reg(addr, addr);
570 
}
571 
 
572 
void testram (unsigned long start_addr, unsigned long stop_addr, unsigned long testno)
573 
{
574 
  unsigned long addr;
575 
  unsigned long err_addr;
576 
  unsigned long err_no = 0;
577 
 
578 
  /* Test 1: Write locations with their addresses */
579 
  if ((testno == 1) || (testno == 0))
580 
  {
581 
    uart_print_str("\n1. Writing locations with their addresses: ");
582 
    for (addr = start_addr; addr <= stop_addr; addr += 4)
583 
      REG32(addr) = addr;
584 
 
585 
    /* Verify */
586 
    for (addr = start_addr; addr <= stop_addr; addr += 4)
587 
      if (REG32(addr) != addr)
588 
      {
589 
        err_no++;
590 
        err_addr = addr;
591 
      }
592 
    if (err_no)
593 
    {
594 
      uart_print_short(err_no);
595 
      uart_print_str(" times failed. Last at location ");
596 
      uart_print_long(err_addr);
597 
    } else
598 
      uart_print_str("Passed");
599 
    err_no = 0;
600 
  }
601 
 
602 
  /* Test 2: Write locations with their inverse address */
603 
  if ((testno == 2) || (testno == 0))
604 
  {
605 
    uart_print_str("\n2. Writing locations with their inverse addresses: ");
606 
    for (addr = start_addr; addr <= stop_addr; addr += 4)
607 
      REG32(addr) = ~addr;
608 
 
609 
    /* Verify */
610 
    for (addr = start_addr; addr <= stop_addr; addr += 4)
611 
      if (REG32(addr) != ~addr)
612 
      {
613 
        err_no++;
614 
        err_addr = addr;
615 
      }
616 
    if (err_no)
617 
    {
618 
      uart_print_short(err_no);
619 
      uart_print_str(" times failed. Last at location ");
620 
      uart_print_long(err_addr);
621 
    } else
622 
      uart_print_str("Passed");
623 
    err_no = 0;
624 
  }
625 
 
626 
  /* Test 3: Write locations with walking ones */
627 
  if ((testno == 3) || (testno == 0))
628 
  {
629 
    uart_print_str("\n3. Writing locations with walking ones: ");
630 
    for (addr = start_addr; addr <= stop_addr; addr += 4)
631 
      REG32(addr) = 1 << (addr >> 2);
632 
 
633 
    /* Verify */
634 
    for (addr = start_addr; addr <= stop_addr; addr += 4)
635 
      if (REG32(addr) != (1 << (addr >> 2)))
636 
      {
637 
        err_no++;
638 
        err_addr = addr;
639 
      }
640 
    if (err_no)
641 
    {
642 
      uart_print_short(err_no);
643 
      uart_print_str(" times failed. Last at location ");
644 
      uart_print_long(err_addr);
645 
    } else
646 
      uart_print_str("Passed");
647 
    err_no = 0;
648 
  }
649 
 
650 
  /* Test 4: Write locations with walking zeros */
651 
  if ((testno == 4) || (testno == 0))
652 
  {
653 
    uart_print_str("\n4. Writing locations with walking zeros: ");
654 
    for (addr = start_addr; addr <= stop_addr; addr += 4)
655 
      REG32(addr) = ~(1 << (addr >> 2));
656 
 
657 
    /* Verify */
658 
    for (addr = start_addr; addr <= stop_addr; addr += 4)
659 
      if (REG32(addr) != ~(1 << (addr >> 2)))
660 
      {
661 
        err_no++;
662 
        err_addr = addr;
663 
      }
664 
    if (err_no)
665 
    {
666 
      uart_print_short(err_no);
667 
      uart_print_str(" times failed. Last at location ");
668 
      uart_print_long(err_addr);
669 
    } else
670 
      uart_print_str("Passed");
671 
    err_no = 0;
672 
  }
673 
}
674 
 
675 
void eth_int_enable(void)
676 
{
677 
  /* Enable exception recognition, external interrupts */
678 
  lolev_ie();
679 
 
680 
  /* Enabled IRQs: Tx buffer, Tx error, Rx buffer, Rx error, Rx BD busy */
681 
  REG32(ETH_REG_BASE + ETH_INT_MASK) |= ETH_INT_MASK_TXB | ETH_INT_MASK_TXE | ETH_INT_MASK_RXF | ETH_INT_MASK_RXE | ETH_INT_MASK_BUSY;
682 
}
683 
 
684 
void crt_enable();
685 
void crt_disable();
686 
void crt_test();
687 
void camera_enable();
688 
void camera_disable();
689 
 
690 
void mon_command()
691 
{
692 
  char c = '\0';
693 
  char str[1000];
694 
  char *pstr = str;
695 
  char cmd[100];
696 
  char *ptmp;
697 
  char sarg[100];
698 
  unsigned long iarg[5];
699 
  int args = 0;
700 
 
701 
  /* Show prompt */
702 
#ifdef XESS
703 
  uart_print_str("\norp-xsv> ");
704 
#else
705 
  uart_print_str("\nbender> ");
706 
#endif
707 
 
708 
  /* Get characters from UART */
709 
  c = uart_getc();
710 
  while (c != '\r' && c != '\f' && c != '\n')
711 
  {
712 
    if (c == '\b')
713 
      pstr--;
714 
    else
715 
      *pstr++ = c;
716 
    uart_putc(c);
717 
    c = uart_getc();
718 
  }
719 
  *pstr = '\0';
720 
  uart_print_str("\n");
721 
 
722 
  /* Get command from the string */
723 
  pstr = str;
724 
  ptmp = cmd;
725 
  while (*pstr != '\0' && *pstr != ' ')
726 
    *ptmp++ = *pstr++;
727 
  *ptmp = '\0';
728 
 
729 
  /* Go to first argument */
730 
  while (*pstr == ' ')
731 
    pstr++;
732 
 
733 
  /* Get argument 1 from the string */
734 
  ptmp = sarg;
735 
  if (*pstr)
736 
    args++;
737 
  while (*pstr != '\0' && *pstr != ' ')
738 
    *ptmp++ = *pstr++;
739 
  *ptmp = '\0';
740 
 
741 
  /* Change argument 1 to unsigned long */
742 
  if (sarg[0])
743 
    iarg[0] = strtoul(sarg);
744 
 
745 
  /* Go to next argument */
746 
  while (*pstr == ' ')
747 
    pstr++;
748 
 
749 
  /* Get argument 2 from the string */
750 
  ptmp = sarg;
751 
  if (*pstr)
752 
    args++;
753 
  while (*pstr != '\0' && *pstr != ' ')
754 
    *ptmp++ = *pstr++;
755 
  *ptmp = '\0';
756 
 
757 
  /* Change argument 2 to unsigned long */
758 
  if (sarg[0])
759 
    iarg[1] = strtoul(sarg);
760 
 
761 
  /* Go to next argument */
762 
  while (*pstr == ' ')
763 
    pstr++;
764 
 
765 
  /* Get argument 3 from the string */
766 
  ptmp = sarg;
767 
  if (*pstr)
768 
    args++;
769 
  while (*pstr != '\0' && *pstr != ' ')
770 
    *ptmp++ = *pstr++;
771 
  *ptmp = '\0';
772 
 
773 
  /* Change argument 3 to unsigned long */
774 
  if (sarg[0])
775 
    iarg[2] = strtoul(sarg);
776 
 
777 
 
778 
  /* Process command and arguments by executing
779 
     specific function. */
780 
  if (strcmp(cmd, "help") == 0)
781 
    {
782 
      uart_print_str("dm <start addr> [<end addr>] ");
783 
      uart_print_str("- display memory location 32-bit\n");
784 
      uart_print_str("pm <addr> [<stop_addr>] <value> ");
785 
      uart_print_str("- patch memory location 32-bit\n");
786 
      uart_print_str("ic_enable - enable instruction cache\n");
787 
      uart_print_str("ic_disable - disable instruction cache\n");
788 
      uart_print_str("dc_enable - enable data cache\n");
789 
      uart_print_str("dc_disable - disable data cache\n");
790 
      uart_print_str("mfspr <spr_addr> - show SPR\n");
791 
      uart_print_str("mtspr <spr_addr> <value> - set SPR\n");
792 
      uart_print_str("eth_init - init ethernet\n");
793 
      uart_print_str("dhry [<num_runs>] - run dhrystone\n");
794 
      uart_print_str("show_txbd [<start BD>] [<max>] ");
795 
      uart_print_str("- show Tx buffer desc\n");
796 
      uart_print_str("show_rxbd [<start BD>] [<max>] ");
797 
      uart_print_str("- show Rx buffer desc\n");
798 
      uart_print_str("send_packet <length> [<start data>]");
799 
      uart_print_str("- create & send packet\n");
800 
      uart_print_str("set_dest_addr <addrhi> <addrmid> <addrlo>");
801 
      uart_print_str("- set destination address (for send_packet)\n");
802 
      uart_print_str("init_txbd_pool <max> ");
803 
      uart_print_str("- initialize Tx buffer descriptors\n");
804 
      uart_print_str("init_rxbd_pool <max> ");
805 
      uart_print_str("- initialize Rx buffer descriptors\n");
806 
      uart_print_str("show_phy_reg [<start_addr>] [<end addr>]");
807 
      uart_print_str("- show PHY registers\n");
808 
      uart_print_str("set_phy_reg <addr> <value>");
809 
      uart_print_str("- set PHY register\n");
810 
      uart_print_str("show_mac_regs ");
811 
      uart_print_str("- show all MAC registers\n");
812 
      uart_print_str("eth_int_enable ");
813 
      uart_print_str("- enable ethernet interrupt\n");
814 
      uart_print_str("show_rx_buffs [<show_all>] ");
815 
      uart_print_str("- show receive buffers (optional arg will also show empty buffers)\n");
816 
      uart_print_str("show_tx_buffs ");
817 
      uart_print_str("- show transmit buffers\n");
818 
      uart_print_str("testram <start_addr> <stop_addr> [<test_no>]");
819 
      uart_print_str("- run a simple RAM test\n");
820 
      uart_print_str("crt_enable");
821 
      uart_print_str("- enables CRT\n");
822 
      uart_print_str("crt_disable");
823 
      uart_print_str("- disables CRT\n");
824 
      uart_print_str("crt_test");
825 
      uart_print_str("- enables CRT and displays some test patterns\n");
826 
      uart_print_str("camera_enable");
827 
      uart_print_str("- enables camera\n");
828 
      uart_print_str("camera_disable");
829 
      uart_print_str("- disables camera\n");
830 
    }
831 
  else if (strcmp(cmd, "show_txbd") == 0)
832 
  {
833 
    if (args == 1)
834 
      show_tx_bd(iarg[0], iarg[0]);
835 
    else if (args == 2)
836 
      show_tx_bd(iarg[0], iarg[1]);
837 
    else
838 
      show_tx_bd(0, 63);
839 
  }
840 
  else if (strcmp(cmd, "show_rxbd") == 0)
841 
  {
842 
    if (args == 1)
843 
      show_rx_bd(iarg[0], iarg[0]);
844 
    else if (args == 2)
845 
      show_rx_bd(iarg[0], iarg[1]);
846 
    else
847 
      show_rx_bd(0, 63);
848 
  }
849 
  else if (strcmp(cmd, "dm") == 0)
850 
  {
851 
    if (args == 1)
852 
      show_mem(iarg[0], iarg[0]);
853 
    else if (args == 2)
854 
      show_mem(iarg[0], iarg[1]);
855 
    else
856 
      uart_print_str("missing/wrong parameters\n");
857 
  }
858 
  else if (strcmp(cmd, "pm") == 0)
859 
  {
860 
    if ((args == 3) || (args == 2))
861 
    {
862 
      unsigned long addr = iarg[0];
863 
      unsigned long stop_addr = iarg[1];
864 
      unsigned long value = iarg[2];
865 
 
866 
      if (args == 2)
867 
      {
868 
        stop_addr = iarg[0];
869 
        value = iarg[1];
870 
      }
871 
 
872 
      for (; addr <= stop_addr; addr += 4)
873 
        REG32(addr) = value;
874 
      show_mem(iarg[0], stop_addr);
875 
    }
876 
    else
877 
      uart_print_str("pm <addr> [<stop_addr>] <value>\n");
878 
  }
879 
  else if (strcmp(cmd, "mfspr") == 0)
880 
  {
881 
    if (args == 1)
882 
      cmd_mfspr(iarg[0]);
883 
    else
884 
      uart_print_str("missing/wrong parameters\n");
885 
  }
886 
  else if (strcmp(cmd, "dhry") == 0)
887 
  {
888 
    if (args == 1)
889 
      dhry_main(iarg[0]);
890 
    else
891 
      dhry_main(20);
892 
  }
893 
  else if (strcmp(cmd, "mtspr") == 0)
894 
  {
895 
    if (args == 2)
896 
      cmd_mtspr(iarg[0], iarg[1]);
897 
    else
898 
      uart_print_str("missing/wrong parameters\n");
899 
  }
900 
  else if (strcmp(cmd, "eth_init") == 0)
901 
      eth_init();
902 
  else if (strcmp(cmd, "ic_enable") == 0)
903 
      ic_enable();
904 
  else if (strcmp(cmd, "ic_disable") == 0)
905 
      ic_disable();
906 
  else if (strcmp(cmd, "dc_enable") == 0)
907 
      dc_enable();
908 
  else if (strcmp(cmd, "dc_disable") == 0)
909 
      dc_disable();
910 
  else if (strcmp(cmd, "show_mac_regs") == 0)
911 
      show_mac_regs();
912 
  else if (strcmp(cmd, "init_txbd_pool") == 0)
913 
  {
914 
    if (args == 1)
915 
      init_tx_bd_pool(iarg[0]);
916 
    else
917 
      uart_print_str("missing/wrong parameter\n");
918 
  }
919 
  else if (strcmp(cmd, "init_rxbd_pool") == 0)
920 
  {
921 
    if (args == 1)
922 
      init_rx_bd_pool(iarg[0]);
923 
    else
924 
      uart_print_str("missing/wrong parameter\n");
925 
  }
926 
  else if (strcmp(cmd, "send_packet") == 0)
927 
  {
928 
    if (args == 1)
929 
      send_packet(iarg[0], 31);
930 
    else
931 
    if (args == 2)
932 
      send_packet(iarg[0], iarg[1]);
933 
    else
934 
      uart_print_str("missing/wrong parameters\n");
935 
  }
936 
  else if (strcmp(cmd, "show_rx_buffs") == 0)
937 
  {
938 
    if (args == 0)
939 
      show_rx_buffs(63, 0);
940 
    else
941 
    if (args == 1)
942 
      show_rx_buffs(63, 1);
943 
    else
944 
      uart_print_str("missing/wrong parameters\n");
945 
  }
946 
  else if (strcmp(cmd, "show_tx_buffs") == 0)
947 
  {
948 
    if (args == 0)
949 
      show_tx_buffs(63);
950 
    else
951 
      uart_print_str("missing/wrong parameters\n");
952 
  }
953 
  else if (strcmp(cmd, "set_dest_addr") == 0)
954 
  {
955 
    if (args == 3)
956 
    {
957 
      dest_mac_addr[0] = (iarg[0] >> 8) & 0xff;
958 
      dest_mac_addr[1] = (iarg[0] >> 0) & 0xff;
959 
      dest_mac_addr[2] = (iarg[1] >> 8) & 0xff;
960 
      dest_mac_addr[3] = (iarg[1] >> 0) & 0xff;
961 
      dest_mac_addr[4] = (iarg[2] >> 8) & 0xff;
962 
      dest_mac_addr[5] = (iarg[2] >> 0) & 0xff;
963 
    }
964 
    else
965 
      uart_print_str("missing/wrong parameters\n");
966 
  }
967 
  else if (strcmp(cmd, "show_phy_reg") == 0)
968 
  {
969 
    if (args == 1)
970 
      show_phy_reg(iarg[0], iarg[0]);
971 
    else
972 
    if (args == 2)
973 
      show_phy_reg(iarg[0], iarg[1]);
974 
    else
975 
      show_phy_reg(0, 30);
976 
  }
977 
  else if (strcmp(cmd, "testram") == 0)
978 
  {
979 
    if (args == 2)
980 
      testram(iarg[0], iarg[1], 0);
981 
    else
982 
    if (args == 3)
983 
      testram(iarg[0], iarg[1], iarg[2]);
984 
    else
985 
      uart_print_str("missing/wrong parameters\n");
986 
  }
987 
  else if (strcmp(cmd, "set_phy_reg") == 0)
988 
  {
989 
    if (args == 2)
990 
      set_phy_reg(iarg[0], iarg[1]);
991 
    else
992 
      uart_print_str("missing/wrong parameters\n");;
993 
  }
994 
  else if (strcmp(cmd, "crt_enable") == 0)
995 
      crt_enable();
996 
  else if (strcmp(cmd, "crt_disable") == 0)
997 
      crt_disable();
998 
  else if (strcmp(cmd, "crt_test") == 0)
999 
      crt_test();
1000 
  else if (strcmp(cmd, "camera_enable") == 0)
1001 
      camera_enable();
1002 
  else if (strcmp(cmd, "camera_disable") == 0)
1003 
      camera_disable();
1004 
  else if (strcmp(cmd, "") == 0);
1005 
  else
1006 
    uart_print_str("Unknown command\n");
1007 
}
1008 
 
1009 
int main(unsigned long dst, unsigned long src)
1010 
{
1011 
  int i;
1012 
  unsigned long counter=0;
1013 
 
1014 
  /* Initialize controller */
1015 
  uart_init();
1016 
 
1017 
  uart_print_str("Ethernet Monitor (type 'help' for help)\n");
1018 
 
1019 
  /* Initialize controller */
1020 
/*  eth_init();*/
1021 
  uart_print_str("Ethernet not initialized (run eth_init command)\n");
1022 
/*  init_rx_bd_pool(0); */
1023 
/*  init_tx_bd_pool(3);*/
1024 
 
1025 
  while(1)
1026 
  {
1027 
   mon_command();
1028 
  }
1029 
}
1030 
 
1031 
void eth_int(void)
1032 
{
1033 
 
1034 
}
1035 
 
1036 
__main(void)
1037 
{
1038 
}
1039 
 

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