OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [orp/] [orp_soc/] [sw/] [tick/] [tick.S] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1156 lampret 
#include "spr_defs.h"
2 
 
3 
.global _main
4 
 
5 
/* Within the test we'll use following global variables:
6 
 
7 
   r16 interrupt counter
8 
   r17 current tick timer comparison counter
9 
   r18 sanity counter
10 
   r19 loop counter
11 
   r20 temp value of SR reg
12 
   r21 temp value of TTMR reg.
13 
   r23 RAM_START
14 
 
15 
   r25-r31 used by int handler
16 
 
17 
   The test do the following:
18 
   We set up the tick timer to trigger once and then we trigger interrupts incrementally
19 
   on every cycle in the specified test program; on interrupt handler we check if data computed
20 
   so far exactly matches precalculated values. If interrupt has returned incorreclty, we can
21 
   detect this using assertion routine at the end.
22 
*/
23 
 
24 
#define  RAM_START 0x00010000
25 
 
26 
.section .vectors, "ax"
27 
.org 0x100
28 
 
29 
  l.nop
30 
  l.j     _main
31 
  l.nop
32 
 
33 
.org 0x500
34 
#
35 
# Interrupt handler
36 
#
37 
 
38 
  l.addi  r31,r3,0
39 
# get interrupted program pc
40 
  l.mfspr r25,r0,SPR_EPCR_BASE
41 
 
42 
# calculate instruction address
43 
  l.movhi r26,hi(_ie_start)
44 
  l.ori   r26,r26,lo(_ie_start)
45 
  l.addi  r3,r25,0    #print insn index
46 
  l.nop   2
47 
  l.sub   r25,r25,r26
48 
  l.addi  r3,r25,0    #print insn index
49 
  l.nop   2
50 
 
51 
  l.addi  r3,r31,0    # restore r3
52 
  l.sfeqi r25, 0x00
53 
  l.bf    _i00
54 
  l.sfeqi r25, 0x04
55 
  l.bf    _i04
56 
  l.sfeqi r25, 0x08
57 
  l.bf    _i08
58 
  l.sfeqi r25, 0x0c
59 
  l.bf    _i0c
60 
  l.sfeqi r25, 0x10
61 
  l.bf    _i10
62 
  l.sfeqi r25, 0x14
63 
  l.bf    _i14
64 
  l.sfeqi r25, 0x18
65 
  l.bf    _i18
66 
  l.sfeqi r25, 0x1c
67 
  l.bf    _i1c
68 
  l.sfeqi r25, 0x20
69 
  l.bf    _i20
70 
  l.sfeqi r25, 0x24
71 
  l.bf    _i24
72 
  l.sfeqi r25, 0x28
73 
  l.bf    _i28
74 
  l.sfeqi r25, 0x2c
75 
  l.bf    _i2c
76 
  l.sfeqi r25, 0x30
77 
  l.bf    _i30
78 
  l.sfeqi r25, 0x34
79 
  l.bf    _i34
80 
  l.sfeqi r25, 0x38
81 
  l.bf    _i38
82 
  l.nop
83 
 
84 
# value not defined
85 
_die:
86 
  l.nop   2             #print r3
87 
 
88 
  l.addi  r3,r0,0xeeee
89 
  l.nop   2
90 
  l.addi  r3,r0,1
91 
  l.jal   _exit
92 
  l.nop
93 
1:
94 
  l.j     1b
95 
  l.nop
96 
 
97 
.section  .text
98 
_main:
99 
        l.nop
100 
        l.nop
101 
 
102 
#
103 
# set tick counter to initial 3 cycles
104 
#
105 
  l.addi r16,r0,0
106 
  l.addi r17,r0,1
107 
  l.addi r18,r0,0
108 
  l.addi r19,r0,0
109 
  l.addi r22,r0,0
110 
 
111 
  l.movhi r23,hi(RAM_START)
112 
  l.ori   r23,r23,lo(RAM_START)
113 
 
114 
#
115 
# unmask all ints
116 
#
117 
        l.movhi r5,0xffff
118 
        l.ori   r5,r5,0xffff
119 
        l.mtspr r0,r5,SPR_PICMR         # set PICMR
120 
 
121 
# Set r20 to hold enable exceptions and interrupts
122 
        l.mfspr r20,r0,SPR_SR
123 
        l.ori r20,r20,SPR_SR_SM|SPR_SR_TEE|SPR_SR_F
124 
 
125 
# Set r21 to hold value of TTMR
126 
        l.movhi r5,hi(SPR_TTMR_SR | SPR_TTMR_IE)
127 
        l.add  r21,r5,r17
128 
 
129 
#
130 
# MAIN LOOP
131 
#
132 
_main_loop:
133 
# reinitialize memory and registers
134 
  l.addi  r3,r0,0xaaaa
135 
  l.addi  r9,r0,0xbbbb
136 
  l.sw    0(r23),r3
137 
  l.sw    4(r23),r9
138 
  l.sw    8(r23),r3
139 
 
140 
# Reinitializes tick timer
141 
  l.addi  r17,r17,1
142 
  l.mtspr r0,r0,SPR_TTCR                # set TTCR
143 
  l.mtspr r0,r21,SPR_TTMR               # set TTMR
144 
  l.mtspr r0,r0,SPR_TTCR                # set TTCR
145 
        l.addi  r21,r21,1
146 
 
147 
# Enable exceptions and interrupts
148 
        l.mtspr r0,r20,SPR_SR   # set SR
149 
 
150 
##### TEST CODE #####
151 
_ie_start:
152 
  l.movhi r3,0x1234         #00
153 
  l.sw    0(r23),r3         #04
154 
  l.movhi r3,hi(RAM_START)  #08
155 
  l.lwz   r3,0(r3)          #0c
156 
  l.movhi r3,hi(RAM_START)  #10
157 
  l.addi  r3,r3,4           #14
158 
  l.j     1f                #18
159 
  l.lwz   r3,0(r3)          #1c
160 
  l.addi  r3,r3,1           #20
161 
1:
162 
  l.sfeqi r3,0xdead         #24
163 
  l.jal   2f                #28
164 
  l.addi  r3,r0,0x5678      #2c
165 
 
166 
_return_addr:
167 
2:
168 
  l.bf    _die              #30
169 
  l.sw    8(r23),r3         #34
170 
_ie_end:
171 
  l.nop                     #38
172 
##### END OF TEST CODE #####
173 
 
174 
# do some testing
175 
 
176 
  l.j     _main_loop
177 
  l.nop
178 
 
179 
_i00:
180 
  l.sfeqi r3,0xaaaa
181 
  l.bnf   _die
182 
  l.nop
183 
  l.j     _resume
184 
  l.nop
185 
_i04:
186 
  l.movhi  r26,0x1234
187 
  l.sfeq   r3,r26
188 
  l.bnf   _die
189 
  l.nop
190 
  l.lwz   r26,0(r23)
191 
  l.sfeqi r26,0xaaaa
192 
  l.bnf   _die
193 
  l.nop
194 
  l.j     _resume
195 
  l.nop
196 
_i08:
197 
  l.movhi r26,0x1234
198 
  l.sfeq  r3,r26
199 
  l.bnf   _die
200 
  l.nop
201 
  l.lwz   r27,0(r23)
202 
  l.sfeq  r27,r26
203 
  l.bnf   _die
204 
  l.nop
205 
  l.j     _resume
206 
  l.nop
207 
_i0c:
208 
  l.sfeq  r3,r23
209 
  l.bnf   _die
210 
  l.nop
211 
  l.j     _resume
212 
  l.nop
213 
_i10:
214 
  l.movhi r26,0x1234
215 
  l.sfeq  r26,r3
216 
  l.bnf   _die
217 
  l.nop
218 
  l.j     _resume
219 
  l.nop
220 
_i14:
221 
  l.sfeq  r3,r23
222 
  l.bnf   _die
223 
  l.nop
224 
  l.j     _resume
225 
  l.nop
226 
_i18:
227 
  l.addi  r26,r23,4
228 
  l.sfeq  r3,r26
229 
  l.bnf   _die
230 
  l.nop
231 
  l.j     _resume
232 
  l.nop
233 
_i1c:
234 
  l.j     _die
235 
  l.nop
236 
_i20:
237 
  l.j     _die
238 
  l.nop
239 
_i24:
240 
  l.mfspr r26,r0,SPR_ESR_BASE
241 
  l.addi  r30,r3,0
242 
  l.addi  r3,r26,0
243 
  l.nop   2
244 
  l.addi  r3,r30,0
245 
  l.andi  r26,r26,SPR_SR_F
246 
  l.sfeq  r26,r0
247 
  l.bf   _die
248 
  l.nop
249 
  l.sfeqi  r3,0xbbbb
250 
  l.bnf   _die
251 
  l.nop
252 
  l.j     _resume
253 
  l.nop
254 
_i28:
255 
  l.mfspr r26,r0,SPR_ESR_BASE
256 
  l.addi  r30,r3,0
257 
  l.addi  r3,r26,0
258 
  l.nop   2
259 
  l.addi  r3,r30,0
260 
  l.andi  r26,r26,SPR_SR_F
261 
  l.sfeq  r26,r0
262 
  l.bnf    _die
263 
  l.nop
264 
  l.sfeqi  r22,1
265 
  l.bf     _resume
266 
  l.addi   r22,r0,1
267 
  l.sfeqi  r9,0xbbbb
268 
  l.bnf   _die
269 
  l.nop
270 
  l.j     _resume
271 
  l.nop
272 
_i2c:
273 
  l.movhi  r26,hi(_return_addr)
274 
  l.ori    r26,r26,lo(_return_addr)
275 
  l.sfeq   r9,r26
276 
  l.bnf   _die
277 
  l.nop
278 
  l.sfeqi  r3,0xbbbb
279 
  l.bnf   _die
280 
  l.nop
281 
  l.j     _resume
282 
  l.nop
283 
_i30:
284 
  l.sfeqi  r3,0x5678
285 
  l.bnf   _die
286 
  l.nop
287 
  l.j     _resume
288 
  l.nop
289 
_i34:
290 
  l.sfeqi  r3,0x5678
291 
  l.bnf   _die
292 
  l.nop
293 
  l.lwz    r26,8(r23)
294 
  l.sfeqi  r26,0xaaaa
295 
  l.bnf   _die
296 
  l.nop
297 
  l.j     _resume
298 
  l.nop
299 
_i38:
300 
  l.lwz    r26,8(r23)
301 
  l.sfeqi  r26,0x5678
302 
  l.bnf   _die
303 
  l.nop
304 
#
305 
# mark finished ok
306 
#
307 
  l.movhi r3,hi(0xdeaddead)
308 
  l.ori   r3,r3,lo(0xdeaddead)
309 
  l.nop   2
310 
  l.addi  r3,r0,0
311 
  l.jal   _exit
312 
  l.nop
313 
_ok:
314 
  l.j     _ok
315 
  l.nop
316 
 
317 
_resume:
318 
  l.mfspr  r27,r0,SPR_ESR_BASE
319 
  l.addi   r26,r0,SPR_SR_TEE
320 
  l.addi   r28,r0,-1
321 
  l.xor    r26,r26,r28
322 
  l.and    r26,r26,r27
323 
  l.mtspr  r0,r26,SPR_ESR_BASE
324 
 
325 
  l.rfe
326 
  l.addi    r3,r3,5         # should not be executed

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.