| 1 |
1195 |
dries |
#-- Synplicity, Inc.
|
| 2 |
|
|
#-- Version 7.3
|
| 3 |
|
|
#-- Project file D:\or1k\xess\xsv_fpga\orp_soc\syn\synplify\xsv_fpga_top.prj
|
| 4 |
|
|
#-- Written on Fri Sep 05 16:00:16 2003
|
| 5 |
|
|
|
| 6 |
|
|
|
| 7 |
|
|
#add_file options
|
| 8 |
|
|
add_file -verilog "$LIB/xilinx/virtex.v"
|
| 9 |
|
|
add_file -verilog "../../rtl/verilog/audio/fifo_empty_16.v"
|
| 10 |
|
|
add_file -verilog "../../rtl/verilog/audio/audio_top.v"
|
| 11 |
|
|
add_file -verilog "../../rtl/verilog/audio/audio_wb_if.v"
|
| 12 |
|
|
add_file -verilog "../../rtl/verilog/audio/fifo_4095_16.v"
|
| 13 |
|
|
add_file -verilog "../../rtl/verilog/audio/audio_codec_if.v"
|
| 14 |
|
|
add_file -verilog "../../rtl/verilog/dbg_interface/dbg_trace.v"
|
| 15 |
|
|
add_file -verilog "../../rtl/verilog/dbg_interface/dbg_register.v"
|
| 16 |
|
|
add_file -verilog "../../rtl/verilog/dbg_interface/dbg_registers.v"
|
| 17 |
|
|
add_file -verilog "../../rtl/verilog/dbg_interface/dbg_sync_clk1_clk2.v"
|
| 18 |
|
|
add_file -verilog "../../rtl/verilog/dbg_interface/dbg_top.v"
|
| 19 |
|
|
add_file -verilog "../../rtl/verilog/dbg_interface/dbg_crc8_d1.v"
|
| 20 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_crc.v"
|
| 21 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/xilinx_dist_ram_16x32.v"
|
| 22 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_fifo.v"
|
| 23 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_maccontrol.v"
|
| 24 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_macstatus.v"
|
| 25 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_miim.v"
|
| 26 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_outputcontrol.v"
|
| 27 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_random.v"
|
| 28 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_receivecontrol.v"
|
| 29 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_register.v"
|
| 30 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_registers.v"
|
| 31 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_rxaddrcheck.v"
|
| 32 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_rxcounters.v"
|
| 33 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_rxethmac.v"
|
| 34 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_rxstatem.v"
|
| 35 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_shiftreg.v"
|
| 36 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_top.v"
|
| 37 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_transmitcontrol.v"
|
| 38 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_txcounters.v"
|
| 39 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_txethmac.v"
|
| 40 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_txstatem.v"
|
| 41 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_spram_256x32.v"
|
| 42 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_wishbone.v"
|
| 43 |
|
|
add_file -verilog "../../rtl/verilog/ethernet/eth_clockgen.v"
|
| 44 |
|
|
add_file -verilog "../../rtl/verilog/mem_if/sram_top.v"
|
| 45 |
|
|
add_file -verilog "../../rtl/verilog/mem_if/flash_top.v"
|
| 46 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_xcv_ram32x8d.v"
|
| 47 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_amultp2_32x32.v"
|
| 48 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_cfgr.v"
|
| 49 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_cpu.v"
|
| 50 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_ctrl.v"
|
| 51 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_dc_fsm.v"
|
| 52 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_dc_ram.v"
|
| 53 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_dc_tag.v"
|
| 54 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_dc_top.v"
|
| 55 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_defines.v"
|
| 56 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_dmmu_tlb.v"
|
| 57 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_dmmu_top.v"
|
| 58 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_dpram_32x32.v"
|
| 59 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_du.v"
|
| 60 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_except.v"
|
| 61 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_freeze.v"
|
| 62 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_genpc.v"
|
| 63 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_gmultp2_32x32.v"
|
| 64 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_ic_fsm.v"
|
| 65 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_ic_ram.v"
|
| 66 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_ic_tag.v"
|
| 67 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_ic_top.v"
|
| 68 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_if.v"
|
| 69 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_immu_tlb.v"
|
| 70 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_immu_top.v"
|
| 71 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_lsu.v"
|
| 72 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_mem2reg.v"
|
| 73 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_mult_mac.v"
|
| 74 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_operandmuxes.v"
|
| 75 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_pic.v"
|
| 76 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_pm.v"
|
| 77 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_reg2mem.v"
|
| 78 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_rfram_generic.v"
|
| 79 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_rf.v"
|
| 80 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_spram_1024x32.v"
|
| 81 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_spram_1024x8.v"
|
| 82 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_spram_2048x32.v"
|
| 83 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_spram_2048x8.v"
|
| 84 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_spram_256x21.v"
|
| 85 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_spram_512x20.v"
|
| 86 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_spram_64x14.v"
|
| 87 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_spram_64x22.v"
|
| 88 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_spram_64x24.v"
|
| 89 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_sprs.v"
|
| 90 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_sb.v"
|
| 91 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_sb_fifo.v"
|
| 92 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_top.v"
|
| 93 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_tpram_32x32.v"
|
| 94 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_tt.v"
|
| 95 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_wb_biu.v"
|
| 96 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_wbmux.v"
|
| 97 |
|
|
add_file -verilog "../../rtl/verilog/or1200/or1200_alu.v"
|
| 98 |
|
|
add_file -verilog "../../rtl/verilog/ps2/ps2_mouse.v"
|
| 99 |
|
|
add_file -verilog "../../rtl/verilog/ps2/ps2_wb_if.v"
|
| 100 |
|
|
add_file -verilog "../../rtl/verilog/ps2/ps2_io_ctrl.v"
|
| 101 |
|
|
add_file -verilog "../../rtl/verilog/ps2/ps2_keyboard.v"
|
| 102 |
|
|
add_file -verilog "../../rtl/verilog/ps2/ps2_top.v"
|
| 103 |
|
|
add_file -verilog "../../rtl/verilog/ps2/ps2_translation_table.v"
|
| 104 |
|
|
add_file -verilog "../../rtl/verilog/ssvga/crtc_iob.v"
|
| 105 |
|
|
add_file -verilog "../../rtl/verilog/ssvga/ssvga_crtc.v"
|
| 106 |
|
|
add_file -verilog "../../rtl/verilog/ssvga/ssvga_fifo.v"
|
| 107 |
|
|
add_file -verilog "../../rtl/verilog/ssvga/ssvga_top.v"
|
| 108 |
|
|
add_file -verilog "../../rtl/verilog/ssvga/ssvga_wbm_if.v"
|
| 109 |
|
|
add_file -verilog "../../rtl/verilog/ssvga/ssvga_wbs_if.v"
|
| 110 |
|
|
add_file -verilog "../../rtl/verilog/uart16550/raminfr.v"
|
| 111 |
|
|
add_file -verilog "../../rtl/verilog/uart16550/uart_rfifo.v"
|
| 112 |
|
|
add_file -verilog "../../rtl/verilog/uart16550/uart_tfifo.v"
|
| 113 |
|
|
add_file -verilog "../../rtl/verilog/uart16550/uart_wb.v"
|
| 114 |
|
|
add_file -verilog "../../rtl/verilog/uart16550/uart_receiver.v"
|
| 115 |
|
|
add_file -verilog "../../rtl/verilog/uart16550/uart_regs.v"
|
| 116 |
|
|
add_file -verilog "../../rtl/verilog/uart16550/uart_top.v"
|
| 117 |
|
|
add_file -verilog "../../rtl/verilog/uart16550/uart_transmitter.v"
|
| 118 |
|
|
add_file -verilog "../../rtl/verilog/uart16550/uart_debug_if.v"
|
| 119 |
|
|
add_file -verilog "../../rtl/verilog/tc_top.v"
|
| 120 |
|
|
add_file -verilog "../../rtl/verilog/tdm_slave_if.v"
|
| 121 |
|
|
add_file -verilog "../../rtl/verilog/xsv_fpga_top.v"
|
| 122 |
|
|
|
| 123 |
|
|
|
| 124 |
|
|
#implementation: "rev_1"
|
| 125 |
|
|
impl -add rev_1
|
| 126 |
|
|
|
| 127 |
|
|
#device options
|
| 128 |
|
|
set_option -technology VIRTEX
|
| 129 |
|
|
set_option -part XCV800
|
| 130 |
|
|
set_option -package HQ240
|
| 131 |
|
|
set_option -speed_grade -4
|
| 132 |
|
|
|
| 133 |
|
|
#compilation/mapping options
|
| 134 |
|
|
set_option -default_enum_encoding default
|
| 135 |
|
|
set_option -symbolic_fsm_compiler 0
|
| 136 |
|
|
set_option -resource_sharing 0
|
| 137 |
|
|
set_option -use_fsm_explorer 0
|
| 138 |
|
|
set_option -top_module "xsv_fpga_top"
|
| 139 |
|
|
|
| 140 |
|
|
#map options
|
| 141 |
|
|
set_option -frequency 10.000
|
| 142 |
|
|
set_option -fanout_limit 100
|
| 143 |
|
|
set_option -disable_io_insertion 0
|
| 144 |
|
|
set_option -pipe 0
|
| 145 |
|
|
set_option -update_models_cp 0
|
| 146 |
|
|
set_option -verification_mode 0
|
| 147 |
|
|
set_option -fixgatedclocks 0
|
| 148 |
|
|
set_option -modular 0
|
| 149 |
|
|
set_option -retiming 0
|
| 150 |
|
|
|
| 151 |
|
|
#simulation options
|
| 152 |
|
|
set_option -write_verilog 0
|
| 153 |
|
|
set_option -write_vhdl 0
|
| 154 |
|
|
|
| 155 |
|
|
#automatic place and route (vendor) options
|
| 156 |
|
|
set_option -write_apr_constraint 1
|
| 157 |
|
|
|
| 158 |
|
|
#set result format/file last
|
| 159 |
|
|
project -result_file "rev_1/xsv_fpga_top.edf"
|
| 160 |
|
|
set_option -include_path "/or1k/xess/xsv_fpga/rtl/verilog/;/or1k/xess/xsv_fpga/rl/verilog/dbg_interface;/or1k/xess/xsv_fpga/rtl/verilog/audio/;/or1k/xess/xsv_fpga/rtl/verilog/ethernet/;/or1k/xess/xsv_fpga/rtl/verilog/mem_if/;/or1k/xess/xsv_fpga/rtl/verilog/or1200/;/or1k/xess/xsv_fpga/rtl/verilog/ps2/;/or1k/xess/xsv_fpga/rtl/verilog/ssvga/;/or1k/xess/xsv_fpga/rtl/verilog/uart16550/;D:/or1k/xess/xsv_fpga/orp_soc/rtl/verilog/uart16550/"
|
| 161 |
|
|
impl -active "rev_1"
|
