URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [orpmon/] [cmds/] [eth.c] - Blame information for rev 809

Go to most recent revision | Details | Compare with Previous | View Log


#include "common.h"
#include "uart.h"
#include "eth.h"
#include "spr_defs.h"
 
extern int tx_pointer_index;
unsigned long dest_mac_addr[6];
 
#if 0
void show_tx_bd(int start, int max)
{
  int cnt, i;
 
  for(i = start; i <= max; i++) {
    /* Read Tx BD */
    printf ("LEN:%04", REG32(ETH_BD_BASE + (i << 3)) >> 16);
    printf (" RD:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 15) & 0x1);
    printf (" IRQ:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 14) & 0x1);
    printf (" WR:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 13) & 0x1);
    printf (" PAD:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 12) & 0x1);
    printf (" CRC:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 11) & 0x1);
    printf (" UR:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 8) & 0x1);
    printf (" RTRY:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 4) & 0xf);
    printf (" RL:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 3) & 0x1);
    printf (" LC:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 2) & 0x1);
    printf (" DF:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 1) & 0x1);
    printf (" CS:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 0) & 0x1);
    printf ("\nTx Buffer Pointer: %08x\n", REG32(ETH_BD_BASE + (i << 3) + 4));
  }
}
 
void show_rx_bd (int start, int max)
{
  int cnt, i;
  unsigned long rx_bd_base, rx_bd_num;
 
  rx_bd_num =  REG32(ETH_REG_BASE + ETH_RXBD_NUM);
  rx_bd_base = ETH_BD_BASE + (rx_bd_num << 2);
 
  for(i = start; i <= max; i++){
    /* Read Rx BD */
    printf ("LEN:%04", REG32(rx_bd_base + (i << 3)) >> 16);
    printf (" E:%04", (REG32(rx_bd_base + (i << 3)) >> 15) & 0x1);
    printf (" IRQ:%04", (REG32(rx_bd_base + (i << 3)) >> 14) & 0x1);
    printf (" WR:%04", (REG32(rx_bd_base + (i << 3)) >> 13) & 0x1);
    printf (" M:%04", (REG32(rx_bd_base + (i << 3)) >> 7) & 0x1);
    printf (" OR:%04", (REG32(rx_bd_base + (i << 3)) >> 6) & 0x1);
    printf (" IS:%04", (REG32(rx_bd_base + (i << 3)) >> 5) & 0x1);
    printf (" DN:%04", (REG32(rx_bd_base + (i << 3)) >> 4) & 0x1);
    printf (" TL:%04", (REG32(rx_bd_base + (i << 3)) >> 3) & 0x1);
    printf (" SF:%04", (REG32(rx_bd_base + (i << 3)) >> 2) & 0x1);
    printf (" CRC:%04", (REG32(rx_bd_base + (i << 3)) >> 1) & 0x1);
    printf (" LC:%04", (REG32(rx_bd_base + (i << 3)) >> 0) & 0x1);
    printf ("\nRx Buffer Pointer: %08x\n", REG32(rx_bd_base + (i << 3) + 4));
  }
}
 
void show_buffer(unsigned long start_addr, unsigned long len)
{
  show_mem(start_addr, start_addr + len - 1);
}
 
void show_rx_buffs(int max, int show_all)
{
 
  int i;
  unsigned long rx_bd_base, rx_bd_num;
 
  rx_bd_num =  REG32(ETH_REG_BASE + ETH_RXBD_NUM);
  rx_bd_base = ETH_BD_BASE + (rx_bd_num << 2);
 
  for(i=0; i<=max; i++)
  {
    if (!(REG32(rx_bd_base + (i << 3)) & ETH_RX_BD_EMPTY) || show_all)
    {
      printf ("Rx BD No. %04x located at %08x\n", i, rx_bd_base + (i << 3));
      show_rx_bd(i, i);
      show_buffer(REG32(rx_bd_base + (i << 3) + 4), REG32(rx_bd_base + (i << 3)) >> 16);
      printf ("\n");
    }
    if (REG32(rx_bd_base + (i << 3)) & ETH_RX_BD_WRAP)
      return;
  }
}
 
void show_tx_buffs(int max)
{
 
  int i;
 
  for(i=0; i<=max; i++)
  {
    if (1)
    {
      printf ("Tx BD No. %04x located at %08x\n", i, ETH_BD_BASE + (i << 3));
      show_tx_bd(i, i);
      show_buffer(REG32(ETH_BD_BASE + (i << 3) + 4), REG32(ETH_BD_BASE + (i << 3)) >> 16);
      printf ("\n");
    }
    if (REG32(ETH_BD_BASE + (i << 3)) & ETH_TX_BD_WRAP)
      return;
  }
}
 
void show_phy_reg (unsigned long start_addr, unsigned long stop_addr)
{
 
  unsigned long addr;
 
  if (start_addr == stop_addr)
  {
    printf ("\nSet MII RGAD ADDRESS to %08x", start_addr);
    printf ("\nMII Command = Read Status\n");
  }
 
  for (addr = start_addr; addr <= stop_addr; addr++)
  {
    REG32(ETH_REG_BASE + ETH_MIIADDRESS) = addr<<8;
    REG32(ETH_REG_BASE + ETH_MIICOMMAND) = ETH_MIICOMMAND_RSTAT;
 
    printf ("PHY %04x", REG32(ETH_REG_BASE + ETH_MIIADDRESS) & 0x1f);
    printf (", addr %04x", REG32(ETH_REG_BASE + ETH_MIIADDRESS) >> 8);
    printf (": %08x\n", REG32(ETH_REG_BASE + ETH_MIIRX_DATA));
  }
}
 
void set_phy_reg (unsigned long addr, unsigned long val)
{
  printf ("\nSet MII RGAD ADDRESS to %08x", addr);
 
  REG32(ETH_REG_BASE + ETH_MIIADDRESS) = addr<<8;
 
  printf ("\nMII Command = Write Control Data\n");
  REG32(ETH_REG_BASE + ETH_MIICOMMAND) = ETH_MIICOMMAND_WCTRLDATA;
 
  REG32(ETH_REG_BASE + ETH_MIITX_DATA) = val;
 
  show_phy_reg(addr, addr);
}
 
void send_packet (unsigned long len, unsigned long start_data, int num_of_packets)
{
  unsigned long i, TxBD;
 
  while (num_of_packets--) {
    unsigned long *data = (unsigned long *)eth_get_tx_buf ();
 
    /* Set dest & src address */
    *data++ = dest_mac_addr[0] << 24 |
              dest_mac_addr[1] << 16 |
              dest_mac_addr[2] << 8  |
              dest_mac_addr[3] << 0;
 
    *data++ = dest_mac_addr[4] << 24 |
              dest_mac_addr[5] << 16 |
              ETH_MACADDR0     << 8  |
              ETH_MACADDR1     << 0;
 
    *data++ = ETH_MACADDR2     << 24 |
              ETH_MACADDR3     << 16 |
              ETH_MACADDR4     << 8  |
              ETH_MACADDR5     << 0;
 
    /* Write data to buffer */
    for(i = 12; i < len; i += 4)
      *data++ = (i + start_data - 12) << 24 | (i + start_data + 1 - 12) << 16 |
                (i + start_data + 2 - 12) << 8 | (i + start_data + 3 - 12);
 
    eth_send (data, len);
    printf (".");
  }
}
 
int eth_init_cmd (int argc, char *argv[])
{
  if (argc) return -1;
  eth_init (0);
  return 0;
}
 
int show_txbd_cmd (int argc, char *argv[])
{
  int cnt, i;
  int start, max;
 
  if (argc == 1) show_tx_bd (strtoul (argv[0]), strtoul (argv[0]));
  else if (argc == 2) show_tx_bd (strtoul (argv[0]), strtoul (argv[1]));
  else show_tx_bd (0, 63);
  return 0;
}
 
int show_rxbd_cmd (int argc, char *argv[])
{
  if (argc == 1) show_rx_bd (strtoul (argv[0]), strtoul (argv[0]));
  else if (argc == 2) show_rx_bd (strtoul (argv[0]), strtoul (argv[1]));
  else show_rx_bd (0, 63);
  return 0;
}
 
int send_packet_cmd (int argc, char *argv[])
{
  if (argc == 1) send_packet(strtoul (argv[0]), 31, 1);
  else if (argc == 2) send_packet(strtoul (argv[0]), strtoul (argv[1]), 1);
  else if (argc == 3) send_packet(strtoul (argv[0]), strtoul (argv[1]), strtoul (argv[2]));
  else return -1;
  return 0;
}
 
int set_dest_addr_cmd (int argc, char *argv[])
{
  if (argc == 3) {
    dest_mac_addr[0] = (strtoul (argv[0]) >> 8) & 0xff;
    dest_mac_addr[1] = (strtoul (argv[0]) >> 0) & 0xff;
    dest_mac_addr[2] = (strtoul (argv[1]) >> 8) & 0xff;
    dest_mac_addr[3] = (strtoul (argv[1]) >> 0) & 0xff;
    dest_mac_addr[4] = (strtoul (argv[2]) >> 8) & 0xff;
    dest_mac_addr[5] = (strtoul (argv[2]) >> 0) & 0xff;
  } else return -1;
  return 0;
}
 
int init_txbd_pool_cmd (int argc, char *argv[])
{
  if (argc == 1) init_tx_bd_pool(strtoul (argv[0]));
  else return -1;
  return 0;
}
 
int init_rxbd_pool_cmd (int argc, char *argv[])
{
  if (argc == 1) init_rx_bd_pool(strtoul (argv[0]));
  else return -1;
  return 0;
}
 
int show_phy_reg_cmd (int argc, char *argv[])
{
  if (argc == 1) show_phy_reg(strtoul (argv[0]), strtoul (argv[0]));
  else if (argc == 2) show_phy_reg(strtoul (argv[0]), strtoul (argv[1]));
  else show_phy_reg(0, 30);
  return 0;
}
 
int set_phy_reg_cmd (int argc, char *argv[])
{
  if (argc == 2) set_phy_reg(strtoul (argv[0]), strtoul (argv[1]));
  else return -1;
  return 0;
}
 
int show_mac_regs_cmd (int argc, char *argv[])
{
  if (argc) return -1;
  printf ("\n %08x", ETH_REG_BASE + ETH_MODER);
  printf (" MODER: %08x",REG32(ETH_REG_BASE + ETH_MODER));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_INT);
  printf (" INT: %08x", REG32(ETH_REG_BASE + ETH_INT));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_INT_MASK);
  printf (" INT_MASK: %08x", REG32(ETH_REG_BASE + ETH_INT_MASK));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_IPGT);
  printf (" IPGT: %08x", REG32(ETH_REG_BASE + ETH_IPGT));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_IPGR1);
  printf (" IPGR1: %08x", REG32(ETH_REG_BASE + ETH_IPGR1));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_IPGR2);
  printf (" IPGR2: %08x", REG32(ETH_REG_BASE + ETH_IPGR2));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_PACKETLEN);
  printf (" PACKETLEN: %08x", REG32(ETH_REG_BASE + ETH_PACKETLEN));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_COLLCONF);
  printf (" COLLCONF: %08x", REG32(ETH_REG_BASE + ETH_COLLCONF));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_RXBD_NUM);
  printf (" RX_BD_NUM: %08x", REG32(ETH_REG_BASE + ETH_RXBD_NUM));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_CTRLMODER);
  printf (" CTRLMODER: %08x", REG32(ETH_REG_BASE + ETH_CTRLMODER));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_MIIMODER);
  printf (" MIIMODER: %08x", REG32(ETH_REG_BASE + ETH_MIIMODER));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_MIICOMMAND);
  printf (" MIICOMMAND: %08x", REG32(ETH_REG_BASE + ETH_MIICOMMAND));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_MIIADDRESS);
  printf (" MIIADDRESS: %08x", REG32(ETH_REG_BASE + ETH_MIIADDRESS));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_MIITX_DATA);
  printf (" MIITX_DATA: %08x", REG32(ETH_REG_BASE + ETH_MIITX_DATA));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_MIIRX_DATA);
  printf (" MIIRX_DATA: %08x", REG32(ETH_REG_BASE + ETH_MIIRX_DATA));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_MIISTATUS);
  printf (" MIISTATUS: %08x", REG32(ETH_REG_BASE + ETH_MIISTATUS));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_MAC_ADDR0);
  printf (" MAC_ADDR0: %08x", REG32(ETH_REG_BASE + ETH_MAC_ADDR0));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_MAC_ADDR1);
  printf (" MAC_ADDR1: %08x", REG32(ETH_REG_BASE + ETH_MAC_ADDR1));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_HASH_ADDR0);
  printf (" ETH_HASH_ADDR0: %08x", REG32(ETH_REG_BASE + ETH_HASH_ADDR0));
 
  printf ("\n %08x", ETH_REG_BASE + ETH_HASH_ADDR1);
  printf (" ETH_HASH_ADDR1: %08x", REG32(ETH_REG_BASE + ETH_HASH_ADDR1));
 
  printf ("\n");
  return 0;
}
 
int eth_int_enable_cmd (int argc, char *argv[])
{
  if (argc) return -1;
  eth_int_enable ();
  return 0;
}
int show_rx_buffs_cmd (int argc, char *argv[])
{
  if (argc == 0) show_rx_buffs(63, 0);
  else if (argc == 1) show_rx_buffs(63, 1);
  else return -1;
  return 0;
}
 
int show_tx_buffs_cmd (int argc, char *argv[])
{
  if (argc == 0) show_tx_buffs(63);
  else return -1;
  return 0;
}
 
#endif
void module_eth_init ()
{
#if 0
  register_command ("eth_init", "",  "init ethernet", eth_init_cmd);
  register_command ("show_txbd", "[<start BD>] [<max>]", "show Tx buffer desc", show_txbd_cmd);
  register_command ("show_rxbd", "[<start BD>] [<max>]", "show Rx buffer desc", show_rxbd_cmd);
  register_command ("send_packet", "<length> [<start data>] [<num_of_packets>]", "create & send packet(s)", send_packet_cmd);
  register_command ("set_dest_addr", "<addrhi> <addrmid> <addrlo>", "set destination address (for send_packet)", set_dest_addr_cmd);
  register_command ("init_txbd_pool", "<max>", "initialize Tx buffer descriptors", init_txbd_pool_cmd);
  register_command ("init_rxbd_pool", "<max>", "initialize Rx buffer descriptors", init_rxbd_pool_cmd);
  register_command ("show_phy_reg", "[<start_addr>] [<end addr>]", "show PHY registers", show_phy_reg_cmd);
  register_command ("set_phy_reg", "<addr> <value>", "set PHY register", set_phy_reg_cmd);
  register_command ("show_mac_regs", "", "show all MAC registers", show_mac_regs_cmd);
  register_command ("eth_int_enable", "", "enable ethernet interrupt", eth_int_enable_cmd);
  register_command ("show_rx_buffs", "[<show_all>]", "show receive buffers (optional arg will also show empty buffers)", show_rx_buffs_cmd);
  register_command ("show_tx_buffs", "", "show transmit buffers", show_rx_buffs_cmd);
  /* Initialize controller */
/*  eth_init();*/
/*  printf ("Ethernet not initialized (run eth_init command)\n");*/
/*  init_rx_bd_pool(0); */
/*  init_tx_bd_pool(3);*/
#endif
}

Browse

Tools

Subversion Repositories or1k

[/] [or1k/] [trunk/] [orpmon/] [cmds/] [eth.c] - Blame information for rev 809

Line No.	Rev	Author	Line
1	809	simons	`#include "common.h"`
2			`#include "uart.h"`
3			`#include "eth.h"`
4			`#include "spr_defs.h"`
5
6			`extern int tx_pointer_index;`
7			`unsigned long dest_mac_addr[6];`
8
9			`#if 0`
10			`void show_tx_bd(int start, int max)`
11			`{`
12			`int cnt, i;`
13
14			`for(i = start; i <= max; i++) {`
15			`/* Read Tx BD */`
16			`printf ("LEN:%04", REG32(ETH_BD_BASE + (i << 3)) >> 16);`
17			`printf (" RD:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 15) & 0x1);`
18			`printf (" IRQ:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 14) & 0x1);`
19			`printf (" WR:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 13) & 0x1);`
20			`printf (" PAD:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 12) & 0x1);`
21			`printf (" CRC:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 11) & 0x1);`
22			`printf (" UR:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 8) & 0x1);`
23			`printf (" RTRY:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 4) & 0xf);`
24			`printf (" RL:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 3) & 0x1);`
25			`printf (" LC:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 2) & 0x1);`
26			`printf (" DF:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 1) & 0x1);`
27			`printf (" CS:%04", (REG32(ETH_BD_BASE + (i << 3)) >> 0) & 0x1);`
28			`printf ("\nTx Buffer Pointer: %08x\n", REG32(ETH_BD_BASE + (i << 3) + 4));`
29			`}`
30			`}`
31
32			`void show_rx_bd (int start, int max)`
33			`{`
34			`int cnt, i;`
35			`unsigned long rx_bd_base, rx_bd_num;`
36
37			`rx_bd_num = REG32(ETH_REG_BASE + ETH_RXBD_NUM);`
38			`rx_bd_base = ETH_BD_BASE + (rx_bd_num << 2);`
39
40			`for(i = start; i <= max; i++){`
41			`/* Read Rx BD */`
42			`printf ("LEN:%04", REG32(rx_bd_base + (i << 3)) >> 16);`
43			`printf (" E:%04", (REG32(rx_bd_base + (i << 3)) >> 15) & 0x1);`
44			`printf (" IRQ:%04", (REG32(rx_bd_base + (i << 3)) >> 14) & 0x1);`
45			`printf (" WR:%04", (REG32(rx_bd_base + (i << 3)) >> 13) & 0x1);`
46			`printf (" M:%04", (REG32(rx_bd_base + (i << 3)) >> 7) & 0x1);`
47			`printf (" OR:%04", (REG32(rx_bd_base + (i << 3)) >> 6) & 0x1);`
48			`printf (" IS:%04", (REG32(rx_bd_base + (i << 3)) >> 5) & 0x1);`
49			`printf (" DN:%04", (REG32(rx_bd_base + (i << 3)) >> 4) & 0x1);`
50			`printf (" TL:%04", (REG32(rx_bd_base + (i << 3)) >> 3) & 0x1);`
51			`printf (" SF:%04", (REG32(rx_bd_base + (i << 3)) >> 2) & 0x1);`
52			`printf (" CRC:%04", (REG32(rx_bd_base + (i << 3)) >> 1) & 0x1);`
53			`printf (" LC:%04", (REG32(rx_bd_base + (i << 3)) >> 0) & 0x1);`
54			`printf ("\nRx Buffer Pointer: %08x\n", REG32(rx_bd_base + (i << 3) + 4));`
55			`}`
56			`}`
57
58			`void show_buffer(unsigned long start_addr, unsigned long len)`
59			`{`
60			`show_mem(start_addr, start_addr + len - 1);`
61			`}`
62
63			`void show_rx_buffs(int max, int show_all)`
64			`{`
65
66			`int i;`
67			`unsigned long rx_bd_base, rx_bd_num;`
68
69			`rx_bd_num = REG32(ETH_REG_BASE + ETH_RXBD_NUM);`
70			`rx_bd_base = ETH_BD_BASE + (rx_bd_num << 2);`
71
72			`for(i=0; i<=max; i++)`
73			`{`
74			`if (!(REG32(rx_bd_base + (i << 3)) & ETH_RX_BD_EMPTY) \|\| show_all)`
75			`{`
76			`printf ("Rx BD No. %04x located at %08x\n", i, rx_bd_base + (i << 3));`
77			`show_rx_bd(i, i);`
78			`show_buffer(REG32(rx_bd_base + (i << 3) + 4), REG32(rx_bd_base + (i << 3)) >> 16);`
79			`printf ("\n");`
80			`}`
81			`if (REG32(rx_bd_base + (i << 3)) & ETH_RX_BD_WRAP)`
82			`return;`
83			`}`
84			`}`
85
86			`void show_tx_buffs(int max)`
87			`{`
88
89			`int i;`
90
91			`for(i=0; i<=max; i++)`
92			`{`
93			`if (1)`
94			`{`
95			`printf ("Tx BD No. %04x located at %08x\n", i, ETH_BD_BASE + (i << 3));`
96			`show_tx_bd(i, i);`
97			`show_buffer(REG32(ETH_BD_BASE + (i << 3) + 4), REG32(ETH_BD_BASE + (i << 3)) >> 16);`
98			`printf ("\n");`
99			`}`
100			`if (REG32(ETH_BD_BASE + (i << 3)) & ETH_TX_BD_WRAP)`
101			`return;`
102			`}`
103			`}`
104
105			`void show_phy_reg (unsigned long start_addr, unsigned long stop_addr)`
106			`{`
107
108			`unsigned long addr;`
109
110			`if (start_addr == stop_addr)`
111			`{`
112			`printf ("\nSet MII RGAD ADDRESS to %08x", start_addr);`
113			`printf ("\nMII Command = Read Status\n");`
114			`}`
115
116			`for (addr = start_addr; addr <= stop_addr; addr++)`
117			`{`
118			`REG32(ETH_REG_BASE + ETH_MIIADDRESS) = addr<<8;`
119			`REG32(ETH_REG_BASE + ETH_MIICOMMAND) = ETH_MIICOMMAND_RSTAT;`
120
121			`printf ("PHY %04x", REG32(ETH_REG_BASE + ETH_MIIADDRESS) & 0x1f);`
122			`printf (", addr %04x", REG32(ETH_REG_BASE + ETH_MIIADDRESS) >> 8);`
123			`printf (": %08x\n", REG32(ETH_REG_BASE + ETH_MIIRX_DATA));`
124			`}`
125			`}`
126
127			`void set_phy_reg (unsigned long addr, unsigned long val)`
128			`{`
129			`printf ("\nSet MII RGAD ADDRESS to %08x", addr);`
130
131			`REG32(ETH_REG_BASE + ETH_MIIADDRESS) = addr<<8;`
132
133			`printf ("\nMII Command = Write Control Data\n");`
134			`REG32(ETH_REG_BASE + ETH_MIICOMMAND) = ETH_MIICOMMAND_WCTRLDATA;`
135
136			`REG32(ETH_REG_BASE + ETH_MIITX_DATA) = val;`
137
138			`show_phy_reg(addr, addr);`
139			`}`
140
141			`void send_packet (unsigned long len, unsigned long start_data, int num_of_packets)`
142			`{`
143			`unsigned long i, TxBD;`
144
145			`while (num_of_packets--) {`
146			`unsigned long data = (unsigned long )eth_get_tx_buf ();`
147
148			`/* Set dest & src address */`
149			`*data++ = dest_mac_addr[0] << 24 \|`
150			`dest_mac_addr[1] << 16 \|`
151			`dest_mac_addr[2] << 8 \|`
152			`dest_mac_addr[3] << 0;`
153
154			`*data++ = dest_mac_addr[4] << 24 \|`
155			`dest_mac_addr[5] << 16 \|`
156			`ETH_MACADDR0 << 8 \|`
157			`ETH_MACADDR1 << 0;`
158
159			`*data++ = ETH_MACADDR2 << 24 \|`
160			`ETH_MACADDR3 << 16 \|`
161			`ETH_MACADDR4 << 8 \|`
162			`ETH_MACADDR5 << 0;`
163
164			`/* Write data to buffer */`
165			`for(i = 12; i < len; i += 4)`
166			`*data++ = (i + start_data - 12) << 24 \| (i + start_data + 1 - 12) << 16 \|`
167			`(i + start_data + 2 - 12) << 8 \| (i + start_data + 3 - 12);`
168
169			`eth_send (data, len);`
170			`printf (".");`
171			`}`
172			`}`
173
174			`int eth_init_cmd (int argc, char *argv[])`
175			`{`
176			`if (argc) return -1;`
177			`eth_init (0);`
178			`return 0;`
179			`}`
180
181			`int show_txbd_cmd (int argc, char *argv[])`
182			`{`
183			`int cnt, i;`
184			`int start, max;`
185
186			`if (argc == 1) show_tx_bd (strtoul (argv[0]), strtoul (argv[0]));`
187			`else if (argc == 2) show_tx_bd (strtoul (argv[0]), strtoul (argv[1]));`
188			`else show_tx_bd (0, 63);`
189			`return 0;`
190			`}`
191
192			`int show_rxbd_cmd (int argc, char *argv[])`
193			`{`
194			`if (argc == 1) show_rx_bd (strtoul (argv[0]), strtoul (argv[0]));`
195			`else if (argc == 2) show_rx_bd (strtoul (argv[0]), strtoul (argv[1]));`
196			`else show_rx_bd (0, 63);`
197			`return 0;`
198			`}`
199
200			`int send_packet_cmd (int argc, char *argv[])`
201			`{`
202			`if (argc == 1) send_packet(strtoul (argv[0]), 31, 1);`
203			`else if (argc == 2) send_packet(strtoul (argv[0]), strtoul (argv[1]), 1);`
204			`else if (argc == 3) send_packet(strtoul (argv[0]), strtoul (argv[1]), strtoul (argv[2]));`
205			`else return -1;`
206			`return 0;`
207			`}`
208
209			`int set_dest_addr_cmd (int argc, char *argv[])`
210			`{`
211			`if (argc == 3) {`
212			`dest_mac_addr[0] = (strtoul (argv[0]) >> 8) & 0xff;`
213			`dest_mac_addr[1] = (strtoul (argv[0]) >> 0) & 0xff;`
214			`dest_mac_addr[2] = (strtoul (argv[1]) >> 8) & 0xff;`
215			`dest_mac_addr[3] = (strtoul (argv[1]) >> 0) & 0xff;`
216			`dest_mac_addr[4] = (strtoul (argv[2]) >> 8) & 0xff;`
217			`dest_mac_addr[5] = (strtoul (argv[2]) >> 0) & 0xff;`
218			`} else return -1;`
219			`return 0;`
220			`}`
221
222			`int init_txbd_pool_cmd (int argc, char *argv[])`
223			`{`
224			`if (argc == 1) init_tx_bd_pool(strtoul (argv[0]));`
225			`else return -1;`
226			`return 0;`
227			`}`
228
229			`int init_rxbd_pool_cmd (int argc, char *argv[])`
230			`{`
231			`if (argc == 1) init_rx_bd_pool(strtoul (argv[0]));`
232			`else return -1;`
233			`return 0;`
234			`}`
235
236			`int show_phy_reg_cmd (int argc, char *argv[])`
237			`{`
238			`if (argc == 1) show_phy_reg(strtoul (argv[0]), strtoul (argv[0]));`
239			`else if (argc == 2) show_phy_reg(strtoul (argv[0]), strtoul (argv[1]));`
240			`else show_phy_reg(0, 30);`
241			`return 0;`
242			`}`
243
244			`int set_phy_reg_cmd (int argc, char *argv[])`
245			`{`
246			`if (argc == 2) set_phy_reg(strtoul (argv[0]), strtoul (argv[1]));`
247			`else return -1;`
248			`return 0;`
249			`}`
250
251			`int show_mac_regs_cmd (int argc, char *argv[])`
252			`{`
253			`if (argc) return -1;`
254			`printf ("\n %08x", ETH_REG_BASE + ETH_MODER);`
255			`printf (" MODER: %08x",REG32(ETH_REG_BASE + ETH_MODER));`
256
257			`printf ("\n %08x", ETH_REG_BASE + ETH_INT);`
258			`printf (" INT: %08x", REG32(ETH_REG_BASE + ETH_INT));`
259
260			`printf ("\n %08x", ETH_REG_BASE + ETH_INT_MASK);`
261			`printf (" INT_MASK: %08x", REG32(ETH_REG_BASE + ETH_INT_MASK));`
262
263			`printf ("\n %08x", ETH_REG_BASE + ETH_IPGT);`
264			`printf (" IPGT: %08x", REG32(ETH_REG_BASE + ETH_IPGT));`
265
266			`printf ("\n %08x", ETH_REG_BASE + ETH_IPGR1);`
267			`printf (" IPGR1: %08x", REG32(ETH_REG_BASE + ETH_IPGR1));`
268
269			`printf ("\n %08x", ETH_REG_BASE + ETH_IPGR2);`
270			`printf (" IPGR2: %08x", REG32(ETH_REG_BASE + ETH_IPGR2));`
271
272			`printf ("\n %08x", ETH_REG_BASE + ETH_PACKETLEN);`
273			`printf (" PACKETLEN: %08x", REG32(ETH_REG_BASE + ETH_PACKETLEN));`
274
275			`printf ("\n %08x", ETH_REG_BASE + ETH_COLLCONF);`
276			`printf (" COLLCONF: %08x", REG32(ETH_REG_BASE + ETH_COLLCONF));`
277
278			`printf ("\n %08x", ETH_REG_BASE + ETH_RXBD_NUM);`
279			`printf (" RX_BD_NUM: %08x", REG32(ETH_REG_BASE + ETH_RXBD_NUM));`
280
281			`printf ("\n %08x", ETH_REG_BASE + ETH_CTRLMODER);`
282			`printf (" CTRLMODER: %08x", REG32(ETH_REG_BASE + ETH_CTRLMODER));`
283
284			`printf ("\n %08x", ETH_REG_BASE + ETH_MIIMODER);`
285			`printf (" MIIMODER: %08x", REG32(ETH_REG_BASE + ETH_MIIMODER));`
286
287			`printf ("\n %08x", ETH_REG_BASE + ETH_MIICOMMAND);`
288			`printf (" MIICOMMAND: %08x", REG32(ETH_REG_BASE + ETH_MIICOMMAND));`
289
290			`printf ("\n %08x", ETH_REG_BASE + ETH_MIIADDRESS);`
291			`printf (" MIIADDRESS: %08x", REG32(ETH_REG_BASE + ETH_MIIADDRESS));`
292
293			`printf ("\n %08x", ETH_REG_BASE + ETH_MIITX_DATA);`
294			`printf (" MIITX_DATA: %08x", REG32(ETH_REG_BASE + ETH_MIITX_DATA));`
295
296			`printf ("\n %08x", ETH_REG_BASE + ETH_MIIRX_DATA);`
297			`printf (" MIIRX_DATA: %08x", REG32(ETH_REG_BASE + ETH_MIIRX_DATA));`
298
299			`printf ("\n %08x", ETH_REG_BASE + ETH_MIISTATUS);`
300			`printf (" MIISTATUS: %08x", REG32(ETH_REG_BASE + ETH_MIISTATUS));`
301
302			`printf ("\n %08x", ETH_REG_BASE + ETH_MAC_ADDR0);`
303			`printf (" MAC_ADDR0: %08x", REG32(ETH_REG_BASE + ETH_MAC_ADDR0));`
304
305			`printf ("\n %08x", ETH_REG_BASE + ETH_MAC_ADDR1);`
306			`printf (" MAC_ADDR1: %08x", REG32(ETH_REG_BASE + ETH_MAC_ADDR1));`
307
308			`printf ("\n %08x", ETH_REG_BASE + ETH_HASH_ADDR0);`
309			`printf (" ETH_HASH_ADDR0: %08x", REG32(ETH_REG_BASE + ETH_HASH_ADDR0));`
310
311			`printf ("\n %08x", ETH_REG_BASE + ETH_HASH_ADDR1);`
312			`printf (" ETH_HASH_ADDR1: %08x", REG32(ETH_REG_BASE + ETH_HASH_ADDR1));`
313
314			`printf ("\n");`
315			`return 0;`
316			`}`
317
318			`int eth_int_enable_cmd (int argc, char *argv[])`
319			`{`
320			`if (argc) return -1;`
321			`eth_int_enable ();`
322			`return 0;`
323			`}`
324			`int show_rx_buffs_cmd (int argc, char *argv[])`
325			`{`
326			`if (argc == 0) show_rx_buffs(63, 0);`
327			`else if (argc == 1) show_rx_buffs(63, 1);`
328			`else return -1;`
329			`return 0;`
330			`}`
331
332			`int show_tx_buffs_cmd (int argc, char *argv[])`
333			`{`
334			`if (argc == 0) show_tx_buffs(63);`
335			`else return -1;`
336			`return 0;`
337			`}`
338
339			`#endif`
340			`void module_eth_init ()`
341			`{`
342			`#if 0`
343			`register_command ("eth_init", "", "init ethernet", eth_init_cmd);`
344			`register_command ("show_txbd", "[<start BD>] [<max>]", "show Tx buffer desc", show_txbd_cmd);`
345			`register_command ("show_rxbd", "[<start BD>] [<max>]", "show Rx buffer desc", show_rxbd_cmd);`
346			`register_command ("send_packet", "<length> [<start data>] [<num_of_packets>]", "create & send packet(s)", send_packet_cmd);`
347			`register_command ("set_dest_addr", "<addrhi> <addrmid> <addrlo>", "set destination address (for send_packet)", set_dest_addr_cmd);`
348			`register_command ("init_txbd_pool", "<max>", "initialize Tx buffer descriptors", init_txbd_pool_cmd);`
349			`register_command ("init_rxbd_pool", "<max>", "initialize Rx buffer descriptors", init_rxbd_pool_cmd);`
350			`register_command ("show_phy_reg", "[<start_addr>] [<end addr>]", "show PHY registers", show_phy_reg_cmd);`
351			`register_command ("set_phy_reg", "<addr> <value>", "set PHY register", set_phy_reg_cmd);`
352			`register_command ("show_mac_regs", "", "show all MAC registers", show_mac_regs_cmd);`
353			`register_command ("eth_int_enable", "", "enable ethernet interrupt", eth_int_enable_cmd);`
354			`register_command ("show_rx_buffs", "[<show_all>]", "show receive buffers (optional arg will also show empty buffers)", show_rx_buffs_cmd);`
355			`register_command ("show_tx_buffs", "", "show transmit buffers", show_rx_buffs_cmd);`
356			`/* Initialize controller */`
357			`/* eth_init();*/`
358			`/* printf ("Ethernet not initialized (run eth_init command)\n");*/`
359			`/* init_rx_bd_pool(0); */`
360			`/* init_tx_bd_pool(3);*/`
361			`#endif`
362			`}`