OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [orpmon/] [drivers/] [eth.c] - Blame information for rev 809

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 809 simons
#include "common.h"
2
#include "support.h"
3
#include "board.h"
4
#include "uart.h"
5
#include "eth.h"
6
#include "spr_defs.h"
7
 
8
extern int printf (const char *fmt, ...);
9
extern void lolev_ie(void);
10
extern void lolev_idis(void);
11
 
12
int tx_next;  /* Next buffer to be given to the user */
13
int tx_last;  /* Next buffer to be checked if packet sent */
14
int tx_full;
15
int rx_next;  /* Next buffer to be checked for new packet and given to the user */
16
void (*receive)(void *add, int len); /* Pointer to function to be called
17
                                        when frame is received */
18
 
19
void init_tx_bd_pool(void)
20
{
21
  eth_bd  *bd;
22
  int i;
23
 
24
  bd = (eth_bd *)ETH_BD_BASE;
25
 
26
  for(i = 0; i < ETH_TXBD_NUM; i++){
27
 
28
    /* Set Tx BD status */
29
    bd[i].status = ETH_TX_BD_PAD | ETH_TX_BD_CRC | ETH_RX_BD_IRQ;
30
 
31
    /* Initialize Tx buffer pointer */
32
    bd[i].addr = ETH_DATA_BASE + i * ETH_MAXBUF_LEN;
33
  }
34
 
35
  bd[i-1].status |= ETH_TX_BD_WRAP; // Last Tx BD - Wrap
36
}
37
 
38
void init_rx_bd_pool(void)
39
{
40
  eth_bd  *bd;
41
  int i;
42
 
43
  bd = (eth_bd *)ETH_BD_BASE + ETH_TXBD_NUM;
44
 
45
  for(i = 0; i < ETH_RXBD_NUM; i++){
46
 
47
    /* Set Tx BD status */
48
    bd[i].status = ETH_RX_BD_EMPTY | ETH_RX_BD_IRQ;
49
 
50
    /* Initialize Tx buffer pointer */
51
    bd[i].addr = ETH_DATA_BASE + (ETH_TXBD_NUM + i) * ETH_MAXBUF_LEN;
52
  }
53
 
54
  bd[i-1].status |= ETH_TX_BD_WRAP; // Last Rx BD - Wrap
55
}
56
 
57
void eth_init (void (*rec)(volatile unsigned char *, int))
58
{
59
 
60
  /* Reset ethernet core */
61
  REG32(ETH_REG_BASE + ETH_MODER) = ETH_MODER_RST;    /* Reset ON */
62
  REG32(ETH_REG_BASE + ETH_MODER) &= ~ETH_MODER_RST;  /* Reset OFF */
63
 
64
  /* Setting TX BD number */
65
  REG32(ETH_REG_BASE + ETH_TX_BD_NUM) = ETH_TXBD_NUM << 1;
66
 
67
  /* Set min/max packet length */
68
  REG32(ETH_REG_BASE + ETH_PACKETLEN) = 0x003c0600;
69
 
70
  /* Set IPGT register to recomended value */
71
  REG32(ETH_REG_BASE + ETH_IPGT) =  0x00000012;
72
 
73
  /* Set IPGR1 register to recomended value */
74
  REG32(ETH_REG_BASE + ETH_IPGR1) =  0x0000000c;
75
 
76
  /* Set IPGR2 register to recomended value */
77
  REG32(ETH_REG_BASE + ETH_IPGR2) =  0x00000012;
78
 
79
  /* Set COLLCONF register to recomended value */
80
  REG32(ETH_REG_BASE + ETH_COLLCONF) =  0x0000003f;
81
 
82
#if 0
83
  REG32(ETH_REG_BASE + ETH_CTRLMODER) = OETH_CTRLMODER_TXFLOW | OETH_CTRLMODER_RXFLOW;
84
#else
85
  REG32(ETH_REG_BASE + ETH_CTRLMODER) = 0;
86
#endif
87
 
88
  /* Initialize RX and TX buffer descriptors */
89
  init_rx_bd_pool();
90
  init_tx_bd_pool();
91
 
92
  /* Initialize tx pointers */
93
  tx_next = 0;
94
  tx_last = 0;
95
  tx_full = 0;
96
 
97
  /* Initialize rx pointers */
98
  rx_next = 0;
99
  receive = rec;
100
 
101
  /* Set local MAC address */
102
  REG32(ETH_REG_BASE + ETH_MAC_ADDR1) = ETH_MACADDR0 << 8 |
103
            ETH_MACADDR1;
104
  REG32(ETH_REG_BASE + ETH_MAC_ADDR0) = ETH_MACADDR2 << 24 |
105
            ETH_MACADDR3 << 16 |
106
            ETH_MACADDR4 << 8 |
107
            ETH_MACADDR5;
108
 
109
  /* Clear all pending interrupts */
110
  REG32(ETH_REG_BASE + ETH_INT) = 0xffffffff;
111
 
112
  /* Promisc, IFG, CRCEn */
113
  REG32(ETH_REG_BASE + ETH_MODER) |= ETH_MODER_PAD | ETH_MODER_IFG | ETH_MODER_CRCEN;
114
 
115
  /* Enable interrupt sources */
116
#if 0
117
  regs->int_mask = ETH_INT_MASK_TXB        |
118
                   ETH_INT_MASK_TXE        |
119
                   ETH_INT_MASK_RXF        |
120
                   ETH_INT_MASK_RXE        |
121
                   ETH_INT_MASK_BUSY       |
122
                   ETH_INT_MASK_TXC        |
123
                   ETH_INT_MASK_RXC;
124
#endif
125
 
126
  /* Enable receiver and transmiter */
127
  REG32(ETH_REG_BASE + ETH_MODER) |= ETH_MODER_RXEN | ETH_MODER_TXEN;
128
 
129
}
130
 
131
/* Returns pointer to next free buffer; NULL if none available */
132
void *eth_get_tx_buf ()
133
{
134
  eth_bd  *bd;
135
  unsigned long add;
136
 
137
  if(tx_full)
138
    return (void *)0;
139
 
140
  bd = (eth_bd *)ETH_BD_BASE;
141
 
142
  if(bd[tx_next].status & ETH_TX_BD_READY)
143
    return (void *)0;
144
 
145
  add = bd[tx_next].addr;
146
 
147
  tx_next = (tx_next + 1) & ETH_TXBD_NUM_MASK;
148
 
149
  if(tx_next == tx_last)
150
    tx_full = 1;
151
 
152
  return (void *)add;
153
}
154
 
155
/* Send a packet at address */
156
void eth_send (void *buf, unsigned long len)
157
{
158
  eth_bd  *bd;
159
 
160
  bd = (eth_bd *)ETH_BD_BASE;
161
 
162
  bd[tx_last].addr = (unsigned long)buf;
163
 
164
  bd[tx_last].status &= ~ETH_TX_BD_STATS;
165
  bd[tx_last].status |= ETH_TX_BD_READY;
166
 
167
  tx_last = (tx_last + 1) & ETH_TXBD_NUM_MASK;
168
  tx_full = 0;
169
}
170
 
171
/* Waits for packet and pass it to the upper layers */
172
unsigned long eth_rx (void)
173
{
174
  eth_bd  *bd;
175
  unsigned long len = 0;
176
 
177
  bd = (eth_bd *)ETH_BD_BASE + ETH_TXBD_NUM;
178
 
179
  while(1) {
180
 
181
    int bad = 0;
182
 
183
    if(bd[rx_next].status & ETH_RX_BD_EMPTY)
184
      return len;
185
 
186
    if(bd[rx_next].status & ETH_RX_BD_OVERRUN) {
187
      printf("eth rx: ETH_RX_BD_OVERRUN\n");
188
      bad = 1;
189
    }
190
    if(bd[rx_next].status & ETH_RX_BD_INVSIMB) {
191
      printf("eth rx: ETH_RX_BD_INVSIMB\n");
192
      bad = 1;
193
    }
194
    if(bd[rx_next].status & ETH_RX_BD_DRIBBLE) {
195
      printf("eth rx: ETH_RX_BD_DRIBBLE\n");
196
      bad = 1;
197
    }
198
    if(bd[rx_next].status & ETH_RX_BD_TOOLONG) {
199
      printf("eth rx: ETH_RX_BD_TOOLONG\n");
200
      bad = 1;
201
    }
202
    if(bd[rx_next].status & ETH_RX_BD_SHORT) {
203
      printf("eth rx: ETH_RX_BD_SHORT\n");
204
      bad = 1;
205
    }
206
    if(bd[rx_next].status & ETH_RX_BD_CRCERR) {
207
      printf("eth rx: ETH_RX_BD_CRCERR\n");
208
      bad = 1;
209
    }
210
    if(bd[rx_next].status & ETH_RX_BD_LATECOL) {
211
      printf("eth rx: ETH_RX_BD_LATECOL\n");
212
      bad = 1;
213
    }
214
 
215
    if(!bad) {
216
      receive((void *)bd[rx_next].addr, bd[rx_next].len);
217
      len += bd[rx_next].len;
218
    }
219
 
220
    bd[rx_next].status &= ~ETH_RX_BD_STATS;
221
    bd[rx_next].status |= ETH_RX_BD_EMPTY;
222
 
223
    rx_next = (rx_next + 1) & ETH_RXBD_NUM_MASK;
224
  }
225
}
226
 
227
void eth_int_enable(void)
228
{
229
  REG32(ETH_REG_BASE + ETH_INT_MASK) =  ETH_INT_MASK_TXB        |
230
                                        ETH_INT_MASK_TXE        |
231
                                        ETH_INT_MASK_RXF        |
232
                                        ETH_INT_MASK_RXE        |
233
                                        ETH_INT_MASK_BUSY       |
234
                                        ETH_INT_MASK_TXC        |
235
                                        ETH_INT_MASK_RXC;
236
}
237
 
238
void eth_halt(void)
239
{
240
  /* Enable receiver and transmiter */
241
  REG32(ETH_REG_BASE + ETH_MODER) &= ~(ETH_MODER_RXEN | ETH_MODER_TXEN);
242
}
243
 
244
void eth_int(void)
245
{
246
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.