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[/] [or1k/] [trunk/] [orpmon/] [drivers/] [eth.c] - Blame information for rev 809

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1 809 simons 
#include "common.h"
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#include "support.h"
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#include "board.h"
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#include "uart.h"
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#include "eth.h"
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#include "spr_defs.h"
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extern int printf (const char *fmt, ...);
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extern void lolev_ie(void);
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extern void lolev_idis(void);
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int tx_next;  /* Next buffer to be given to the user */
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int tx_last;  /* Next buffer to be checked if packet sent */
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int tx_full;
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int rx_next;  /* Next buffer to be checked for new packet and given to the user */
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void (*receive)(void *add, int len); /* Pointer to function to be called
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                                        when frame is received */
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void init_tx_bd_pool(void)
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{
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  eth_bd  *bd;
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  int i;
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  bd = (eth_bd *)ETH_BD_BASE;
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  for(i = 0; i < ETH_TXBD_NUM; i++){
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    /* Set Tx BD status */
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    bd[i].status = ETH_TX_BD_PAD | ETH_TX_BD_CRC | ETH_RX_BD_IRQ;
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    /* Initialize Tx buffer pointer */
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    bd[i].addr = ETH_DATA_BASE + i * ETH_MAXBUF_LEN;
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  }
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  bd[i-1].status |= ETH_TX_BD_WRAP; // Last Tx BD - Wrap
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}
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void init_rx_bd_pool(void)
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{
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  eth_bd  *bd;
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  int i;
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  bd = (eth_bd *)ETH_BD_BASE + ETH_TXBD_NUM;
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  for(i = 0; i < ETH_RXBD_NUM; i++){
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    /* Set Tx BD status */
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    bd[i].status = ETH_RX_BD_EMPTY | ETH_RX_BD_IRQ;
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    /* Initialize Tx buffer pointer */
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    bd[i].addr = ETH_DATA_BASE + (ETH_TXBD_NUM + i) * ETH_MAXBUF_LEN;
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  }
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  bd[i-1].status |= ETH_TX_BD_WRAP; // Last Rx BD - Wrap
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}
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void eth_init (void (*rec)(volatile unsigned char *, int))
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{
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  /* Reset ethernet core */
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  REG32(ETH_REG_BASE + ETH_MODER) = ETH_MODER_RST;    /* Reset ON */
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  REG32(ETH_REG_BASE + ETH_MODER) &= ~ETH_MODER_RST;  /* Reset OFF */
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  /* Setting TX BD number */
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  REG32(ETH_REG_BASE + ETH_TX_BD_NUM) = ETH_TXBD_NUM << 1;
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  /* Set min/max packet length */
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  REG32(ETH_REG_BASE + ETH_PACKETLEN) = 0x003c0600;
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  /* Set IPGT register to recomended value */
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  REG32(ETH_REG_BASE + ETH_IPGT) =  0x00000012;
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  /* Set IPGR1 register to recomended value */
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  REG32(ETH_REG_BASE + ETH_IPGR1) =  0x0000000c;
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  /* Set IPGR2 register to recomended value */
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  REG32(ETH_REG_BASE + ETH_IPGR2) =  0x00000012;
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  /* Set COLLCONF register to recomended value */
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  REG32(ETH_REG_BASE + ETH_COLLCONF) =  0x0000003f;
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#if 0
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  REG32(ETH_REG_BASE + ETH_CTRLMODER) = OETH_CTRLMODER_TXFLOW | OETH_CTRLMODER_RXFLOW;
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#else
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  REG32(ETH_REG_BASE + ETH_CTRLMODER) = 0;
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#endif
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  /* Initialize RX and TX buffer descriptors */
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  init_rx_bd_pool();
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  init_tx_bd_pool();
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  /* Initialize tx pointers */
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  tx_next = 0;
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  tx_last = 0;
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  tx_full = 0;
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  /* Initialize rx pointers */
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  rx_next = 0;
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  receive = rec;
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  /* Set local MAC address */
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  REG32(ETH_REG_BASE + ETH_MAC_ADDR1) = ETH_MACADDR0 << 8 |
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            ETH_MACADDR1;
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  REG32(ETH_REG_BASE + ETH_MAC_ADDR0) = ETH_MACADDR2 << 24 |
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            ETH_MACADDR3 << 16 |
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            ETH_MACADDR4 << 8 |
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            ETH_MACADDR5;
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  /* Clear all pending interrupts */
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  REG32(ETH_REG_BASE + ETH_INT) = 0xffffffff;
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  /* Promisc, IFG, CRCEn */
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  REG32(ETH_REG_BASE + ETH_MODER) |= ETH_MODER_PAD | ETH_MODER_IFG | ETH_MODER_CRCEN;
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  /* Enable interrupt sources */
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#if 0
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  regs->int_mask = ETH_INT_MASK_TXB        |
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                   ETH_INT_MASK_TXE        |
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                   ETH_INT_MASK_RXF        |
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                   ETH_INT_MASK_RXE        |
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                   ETH_INT_MASK_BUSY       |
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                   ETH_INT_MASK_TXC        |
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                   ETH_INT_MASK_RXC;
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#endif
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  /* Enable receiver and transmiter */
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  REG32(ETH_REG_BASE + ETH_MODER) |= ETH_MODER_RXEN | ETH_MODER_TXEN;
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129 
}
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/* Returns pointer to next free buffer; NULL if none available */
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void *eth_get_tx_buf ()
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{
134 
  eth_bd  *bd;
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  unsigned long add;
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137 
  if(tx_full)
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    return (void *)0;
139 
 
140 
  bd = (eth_bd *)ETH_BD_BASE;
141 
 
142 
  if(bd[tx_next].status & ETH_TX_BD_READY)
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    return (void *)0;
144 
 
145 
  add = bd[tx_next].addr;
146 
 
147 
  tx_next = (tx_next + 1) & ETH_TXBD_NUM_MASK;
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149 
  if(tx_next == tx_last)
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    tx_full = 1;
151 
 
152 
  return (void *)add;
153 
}
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155 
/* Send a packet at address */
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void eth_send (void *buf, unsigned long len)
157 
{
158 
  eth_bd  *bd;
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160 
  bd = (eth_bd *)ETH_BD_BASE;
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162 
  bd[tx_last].addr = (unsigned long)buf;
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164 
  bd[tx_last].status &= ~ETH_TX_BD_STATS;
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  bd[tx_last].status |= ETH_TX_BD_READY;
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167 
  tx_last = (tx_last + 1) & ETH_TXBD_NUM_MASK;
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  tx_full = 0;
169 
}
170 
 
171 
/* Waits for packet and pass it to the upper layers */
172 
unsigned long eth_rx (void)
173 
{
174 
  eth_bd  *bd;
175 
  unsigned long len = 0;
176 
 
177 
  bd = (eth_bd *)ETH_BD_BASE + ETH_TXBD_NUM;
178 
 
179 
  while(1) {
180 
 
181 
    int bad = 0;
182 
 
183 
    if(bd[rx_next].status & ETH_RX_BD_EMPTY)
184 
      return len;
185 
 
186 
    if(bd[rx_next].status & ETH_RX_BD_OVERRUN) {
187 
      printf("eth rx: ETH_RX_BD_OVERRUN\n");
188 
      bad = 1;
189 
    }
190 
    if(bd[rx_next].status & ETH_RX_BD_INVSIMB) {
191 
      printf("eth rx: ETH_RX_BD_INVSIMB\n");
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      bad = 1;
193 
    }
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    if(bd[rx_next].status & ETH_RX_BD_DRIBBLE) {
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      printf("eth rx: ETH_RX_BD_DRIBBLE\n");
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      bad = 1;
197 
    }
198 
    if(bd[rx_next].status & ETH_RX_BD_TOOLONG) {
199 
      printf("eth rx: ETH_RX_BD_TOOLONG\n");
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      bad = 1;
201 
    }
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    if(bd[rx_next].status & ETH_RX_BD_SHORT) {
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      printf("eth rx: ETH_RX_BD_SHORT\n");
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      bad = 1;
205 
    }
206 
    if(bd[rx_next].status & ETH_RX_BD_CRCERR) {
207 
      printf("eth rx: ETH_RX_BD_CRCERR\n");
208 
      bad = 1;
209 
    }
210 
    if(bd[rx_next].status & ETH_RX_BD_LATECOL) {
211 
      printf("eth rx: ETH_RX_BD_LATECOL\n");
212 
      bad = 1;
213 
    }
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215 
    if(!bad) {
216 
      receive((void *)bd[rx_next].addr, bd[rx_next].len);
217 
      len += bd[rx_next].len;
218 
    }
219 
 
220 
    bd[rx_next].status &= ~ETH_RX_BD_STATS;
221 
    bd[rx_next].status |= ETH_RX_BD_EMPTY;
222 
 
223 
    rx_next = (rx_next + 1) & ETH_RXBD_NUM_MASK;
224 
  }
225 
}
226 
 
227 
void eth_int_enable(void)
228 
{
229 
  REG32(ETH_REG_BASE + ETH_INT_MASK) =  ETH_INT_MASK_TXB        |
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                                        ETH_INT_MASK_TXE        |
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                                        ETH_INT_MASK_RXF        |
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                                        ETH_INT_MASK_RXE        |
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                                        ETH_INT_MASK_BUSY       |
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                                        ETH_INT_MASK_TXC        |
235 
                                        ETH_INT_MASK_RXC;
236 
}
237 
 
238 
void eth_halt(void)
239 
{
240 
  /* Enable receiver and transmiter */
241 
  REG32(ETH_REG_BASE + ETH_MODER) &= ~(ETH_MODER_RXEN | ETH_MODER_TXEN);
242 
}
243 
 
244 
void eth_int(void)
245 
{
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}

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