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/*
/////////////////////////////////////////////////////////////////////
////                                                             ////
////  Include file for OpenCores ATA Controller (OCIDEC)         ////
////                                                             ////
////  File    : oc_ata.h                                         ////
////  Function: c-include file                                   ////
////                                                             ////
////  Authors: Richard Herveille (rherveille@opencores)          ////
////           www.opencores.org                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2002 Richard Herveille                        ////
////                    rherveille@opencores.org                 ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
*/
 
/*
 * Definitions for the Opencores ATA Controller Core
 */
 
#ifndef __OC_ATA_H
#define __OC_ATA_H
 
 
#define ATA_DEBUG
 
 
#define MAX_ATA_COMMANDS  100
 
 
#ifndef REG32
#define REG32(adr) *((volatile unsigned int *)(adr))
#endif
 
/* --- Register definitions --- */
 
/* ----- Core Registers                                              */
#define ATA_CTRL  0x00         /* Control register                   */
#define ATA_STAT  0x04         /* Status register                    */
#define ATA_PCTR  0x08         /* PIO command timing register        */
#define ATA_PFTR0 0x0c         /* PIO Fast Timing register Device0   */
#define ATA_PFTR1 0x10         /* PIO Fast Timing register Device1   */
#define ATA_DTR0  0x14         /* DMA Timing register Device2        */
#define ATA_DTR1  0x18         /* DMA Timing register Device1        */
#define ATA_DTXB  0x3c         /* DMA Transmit buffer                */
#define ATA_RXB   0x3c         /* DMA Receive buffer                 */
 
/* ----- ATA Registers                                               */
#define ATA_ASR   0x78         /* Alternate Status Register      (R) */
#define ATA_CR    0x5c         /* Command Register               (W) */
#define ATA_CHR   0x54         /* Cylinder High Register       (R/W) */
#define ATA_CLR   0x50         /* Cylinder Low Register        (R/W) */
#define ATA_DR    0x40         /* Data Register                      */
#define ATA_DCR   0x78         /* Device Control Register        (W) */
#define ATA_DHR   0x58         /* Device/Head Register         (R/W) */
#define ATA_ERR   0x44         /* Error Register                 (R) */
#define ATA_FR    0x44         /* Features Register              (W) */
#define ATA_SCR   0x48         /* Sector Count Register        (R/W) */
#define ATA_SNR   0x4c         /* Sector Number Register       (R/W) */
#define ATA_SR    0x5c         /* Status Register                (R) */
#define ATA_DA    0x7c         /* Device Address Register        (R) */
             /* ATA/ATAPI-5 does not describe Device Status Register */
 
/* ----------------------------                                       */
/* ----- Bits definitions -----                                       */
/* ----------------------------                                       */
 
/* ----- Core Control register                                        */
                                /* bits 31-16 are reserved            */
#define ATA_DMA_EN  (0<<15)     /* DMAen, DMA enable bit              */
                                /* bit 14 is reserved                 */
#define ATA_DMA_WR  (1<<14)     /* DMA Write transaction              */
#define ATA_DMA_RD  (0<<14)     /* DMA Read transaction               */
                                /* bits 13-10 are reserved            */
#define ATA_BELEC1  (1<< 9)     /* Big-Little endian conversion       */
                                /* enable bit for Device1             */
#define ATA_BELEC0  (1<< 8)     /* Big-Little endian conversion       */
                                /* enable bit for Device0             */
#define ATA_IDE_EN  (1<< 7)     /* IDE core enable bit                */
#define ATA_FTE1    (1<< 6)     /* Device1 Fast PIO Timing Enable bit */
#define ATA_FTE0    (1<< 5)     /* Device0 Fast PIO Timing Enable bit */
#define ATA_PWPP    (1<< 4)     /* PIO Write Ping-Pong Enable bit     */
#define ATA_IORDY_FTE1 (1<< 3)  /* Device1 Fast PIO Timing IORDY      */
                                /* enable bit                         */
#define ATA_IORDY_FTE0 (1<< 2)  /* Device0 Fast PIO Timing IORDY      */
                                /* enable bit                         */
#define ATA_IORDY   (1<< 1)     /* PIO Command Timing IORDY enable bit*/
#define ATA_RST     (1<< 0)     /* ATA Reset bit                      */
 
/* ----- Core Status register                                         */
#define ATA_DEVID   0xf0000000  /* bits 31-28 Device-ID               */
#define ATA_REVNO   0x0f000000  /* bits 27-24 Revision number         */
                                /* bits 23-16 are reserved            */
#define ATA_DMA_TIP (1<<15)     /* DMA Transfer in progress           */
                                /* bits 14-10 are reserved            */
#define ATA_DRBE    (1<<10)     /* DMA Receive buffer empty           */
#define ATA_DTBF    (1<< 9)     /* DMA Transmit buffer full           */
#define ATA_DMARQ   (1<< 8)     /* DMARQ Line status                  */
#define ATA_PIO_TIP (1<< 7      /* PIO Transfer in progress           */
#define ATA_PWPPF   (1<< 6)     /* PIO write ping-pong full           */
                                /* bits 5-1 are reserved              */
#define ATA_IDEIS  (1<< 0)      /* IDE Interrupt status               */
 
 
/* -----  Core Timing registers                                       */
#define ATA_TEOC       24       /* End of cycle time          DMA/PIO */
#define ATA_T4         16       /* DIOW- data hold time           PIO */
#define ATA_T2          8       /* DIOR-/DIOW- pulse width        PIO */
#define ATA_TD          8       /* DIOR-/DIOW- pulse width        DMA */
#define ATA_T1          0       /* Address valid to DIOR-/DIOW-   PIO */
#define ATA_TM          0       /* CS[1:0]valid to DIOR-/DIOW-    DMA */
 
 
/* ----- ATA (Alternate) Status Register                              */
#define ATA_SR_BSY  0x80        /* Busy                               */
#define ATA_SR_DRDY 0x40        /* Device Ready                       */
#define ATA_SR_DF   0x20        /* Device Fault                       */
#define ATA_SR_DSC  0x10        /* Device Seek Complete               */
#define ATA_SR_DRQ  0x08        /* Data Request                       */
#define ATA_SR_COR  0x04        /* Corrected data (obsolete)          */
#define ATA_SR_IDX  0x02        /*                (obsolete)          */
#define ATA_SR_ERR  0x01        /* Error                              */
 
/* ----- ATA Device Control Register                                  */
                                /* bits 7-3 are reserved              */
#define ATA_DCR_RST 0x04        /* Software reset   (RST=1, reset)    */
#define ATA_DCR_IEN 0x02        /* Interrupt Enable (IEN=0, enabled)  */
                                /* always write a '0' to bit0         */
 
/* ----- ATA Device Address Register                                  */
/* All values in this register are one's complement (i.e. inverted)   */
#define ATA_DAR_WTG 0x40        /* Write Gate                         */
#define ATA_DAR_H   0x3c        /* Head Select                        */
#define ATA_DAR_DS1 0x02        /* Drive select 1                     */
#define ATA_DAR_DS0 0x01        /* Drive select 0                     */
 
/* ----- Device/Head Register                                         */
#define ATA_DHR_LBA 0x40        /* LBA/CHS mode ('1'=LBA mode)        */
#define ATA_DHR_DEV 0x10        /* Device       ('0'=dev0, '1'=dev1)  */
#define ATA_DHR_H   0x0f        /* Head Select                        */
 
/* ----- Error Register                                               */
#define ATA_ERR_BBK  0x80        /* Bad Block                          */
#define ATA_ERR_UNC  0x40       /* Uncorrectable Data Error           */
#define ATA_ERR_IDNF 0x10       /* ID Not Found                       */
#define ATA_ERR_ABT  0x04       /* Aborted Command                    */
#define ATA_ERR_TON  0x02       /* Track0 Not Found                   */
#define ATA_ERR_AMN  0x01       /* Address Mark Not Found             */
 
 
/* ----------------------------                                       */
/* ----- ATA commands     -----                                       */
/* ----------------------------                                       */
#define CFA_ERASE_SECTORS                0xC0
#define CFA_REQUEST_EXTENDED_ERROR_CODE  0x03
#define CFA_TRANSLATE_SECTOR             0x87
#define CFA_WRITE_MULTIPLE_WITHOUT_ERASE 0xCD
#define CFA_WRITE_SECTORS_WITHOUT_ERASE  0x38
#define CHECK_POWER_MODE                 0xE5
#define DEVICE_RESET                     0x08
#define DOWNLOAD_MICROCODE               0x92
#define EXECUTE_DEVICE_DIAGNOSTIC        0x90
#define FLUSH_CACHE                      0xE7
#define GET_MEDIA_STATUS                 0xDA
#define IDENTIFY_DEVICE                  0xEC
#define IDENTIFY_PACKET_DEVICE           0xA1
#define IDLE                             0xE3
#define IDLE_IMMEDIATE                   0xE1
#define INITIALIZE_DEVICE_PARAMETERS     0x91
#define MEDIA_EJECT                      0xED
#define MEDIA_LOCK                       0xDE
#define MEDIA_UNLOCK                     0xDF
#define NOP                              0x00
#define PACKET                           0xA0
#define READ_BUFFER                      0xE4
#define READ_DMA                         0xC8
#define READ_DMA_QUEUED                  0xC7
#define READ_MULTIPLE                    0xC4
#define READ_NATIVE_MAX_ADDRESS          0xF8
#define READ_SECTOR                      0x20
#define READ_SECTORS                     0x20
#define READ_VERIFY_SECTOR               0x40
#define READ_VERIFY_SECTORS              0x40
#define SECURITY_DISABLE_PASSWORD        0xF6
#define SECURITY_ERASE_PREPARE           0xF3
#define SECURITY_ERASE_UNIT              0xF4
#define SECURITY_FREEZE_LOCK             0xF5
#define SECURITY_SET_PASSWORD            0xF1
#define SECURITY_UNLOCK                  0xF2
#define SEEK                             0x70
#define SERVICE                          0xA2
#define SET_FEATURES                     0xEF
#define SET_MAX                          0xF9
#define SET_MULTIPLE_MODE                0xC6
#define SLEEP                            0xE6
#define SMART                            0xB0
#define STANDBY                          0xE2
#define STANDBY_IMMEDIATE                0xE0
#define WRITE_BUFFER                     0xE8
#define WRITE_DMA                        0xCA
#define WRITE_DMA_QUEUED                 0xCC
#define WRITE_MULTIPLE                   0xC5
#define WRITE_SECTOR                     0x30
#define WRITE_SECTORS                    0x30
 
 
/* SET_FEATURES has a number of sub-commands (in Features Register)   */
#define CFA_ENABLE_8BIT_PIO_TRANSFER_MODE       0x01
#define ENABLE_WRITE_CACHE                      0x02
#define SET_TRANSFER_MODE_SECTOR_COUNT_REG      0x03
#define ENABLE_ADVANCED_POWER_MANAGEMENT        0x05
#define ENABLE_POWERUP_IN_STANDBY_FEATURE_SET   0x06
#define POWERUP_IN_STANDBY_FEATURE_SET_SPINUP   0x07
#define CFA_ENABLE_POWER_MODE1                  0x0A
#define DISABLE_MEDIA_STATUS_NOTIFICATION       0x31
#define DISABLE_READ_LOOKAHEAD                  0x55
#define ENABLE_RELEASE_INTERRUPT                0x5D
#define ENABLE_SERVICE_INTERRUPT                0x5E
#define DISABLE_REVERTING_TO_POWERON_DEFAULTS   0x66
#define CFA_DISABLE_8BIT_PIO_TRANSFER_MODE      0x81
#define DISABLE_WRITE_CACHE                     0x82
#define DISABLE_ADVANCED_POWER_MANAGEMENT       0x85
#define DISABLE_POWERUP_IN_STANDBY_FEATURE_SET  0x86
#define CFA_DISABLE_POWER_MODE1                 0x8A
#define ENABLE_MEDIA_STATUS_NOTIFICATION        0x95
#define ENABLE_READ_LOOKAHEAD_FEATURE           0xAA
#define ENABLE_REVERTING_TO_POWERON_DEFAULTS    0xCC
#define DISABLE_RELEASE_INTERRUPT               0xDD
#define DISABLE_SERVICE_INTERRUPT               0xDE
 
/* SET_MAX has a number of sub-commands (in Features Register)        */
#define SET_MAX_ADDRESS                         0x00
#define SET_MAX_SET_PASSWORD                    0x01
#define SET_MAX_LOCK                            0x02
#define SET_MAX_UNLOCK                          0x03
#define SET_MAX_FREEZE_LOCK                     0x04
 
/* SET_MAX has a number of sub-commands (in Features Register)        */
#define SMART_READ_DATA                         0xD0
#define SMART_ATTRIBITE_AUTOSAVE                0xD1
#define SMART_SAVE_ATTRIBUTE_VALUES             0xD3
#define SMART_EXECUTE_OFFLINE_IMMEDIATE         0xD4
#define SMART_READ_LOG                          0xD5
#define SMART_WRITE_LOG                         0xD6
#define SMART_ENABLE_OPERATIONS                 0xD8
#define SMART_DISABLE_OPERATIONS                0xD9
#define SMART_RETURN_STATUS                     0xDA
 
/* ----------------------------                                       */
/* ----- Structs          -----                                       */
/* ----------------------------                                       */
 
/* ----------------------------                                       */
/* ----- Macros           -----                                       */
/* ----------------------------                                       */
 
#define ata_astatus(base)      (REG32(base + ATA_ASR))
#define ata_status(base)       (REG32(base + ATA_SR))
#define ata_error(base)        (REG32(base + ATA_ERR))
 
#define ata_dev_busy(base)     (ata_astatus(base) & ATA_SR_BSY)
#define ata_dev_cmdrdy(base)   (ata_astatus(base) & (~ATA_SR_BSY & ATA_SR_DRDY))
#define ata_dev_datrdy(base)   (ata_astatus(base) & ATA_SR_DRQ)
 
/* ----------------------------                                       */
/* ----- Prototypes       -----                                       */
/* ----------------------------                                       */
void module_ata_init (void);
int atabug(int argc, char **argv);
int atabug_exit(int argc, char **argv);
int atabug_help(int argc, char **argv);
void register_ata_command (const char *name, const char *params, const char *help, int (*func)(int argc, char *argv[]));
int ata_mon_command(void);
int execute_ata_command(char *pstr, int argc, char **argv);
 
int ata_dump_device_regs_cmd(int argc, char **argv);
int ata_dump_host_regs_cmd(int argc, char **argv);
int ata_enable_cmd(int argc, char **argv);
int ata_exec_cmd_cmd(int argc, char **argv);
int ata_identify_device_cmd(int argc, char **argv);
int ata_read_sector_cmd(int argc, char **argv);
int ata_reset_cmd(int argc, char **argv);
int ata_select_device_cmd(int argc, char **argv);
 
unsigned char atabug_dump_data(unsigned short *buffer, int cnt);
 
 
#endif

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[/] [or1k/] [trunk/] [orpmon/] [include/] [ata.h] - Blame information for rev 878

Line No.	Rev	Author	Line
1	878	rherveille	`/*`
2			`/////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// Include file for OpenCores ATA Controller (OCIDEC) ////`
5			`//// ////`
6			`//// File : oc_ata.h ////`
7			`//// Function: c-include file ////`
8			`//// ////`
9			`//// Authors: Richard Herveille (rherveille@opencores) ////`
10			`//// www.opencores.org ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2002 Richard Herveille ////`
15			`//// rherveille@opencores.org ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer.////`
21			`//// ////`
22			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
23			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
24			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
25			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
26			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
27			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
28			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
29			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
30			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
31			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
32			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
33			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
34			`//// POSSIBILITY OF SUCH DAMAGE. ////`
35			`//// ////`
36			`/////////////////////////////////////////////////////////////////////`
37			`*/`
38
39			`/*`
40			`* Definitions for the Opencores ATA Controller Core`
41			`*/`
42
43			`#ifndef __OC_ATA_H`
44			`#define __OC_ATA_H`
45
46
47			`#define ATA_DEBUG`
48
49
50			`#define MAX_ATA_COMMANDS 100`
51
52
53			`#ifndef REG32`
54			`#define REG32(adr) ((volatile unsigned int )(adr))`
55			`#endif`
56
57			`/* --- Register definitions --- */`
58
59			`/* ----- Core Registers */`
60			`#define ATA_CTRL 0x00 /* Control register */`
61			`#define ATA_STAT 0x04 /* Status register */`
62			`#define ATA_PCTR 0x08 /* PIO command timing register */`
63			`#define ATA_PFTR0 0x0c /* PIO Fast Timing register Device0 */`
64			`#define ATA_PFTR1 0x10 /* PIO Fast Timing register Device1 */`
65			`#define ATA_DTR0 0x14 /* DMA Timing register Device2 */`
66			`#define ATA_DTR1 0x18 /* DMA Timing register Device1 */`
67			`#define ATA_DTXB 0x3c /* DMA Transmit buffer */`
68			`#define ATA_RXB 0x3c /* DMA Receive buffer */`
69
70			`/* ----- ATA Registers */`
71			`#define ATA_ASR 0x78 /* Alternate Status Register (R) */`
72			`#define ATA_CR 0x5c /* Command Register (W) */`
73			`#define ATA_CHR 0x54 /* Cylinder High Register (R/W) */`
74			`#define ATA_CLR 0x50 /* Cylinder Low Register (R/W) */`
75			`#define ATA_DR 0x40 /* Data Register */`
76			`#define ATA_DCR 0x78 /* Device Control Register (W) */`
77			`#define ATA_DHR 0x58 /* Device/Head Register (R/W) */`
78			`#define ATA_ERR 0x44 /* Error Register (R) */`
79			`#define ATA_FR 0x44 /* Features Register (W) */`
80			`#define ATA_SCR 0x48 /* Sector Count Register (R/W) */`
81			`#define ATA_SNR 0x4c /* Sector Number Register (R/W) */`
82			`#define ATA_SR 0x5c /* Status Register (R) */`
83			`#define ATA_DA 0x7c /* Device Address Register (R) */`
84			`/* ATA/ATAPI-5 does not describe Device Status Register */`
85
86			`/* ---------------------------- */`
87			`/* ----- Bits definitions ----- */`
88			`/* ---------------------------- */`
89
90			`/* ----- Core Control register */`
91			`/* bits 31-16 are reserved */`
92			`#define ATA_DMA_EN (0<<15) /* DMAen, DMA enable bit */`
93			`/* bit 14 is reserved */`
94			`#define ATA_DMA_WR (1<<14) /* DMA Write transaction */`
95			`#define ATA_DMA_RD (0<<14) /* DMA Read transaction */`
96			`/* bits 13-10 are reserved */`
97			`#define ATA_BELEC1 (1<< 9) /* Big-Little endian conversion */`
98			`/* enable bit for Device1 */`
99			`#define ATA_BELEC0 (1<< 8) /* Big-Little endian conversion */`
100			`/* enable bit for Device0 */`
101			`#define ATA_IDE_EN (1<< 7) /* IDE core enable bit */`
102			`#define ATA_FTE1 (1<< 6) /* Device1 Fast PIO Timing Enable bit */`
103			`#define ATA_FTE0 (1<< 5) /* Device0 Fast PIO Timing Enable bit */`
104			`#define ATA_PWPP (1<< 4) /* PIO Write Ping-Pong Enable bit */`
105			`#define ATA_IORDY_FTE1 (1<< 3) /* Device1 Fast PIO Timing IORDY */`
106			`/* enable bit */`
107			`#define ATA_IORDY_FTE0 (1<< 2) /* Device0 Fast PIO Timing IORDY */`
108			`/* enable bit */`
109			`#define ATA_IORDY (1<< 1) /* PIO Command Timing IORDY enable bit*/`
110			`#define ATA_RST (1<< 0) /* ATA Reset bit */`
111
112			`/* ----- Core Status register */`
113			`#define ATA_DEVID 0xf0000000 /* bits 31-28 Device-ID */`
114			`#define ATA_REVNO 0x0f000000 /* bits 27-24 Revision number */`
115			`/* bits 23-16 are reserved */`
116			`#define ATA_DMA_TIP (1<<15) /* DMA Transfer in progress */`
117			`/* bits 14-10 are reserved */`
118			`#define ATA_DRBE (1<<10) /* DMA Receive buffer empty */`
119			`#define ATA_DTBF (1<< 9) /* DMA Transmit buffer full */`
120			`#define ATA_DMARQ (1<< 8) /* DMARQ Line status */`
121			`#define ATA_PIO_TIP (1<< 7 /* PIO Transfer in progress */`
122			`#define ATA_PWPPF (1<< 6) /* PIO write ping-pong full */`
123			`/* bits 5-1 are reserved */`
124			`#define ATA_IDEIS (1<< 0) /* IDE Interrupt status */`
125
126
127			`/* ----- Core Timing registers */`
128			`#define ATA_TEOC 24 /* End of cycle time DMA/PIO */`
129			`#define ATA_T4 16 /* DIOW- data hold time PIO */`
130			`#define ATA_T2 8 /* DIOR-/DIOW- pulse width PIO */`
131			`#define ATA_TD 8 /* DIOR-/DIOW- pulse width DMA */`
132			`#define ATA_T1 0 /* Address valid to DIOR-/DIOW- PIO */`
133			`#define ATA_TM 0 /* CS[1:0]valid to DIOR-/DIOW- DMA */`
134
135
136			`/* ----- ATA (Alternate) Status Register */`
137			`#define ATA_SR_BSY 0x80 /* Busy */`
138			`#define ATA_SR_DRDY 0x40 /* Device Ready */`
139			`#define ATA_SR_DF 0x20 /* Device Fault */`
140			`#define ATA_SR_DSC 0x10 /* Device Seek Complete */`
141			`#define ATA_SR_DRQ 0x08 /* Data Request */`
142			`#define ATA_SR_COR 0x04 /* Corrected data (obsolete) */`
143			`#define ATA_SR_IDX 0x02 /* (obsolete) */`
144			`#define ATA_SR_ERR 0x01 /* Error */`
145
146			`/* ----- ATA Device Control Register */`
147			`/* bits 7-3 are reserved */`
148			`#define ATA_DCR_RST 0x04 /* Software reset (RST=1, reset) */`
149			`#define ATA_DCR_IEN 0x02 /* Interrupt Enable (IEN=0, enabled) */`
150			`/* always write a '0' to bit0 */`
151
152			`/* ----- ATA Device Address Register */`
153			`/* All values in this register are one's complement (i.e. inverted) */`
154			`#define ATA_DAR_WTG 0x40 /* Write Gate */`
155			`#define ATA_DAR_H 0x3c /* Head Select */`
156			`#define ATA_DAR_DS1 0x02 /* Drive select 1 */`
157			`#define ATA_DAR_DS0 0x01 /* Drive select 0 */`
158
159			`/* ----- Device/Head Register */`
160			`#define ATA_DHR_LBA 0x40 /* LBA/CHS mode ('1'=LBA mode) */`
161			`#define ATA_DHR_DEV 0x10 /* Device ('0'=dev0, '1'=dev1) */`
162			`#define ATA_DHR_H 0x0f /* Head Select */`
163
164			`/* ----- Error Register */`
165			`#define ATA_ERR_BBK 0x80 /* Bad Block */`
166			`#define ATA_ERR_UNC 0x40 /* Uncorrectable Data Error */`
167			`#define ATA_ERR_IDNF 0x10 /* ID Not Found */`
168			`#define ATA_ERR_ABT 0x04 /* Aborted Command */`
169			`#define ATA_ERR_TON 0x02 /* Track0 Not Found */`
170			`#define ATA_ERR_AMN 0x01 /* Address Mark Not Found */`
171
172
173			`/* ---------------------------- */`
174			`/* ----- ATA commands ----- */`
175			`/* ---------------------------- */`
176			`#define CFA_ERASE_SECTORS 0xC0`
177			`#define CFA_REQUEST_EXTENDED_ERROR_CODE 0x03`
178			`#define CFA_TRANSLATE_SECTOR 0x87`
179			`#define CFA_WRITE_MULTIPLE_WITHOUT_ERASE 0xCD`
180			`#define CFA_WRITE_SECTORS_WITHOUT_ERASE 0x38`
181			`#define CHECK_POWER_MODE 0xE5`
182			`#define DEVICE_RESET 0x08`
183			`#define DOWNLOAD_MICROCODE 0x92`
184			`#define EXECUTE_DEVICE_DIAGNOSTIC 0x90`
185			`#define FLUSH_CACHE 0xE7`
186			`#define GET_MEDIA_STATUS 0xDA`
187			`#define IDENTIFY_DEVICE 0xEC`
188			`#define IDENTIFY_PACKET_DEVICE 0xA1`
189			`#define IDLE 0xE3`
190			`#define IDLE_IMMEDIATE 0xE1`
191			`#define INITIALIZE_DEVICE_PARAMETERS 0x91`
192			`#define MEDIA_EJECT 0xED`
193			`#define MEDIA_LOCK 0xDE`
194			`#define MEDIA_UNLOCK 0xDF`
195			`#define NOP 0x00`
196			`#define PACKET 0xA0`
197			`#define READ_BUFFER 0xE4`
198			`#define READ_DMA 0xC8`
199			`#define READ_DMA_QUEUED 0xC7`
200			`#define READ_MULTIPLE 0xC4`
201			`#define READ_NATIVE_MAX_ADDRESS 0xF8`
202			`#define READ_SECTOR 0x20`
203			`#define READ_SECTORS 0x20`
204			`#define READ_VERIFY_SECTOR 0x40`
205			`#define READ_VERIFY_SECTORS 0x40`
206			`#define SECURITY_DISABLE_PASSWORD 0xF6`
207			`#define SECURITY_ERASE_PREPARE 0xF3`
208			`#define SECURITY_ERASE_UNIT 0xF4`
209			`#define SECURITY_FREEZE_LOCK 0xF5`
210			`#define SECURITY_SET_PASSWORD 0xF1`
211			`#define SECURITY_UNLOCK 0xF2`
212			`#define SEEK 0x70`
213			`#define SERVICE 0xA2`
214			`#define SET_FEATURES 0xEF`
215			`#define SET_MAX 0xF9`
216			`#define SET_MULTIPLE_MODE 0xC6`
217			`#define SLEEP 0xE6`
218			`#define SMART 0xB0`
219			`#define STANDBY 0xE2`
220			`#define STANDBY_IMMEDIATE 0xE0`
221			`#define WRITE_BUFFER 0xE8`
222			`#define WRITE_DMA 0xCA`
223			`#define WRITE_DMA_QUEUED 0xCC`
224			`#define WRITE_MULTIPLE 0xC5`
225			`#define WRITE_SECTOR 0x30`
226			`#define WRITE_SECTORS 0x30`
227
228
229			`/* SET_FEATURES has a number of sub-commands (in Features Register) */`
230			`#define CFA_ENABLE_8BIT_PIO_TRANSFER_MODE 0x01`
231			`#define ENABLE_WRITE_CACHE 0x02`
232			`#define SET_TRANSFER_MODE_SECTOR_COUNT_REG 0x03`
233			`#define ENABLE_ADVANCED_POWER_MANAGEMENT 0x05`
234			`#define ENABLE_POWERUP_IN_STANDBY_FEATURE_SET 0x06`
235			`#define POWERUP_IN_STANDBY_FEATURE_SET_SPINUP 0x07`
236			`#define CFA_ENABLE_POWER_MODE1 0x0A`
237			`#define DISABLE_MEDIA_STATUS_NOTIFICATION 0x31`
238			`#define DISABLE_READ_LOOKAHEAD 0x55`
239			`#define ENABLE_RELEASE_INTERRUPT 0x5D`
240			`#define ENABLE_SERVICE_INTERRUPT 0x5E`
241			`#define DISABLE_REVERTING_TO_POWERON_DEFAULTS 0x66`
242			`#define CFA_DISABLE_8BIT_PIO_TRANSFER_MODE 0x81`
243			`#define DISABLE_WRITE_CACHE 0x82`
244			`#define DISABLE_ADVANCED_POWER_MANAGEMENT 0x85`
245			`#define DISABLE_POWERUP_IN_STANDBY_FEATURE_SET 0x86`
246			`#define CFA_DISABLE_POWER_MODE1 0x8A`
247			`#define ENABLE_MEDIA_STATUS_NOTIFICATION 0x95`
248			`#define ENABLE_READ_LOOKAHEAD_FEATURE 0xAA`
249			`#define ENABLE_REVERTING_TO_POWERON_DEFAULTS 0xCC`
250			`#define DISABLE_RELEASE_INTERRUPT 0xDD`
251			`#define DISABLE_SERVICE_INTERRUPT 0xDE`
252
253			`/* SET_MAX has a number of sub-commands (in Features Register) */`
254			`#define SET_MAX_ADDRESS 0x00`
255			`#define SET_MAX_SET_PASSWORD 0x01`
256			`#define SET_MAX_LOCK 0x02`
257			`#define SET_MAX_UNLOCK 0x03`
258			`#define SET_MAX_FREEZE_LOCK 0x04`
259
260			`/* SET_MAX has a number of sub-commands (in Features Register) */`
261			`#define SMART_READ_DATA 0xD0`
262			`#define SMART_ATTRIBITE_AUTOSAVE 0xD1`
263			`#define SMART_SAVE_ATTRIBUTE_VALUES 0xD3`
264			`#define SMART_EXECUTE_OFFLINE_IMMEDIATE 0xD4`
265			`#define SMART_READ_LOG 0xD5`
266			`#define SMART_WRITE_LOG 0xD6`
267			`#define SMART_ENABLE_OPERATIONS 0xD8`
268			`#define SMART_DISABLE_OPERATIONS 0xD9`
269			`#define SMART_RETURN_STATUS 0xDA`
270
271			`/* ---------------------------- */`
272			`/* ----- Structs ----- */`
273			`/* ---------------------------- */`
274
275			`/* ---------------------------- */`
276			`/* ----- Macros ----- */`
277			`/* ---------------------------- */`
278
279			`#define ata_astatus(base) (REG32(base + ATA_ASR))`
280			`#define ata_status(base) (REG32(base + ATA_SR))`
281			`#define ata_error(base) (REG32(base + ATA_ERR))`
282
283			`#define ata_dev_busy(base) (ata_astatus(base) & ATA_SR_BSY)`
284			`#define ata_dev_cmdrdy(base) (ata_astatus(base) & (~ATA_SR_BSY & ATA_SR_DRDY))`
285			`#define ata_dev_datrdy(base) (ata_astatus(base) & ATA_SR_DRQ)`
286
287			`/* ---------------------------- */`
288			`/* ----- Prototypes ----- */`
289			`/* ---------------------------- */`
290			`void module_ata_init (void);`
291			`int atabug(int argc, char **argv);`
292			`int atabug_exit(int argc, char **argv);`
293			`int atabug_help(int argc, char **argv);`
294			`void register_ata_command (const char name, const char params, const char help, int (func)(int argc, char *argv[]));`
295			`int ata_mon_command(void);`
296			`int execute_ata_command(char pstr, int argc, char *argv);`
297
298			`int ata_dump_device_regs_cmd(int argc, char **argv);`
299			`int ata_dump_host_regs_cmd(int argc, char **argv);`
300			`int ata_enable_cmd(int argc, char **argv);`
301			`int ata_exec_cmd_cmd(int argc, char **argv);`
302			`int ata_identify_device_cmd(int argc, char **argv);`
303			`int ata_read_sector_cmd(int argc, char **argv);`
304			`int ata_reset_cmd(int argc, char **argv);`
305			`int ata_select_device_cmd(int argc, char **argv);`
306
307			`unsigned char atabug_dump_data(unsigned short *buffer, int cnt);`
308
309
310			`#endif`