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[/] [or1k/] [trunk/] [orpmon/] [include/] [eth.h] - Blame information for rev 834

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#define ETH_REG_BASE  ETH_BASE 
#define ETH_BD_BASE   (ETH_BASE + 0x400)
#define ETH_TOTAL_BD  128
#define ETH_MAXBUF_LEN 0x600
 
#define ETH_TXBD_NUM      8
#define ETH_TXBD_NUM_MASK (ETH_TXBD_NUM - 1)
#define ETH_RXBD_NUM      8
#define ETH_RXBD_NUM_MASK (ETH_RXBD_NUM - 1)
 
/* Ethernet buffer descriptor */
typedef struct _eth_bd {
        volatile unsigned long   len_status;     /* Buffer length and status */
        volatile unsigned long    addr;          /* Buffer address */
} eth_bd;
 
extern void eth_init (void (*rec)(volatile unsigned char *, int));
extern void *eth_get_tx_buf (void);
extern void eth_send (void *buf, unsigned long len);
extern unsigned long eth_rx (void);
extern void eth_halt(void);
 
/* Tx BD */
#define ETH_TX_BD_READY    0x8000 /* Tx BD Ready */
#define ETH_TX_BD_IRQ      0x4000 /* Tx BD IRQ Enable */
#define ETH_TX_BD_WRAP     0x2000 /* Tx BD Wrap (last BD) */
#define ETH_TX_BD_PAD      0x1000 /* Tx BD Pad Enable */
#define ETH_TX_BD_CRC      0x0800 /* Tx BD CRC Enable */
 
#define ETH_TX_BD_UNDERRUN 0x0100 /* Tx BD Underrun Status */
#define ETH_TX_BD_RETRY    0x00F0 /* Tx BD Retry Status */
#define ETH_TX_BD_RETLIM   0x0008 /* Tx BD Retransmission Limit Status */
#define ETH_TX_BD_LATECOL  0x0004 /* Tx BD Late Collision Status */
#define ETH_TX_BD_DEFER    0x0002 /* Tx BD Defer Status */
#define ETH_TX_BD_CARRIER  0x0001 /* Tx BD Carrier Sense Lost Status */
#define ETH_TX_BD_STATS        (ETH_TX_BD_UNDERRUN             | \
                                ETH_TX_BD_RETRY                | \
                                ETH_TX_BD_RETLIM               | \
                                ETH_TX_BD_LATECOL              | \
                                ETH_TX_BD_DEFER                | \
                                ETH_TX_BD_CARRIER)
 
/* Rx BD */
#define ETH_RX_BD_EMPTY    0x8000 /* Rx BD Empty */
#define ETH_RX_BD_IRQ      0x4000 /* Rx BD IRQ Enable */
#define ETH_RX_BD_WRAP     0x2000 /* Rx BD Wrap (last BD) */
 
#define ETH_RX_BD_MISS     0x0080 /* Rx BD Miss Status */
#define ETH_RX_BD_OVERRUN  0x0040 /* Rx BD Overrun Status */
#define ETH_RX_BD_INVSIMB  0x0020 /* Rx BD Invalid Symbol Status */
#define ETH_RX_BD_DRIBBLE  0x0010 /* Rx BD Dribble Nibble Status */
#define ETH_RX_BD_TOOLONG  0x0008 /* Rx BD Too Long Status */
#define ETH_RX_BD_SHORT    0x0004 /* Rx BD Too Short Frame Status */
#define ETH_RX_BD_CRCERR   0x0002 /* Rx BD CRC Error Status */
#define ETH_RX_BD_LATECOL  0x0001 /* Rx BD Late Collision Status */
#define ETH_RX_BD_STATS        (ETH_RX_BD_MISS                | \
                                ETH_RX_BD_OVERRUN              | \
                                ETH_RX_BD_INVSIMB              | \
                                ETH_RX_BD_DRIBBLE              | \
                                ETH_RX_BD_TOOLONG              | \
                                ETH_RX_BD_SHORT                | \
                                ETH_RX_BD_CRCERR               | \
                                ETH_RX_BD_LATECOL)
 
/* Register space */
#define ETH_MODER      0x00     /* Mode Register */
#define ETH_INT        0x04     /* Interrupt Source Register */
#define ETH_INT_MASK   0x08 /* Interrupt Mask Register */
#define ETH_IPGT       0x0C /* Back to Bak Inter Packet Gap Register */
#define ETH_IPGR1      0x10 /* Non Back to Back Inter Packet Gap Register 1 */
#define ETH_IPGR2      0x14 /* Non Back to Back Inter Packet Gap Register 2 */
#define ETH_PACKETLEN  0x18 /* Packet Length Register (min. and max.) */
#define ETH_COLLCONF   0x1C /* Collision and Retry Configuration Register */
#define ETH_TX_BD_NUM  0x20 /* Transmit Buffer Descriptor Number Register */
#define ETH_CTRLMODER  0x24 /* Control Module Mode Register */
#define ETH_MIIMODER   0x28 /* MII Mode Register */
#define ETH_MIICOMMAND 0x2C /* MII Command Register */
#define ETH_MIIADDRESS 0x30 /* MII Address Register */
#define ETH_MIITX_DATA 0x34 /* MII Transmit Data Register */
#define ETH_MIIRX_DATA 0x38 /* MII Receive Data Register */
#define ETH_MIISTATUS  0x3C /* MII Status Register */
#define ETH_MAC_ADDR0  0x40 /* MAC Individual Address Register 0 */
#define ETH_MAC_ADDR1  0x44 /* MAC Individual Address Register 1 */
#define ETH_HASH_ADDR0 0x48 /* Hash Register 0 */
#define ETH_HASH_ADDR1 0x4C /* Hash Register 1 */
 
/* MODER Register */
#define ETH_MODER_RXEN     0x00000001 /* Receive Enable  */
#define ETH_MODER_TXEN     0x00000002 /* Transmit Enable */
#define ETH_MODER_NOPRE    0x00000004 /* No Preamble  */
#define ETH_MODER_BRO      0x00000008 /* Reject Broadcast */
#define ETH_MODER_IAM      0x00000010 /* Use Individual Hash */
#define ETH_MODER_PRO      0x00000020 /* Promiscuous (receive all) */
#define ETH_MODER_IFG      0x00000040 /* Min. IFG not required */
#define ETH_MODER_LOOPBCK  0x00000080 /* Loop Back */
#define ETH_MODER_NOBCKOF  0x00000100 /* No Backoff */
#define ETH_MODER_EXDFREN  0x00000200 /* Excess Defer */
#define ETH_MODER_FULLD    0x00000400 /* Full Duplex */
#define ETH_MODER_RST      0x00000800 /* Reset MAC */
#define ETH_MODER_DLYCRCEN 0x00001000 /* Delayed CRC Enable */
#define ETH_MODER_CRCEN    0x00002000 /* CRC Enable */
#define ETH_MODER_HUGEN    0x00004000 /* Huge Enable */
#define ETH_MODER_PAD      0x00008000 /* Pad Enable */
#define ETH_MODER_RECSMALL 0x00010000 /* Receive Small */
 
/* Interrupt Source Register */
#define ETH_INT_TXB        0x00000001 /* Transmit Buffer IRQ */
#define ETH_INT_TXE        0x00000002 /* Transmit Error IRQ */
#define ETH_INT_RXF        0x00000004 /* Receive Frame IRQ */
#define ETH_INT_RXE        0x00000008 /* Receive Error IRQ */
#define ETH_INT_BUSY       0x00000010 /* Busy IRQ */
#define ETH_INT_TXC        0x00000020 /* Transmit Control Frame IRQ */
#define ETH_INT_RXC        0x00000040 /* Received Control Frame IRQ */
 
/* Interrupt Mask Register */
#define ETH_INT_MASK_TXB   0x00000001 /* Transmit Buffer IRQ Mask */
#define ETH_INT_MASK_TXE   0x00000002 /* Transmit Error IRQ Mask */
#define ETH_INT_MASK_RXF   0x00000004 /* Receive Frame IRQ Mask */
#define ETH_INT_MASK_RXE   0x00000008 /* Receive Error IRQ Mask */
#define ETH_INT_MASK_BUSY  0x00000010 /* Busy IRQ Mask */
#define ETH_INT_MASK_TXC   0x00000020 /* Transmit Control Frame IRQ Mask */
#define ETH_INT_MASK_RXC   0x00000040 /* Received Control Frame IRQ Mask */
 
/* Control Module Mode Register */
#define ETH_CTRLMODER_PASSALL 0x00000001 /* Pass Control Frames */
#define ETH_CTRLMODER_RXFLOW  0x00000002 /* Receive Control Flow Enable */
#define ETH_CTRLMODER_TXFLOW  0x00000004 /* Transmit Control Flow Enable */
 
/* MII Mode Register */
#define ETH_MIIMODER_CLKDIV   0x000000FF /* Clock Divider */
#define ETH_MIIMODER_NOPRE    0x00000100 /* No Preamble */
#define ETH_MIIMODER_RST      0x00000200 /* MIIM Reset */
 
/* MII Command Register */
#define ETH_MIICOMMAND_SCANSTAT  0x00000001 /* Scan Status */
#define ETH_MIICOMMAND_RSTAT     0x00000002 /* Read Status */
#define ETH_MIICOMMAND_WCTRLDATA 0x00000004 /* Write Control Data */
 
/* MII Address Register */
#define ETH_MIIADDRESS_FIAD 0x0000001F /* PHY Address */
#define ETH_MIIADDRESS_RGAD 0x00001F00 /* RGAD Address */
 
/* MII Status Register */
#define ETH_MIISTATUS_LINKFAIL 0x00000001 /* Link Fail */
#define ETH_MIISTATUS_BUSY     0x00000002 /* MII Busy */
#define ETH_MIISTATUS_NVALID   0x00000004 /* Data in MII Status Register is invalid */
 

Line No.	Rev	Author	Line
1	809	simons	`#define ETH_REG_BASE ETH_BASE`
2	817	simons	`#define ETH_BD_BASE (ETH_BASE + 0x400)`
3	809	simons	`#define ETH_TOTAL_BD 128`
4			`#define ETH_MAXBUF_LEN 0x600`
5
6			`#define ETH_TXBD_NUM 8`
7			`#define ETH_TXBD_NUM_MASK (ETH_TXBD_NUM - 1)`
8			`#define ETH_RXBD_NUM 8`
9			`#define ETH_RXBD_NUM_MASK (ETH_RXBD_NUM - 1)`
10
11			`/* Ethernet buffer descriptor */`
12			`typedef struct _eth_bd {`
13	834	simons	`volatile unsigned long len_status; /* Buffer length and status */`
14	833	simons	`volatile unsigned long addr; /* Buffer address */`
15	809	simons	`} eth_bd;`
16
17			`extern void eth_init (void (rec)(volatile unsigned char , int));`
18			`extern void *eth_get_tx_buf (void);`
19			`extern void eth_send (void *buf, unsigned long len);`
20			`extern unsigned long eth_rx (void);`
21			`extern void eth_halt(void);`
22
23			`/* Tx BD */`
24			`#define ETH_TX_BD_READY 0x8000 /* Tx BD Ready */`
25			`#define ETH_TX_BD_IRQ 0x4000 /* Tx BD IRQ Enable */`
26			`#define ETH_TX_BD_WRAP 0x2000 /* Tx BD Wrap (last BD) */`
27			`#define ETH_TX_BD_PAD 0x1000 /* Tx BD Pad Enable */`
28			`#define ETH_TX_BD_CRC 0x0800 /* Tx BD CRC Enable */`
29
30			`#define ETH_TX_BD_UNDERRUN 0x0100 /* Tx BD Underrun Status */`
31			`#define ETH_TX_BD_RETRY 0x00F0 /* Tx BD Retry Status */`
32			`#define ETH_TX_BD_RETLIM 0x0008 /* Tx BD Retransmission Limit Status */`
33			`#define ETH_TX_BD_LATECOL 0x0004 /* Tx BD Late Collision Status */`
34			`#define ETH_TX_BD_DEFER 0x0002 /* Tx BD Defer Status */`
35			`#define ETH_TX_BD_CARRIER 0x0001 /* Tx BD Carrier Sense Lost Status */`
36			`#define ETH_TX_BD_STATS (ETH_TX_BD_UNDERRUN \| \`
37			`ETH_TX_BD_RETRY \| \`
38			`ETH_TX_BD_RETLIM \| \`
39			`ETH_TX_BD_LATECOL \| \`
40			`ETH_TX_BD_DEFER \| \`
41			`ETH_TX_BD_CARRIER)`
42
43			`/* Rx BD */`
44			`#define ETH_RX_BD_EMPTY 0x8000 /* Rx BD Empty */`
45			`#define ETH_RX_BD_IRQ 0x4000 /* Rx BD IRQ Enable */`
46			`#define ETH_RX_BD_WRAP 0x2000 /* Rx BD Wrap (last BD) */`
47
48			`#define ETH_RX_BD_MISS 0x0080 /* Rx BD Miss Status */`
49			`#define ETH_RX_BD_OVERRUN 0x0040 /* Rx BD Overrun Status */`
50			`#define ETH_RX_BD_INVSIMB 0x0020 /* Rx BD Invalid Symbol Status */`
51			`#define ETH_RX_BD_DRIBBLE 0x0010 /* Rx BD Dribble Nibble Status */`
52			`#define ETH_RX_BD_TOOLONG 0x0008 /* Rx BD Too Long Status */`
53			`#define ETH_RX_BD_SHORT 0x0004 /* Rx BD Too Short Frame Status */`
54			`#define ETH_RX_BD_CRCERR 0x0002 /* Rx BD CRC Error Status */`
55			`#define ETH_RX_BD_LATECOL 0x0001 /* Rx BD Late Collision Status */`
56			`#define ETH_RX_BD_STATS (ETH_RX_BD_MISS \| \`
57			`ETH_RX_BD_OVERRUN \| \`
58			`ETH_RX_BD_INVSIMB \| \`
59			`ETH_RX_BD_DRIBBLE \| \`
60			`ETH_RX_BD_TOOLONG \| \`
61			`ETH_RX_BD_SHORT \| \`
62			`ETH_RX_BD_CRCERR \| \`
63			`ETH_RX_BD_LATECOL)`
64
65			`/* Register space */`
66			`#define ETH_MODER 0x00 /* Mode Register */`
67			`#define ETH_INT 0x04 /* Interrupt Source Register */`
68			`#define ETH_INT_MASK 0x08 /* Interrupt Mask Register */`
69			`#define ETH_IPGT 0x0C /* Back to Bak Inter Packet Gap Register */`
70			`#define ETH_IPGR1 0x10 /* Non Back to Back Inter Packet Gap Register 1 */`
71			`#define ETH_IPGR2 0x14 /* Non Back to Back Inter Packet Gap Register 2 */`
72			`#define ETH_PACKETLEN 0x18 /* Packet Length Register (min. and max.) */`
73			`#define ETH_COLLCONF 0x1C /* Collision and Retry Configuration Register */`
74			`#define ETH_TX_BD_NUM 0x20 /* Transmit Buffer Descriptor Number Register */`
75			`#define ETH_CTRLMODER 0x24 /* Control Module Mode Register */`
76			`#define ETH_MIIMODER 0x28 /* MII Mode Register */`
77			`#define ETH_MIICOMMAND 0x2C /* MII Command Register */`
78			`#define ETH_MIIADDRESS 0x30 /* MII Address Register */`
79			`#define ETH_MIITX_DATA 0x34 /* MII Transmit Data Register */`
80			`#define ETH_MIIRX_DATA 0x38 /* MII Receive Data Register */`
81			`#define ETH_MIISTATUS 0x3C /* MII Status Register */`
82			`#define ETH_MAC_ADDR0 0x40 /* MAC Individual Address Register 0 */`
83			`#define ETH_MAC_ADDR1 0x44 /* MAC Individual Address Register 1 */`
84			`#define ETH_HASH_ADDR0 0x48 /* Hash Register 0 */`
85			`#define ETH_HASH_ADDR1 0x4C /* Hash Register 1 */`
86
87			`/* MODER Register */`
88			`#define ETH_MODER_RXEN 0x00000001 /* Receive Enable */`
89			`#define ETH_MODER_TXEN 0x00000002 /* Transmit Enable */`
90			`#define ETH_MODER_NOPRE 0x00000004 /* No Preamble */`
91			`#define ETH_MODER_BRO 0x00000008 /* Reject Broadcast */`
92			`#define ETH_MODER_IAM 0x00000010 /* Use Individual Hash */`
93			`#define ETH_MODER_PRO 0x00000020 /* Promiscuous (receive all) */`
94			`#define ETH_MODER_IFG 0x00000040 /* Min. IFG not required */`
95			`#define ETH_MODER_LOOPBCK 0x00000080 /* Loop Back */`
96			`#define ETH_MODER_NOBCKOF 0x00000100 /* No Backoff */`
97			`#define ETH_MODER_EXDFREN 0x00000200 /* Excess Defer */`
98			`#define ETH_MODER_FULLD 0x00000400 /* Full Duplex */`
99			`#define ETH_MODER_RST 0x00000800 /* Reset MAC */`
100			`#define ETH_MODER_DLYCRCEN 0x00001000 /* Delayed CRC Enable */`
101			`#define ETH_MODER_CRCEN 0x00002000 /* CRC Enable */`
102			`#define ETH_MODER_HUGEN 0x00004000 /* Huge Enable */`
103			`#define ETH_MODER_PAD 0x00008000 /* Pad Enable */`
104			`#define ETH_MODER_RECSMALL 0x00010000 /* Receive Small */`
105
106			`/* Interrupt Source Register */`
107			`#define ETH_INT_TXB 0x00000001 /* Transmit Buffer IRQ */`
108			`#define ETH_INT_TXE 0x00000002 /* Transmit Error IRQ */`
109			`#define ETH_INT_RXF 0x00000004 /* Receive Frame IRQ */`
110			`#define ETH_INT_RXE 0x00000008 /* Receive Error IRQ */`
111			`#define ETH_INT_BUSY 0x00000010 /* Busy IRQ */`
112			`#define ETH_INT_TXC 0x00000020 /* Transmit Control Frame IRQ */`
113			`#define ETH_INT_RXC 0x00000040 /* Received Control Frame IRQ */`
114
115			`/* Interrupt Mask Register */`
116			`#define ETH_INT_MASK_TXB 0x00000001 /* Transmit Buffer IRQ Mask */`
117			`#define ETH_INT_MASK_TXE 0x00000002 /* Transmit Error IRQ Mask */`
118			`#define ETH_INT_MASK_RXF 0x00000004 /* Receive Frame IRQ Mask */`
119			`#define ETH_INT_MASK_RXE 0x00000008 /* Receive Error IRQ Mask */`
120			`#define ETH_INT_MASK_BUSY 0x00000010 /* Busy IRQ Mask */`
121			`#define ETH_INT_MASK_TXC 0x00000020 /* Transmit Control Frame IRQ Mask */`
122			`#define ETH_INT_MASK_RXC 0x00000040 /* Received Control Frame IRQ Mask */`
123
124			`/* Control Module Mode Register */`
125			`#define ETH_CTRLMODER_PASSALL 0x00000001 /* Pass Control Frames */`
126			`#define ETH_CTRLMODER_RXFLOW 0x00000002 /* Receive Control Flow Enable */`
127			`#define ETH_CTRLMODER_TXFLOW 0x00000004 /* Transmit Control Flow Enable */`
128
129			`/* MII Mode Register */`
130			`#define ETH_MIIMODER_CLKDIV 0x000000FF /* Clock Divider */`
131			`#define ETH_MIIMODER_NOPRE 0x00000100 /* No Preamble */`
132			`#define ETH_MIIMODER_RST 0x00000200 /* MIIM Reset */`
133
134			`/* MII Command Register */`
135			`#define ETH_MIICOMMAND_SCANSTAT 0x00000001 /* Scan Status */`
136			`#define ETH_MIICOMMAND_RSTAT 0x00000002 /* Read Status */`
137			`#define ETH_MIICOMMAND_WCTRLDATA 0x00000004 /* Write Control Data */`
138
139			`/* MII Address Register */`
140			`#define ETH_MIIADDRESS_FIAD 0x0000001F /* PHY Address */`
141			`#define ETH_MIIADDRESS_RGAD 0x00001F00 /* RGAD Address */`
142
143			`/* MII Status Register */`
144			`#define ETH_MIISTATUS_LINKFAIL 0x00000001 /* Link Fail */`
145			`#define ETH_MIISTATUS_BUSY 0x00000002 /* MII Busy */`
146			`#define ETH_MIISTATUS_NVALID 0x00000004 /* Data in MII Status Register is invalid */`
147

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