URL
https://opencores.org/ocsvn/or1k/or1k/trunk
[/] [or1k/] [trunk/] [orpmon/] [include/] [mc-init-1.h] - Blame information for rev 1771
Go to most recent revision |
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
1312 |
jurem |
#ifndef _MC_INIT_1_H_
|
| 2 |
|
|
#define _MC_INIT_1_H_
|
| 3 |
|
|
|
| 4 |
|
|
#if IN_CLK==25000000
|
| 5 |
|
|
# define MC_CSR_VAL 0x0B000300
|
| 6 |
|
|
# define MC_MASK_VAL 0x000003f0
|
| 7 |
|
|
# define FLASH_BASE_ADDR 0xf0000000
|
| 8 |
|
|
# define FLASH_TMS_VAL 0x00000103
|
| 9 |
|
|
# define SDRAM_BASE_ADDR 0x00000000
|
| 10 |
|
|
# define SDRAM_TMS_VAL 0x19220057
|
| 11 |
|
|
#elif IN_CLK==50000000 /* marvin on bender2 board - 50mhz */
|
| 12 |
|
|
# define MC_CSR_VAL 0x0B000300
|
| 13 |
|
|
# define MC_MASK_VAL 0x000003f0
|
| 14 |
|
|
# define FLASH_BASE_ADDR 0xf0000000
|
| 15 |
|
|
# define FLASH_TMS_VAL 0x00000810
|
| 16 |
|
|
# define SDRAM_BASE_ADDR 0x00000000
|
| 17 |
|
|
# define SDRAM_TMS_VAL 0x2a570700
|
| 18 |
|
|
#elif IN_CLK==100000000
|
| 19 |
|
|
# define MC_CSR_VAL 0x0B000300
|
| 20 |
|
|
# define MC_MASK_VAL 0x000003f0
|
| 21 |
|
|
# define FLASH_BASE_ADDR 0xf0000000
|
| 22 |
|
|
# define FLASH_TMS_VAL 0x00000810
|
| 23 |
|
|
# define SDRAM_BASE_ADDR 0x00000000
|
| 24 |
|
|
# define SDRAM_TMS_VAL 0x2a570700
|
| 25 |
|
|
#elif IN_CLK==120000000 /* marvin on 120mhz */
|
| 26 |
|
|
# define MC_CSR_VAL 0x0B000300
|
| 27 |
|
|
# define MC_MASK_VAL 0x000003f0
|
| 28 |
|
|
# define FLASH_BASE_ADDR 0xf0000000
|
| 29 |
|
|
# define FLASH_TMS_VAL 0x00000810
|
| 30 |
|
|
# define SDRAM_BASE_ADDR 0x00000000
|
| 31 |
|
|
# define SDRAM_TMS_VAL 0x2a570700
|
| 32 |
|
|
#else
|
| 33 |
|
|
# error No MC initialize values for this frequency
|
| 34 |
|
|
#endif
|
| 35 |
|
|
|
| 36 |
|
|
#endif /* _MC_INIT_1_H_ */
|
| 37 |
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.