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[/] [or1k/] [trunk/] [orpmon/] [reset.S] - Blame information for rev 816

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#include "spr_defs.h"
#include "board.h"
#include "mc.h"
 
 
 
        .extern _reset_support
        .extern _eth_int
        .extern _src_beg
        .extern _dst_beg
        .extern _dst_end
        .extern _c_reset
        .extern _int_main
 
        /* Used by global.src_addr for default value */
        .extern _src_addr
 
        .global _lolev_ie
        .global _lolev_idis
 
              .section .stack, "aw", @nobits
.space  STACK_SIZE
_stack:
 
.if IN_FLASH
        .section .reset, "ax"
.else
              .section .vectors, "ax"
.endif
 
        .org 0x100
_reset:
.if IN_FLASH
        l.movhi r3,hi(MC_BASE_ADD)
        l.ori   r3,r3,MC_BA_MASK
        l.addi  r5,r0,0x00
        l.sw    0(r3),r5
.endif
        l.movhi r3,hi(_start)
        l.ori   r3,r3,lo(_start)
        l.jr    r3
        l.nop
 
.if IN_FLASH
        .section .vectors, "ax"
.endif
        .org 0x800
 
        l.j     _int_wrapper
        l.nop
 
        .section .text
 
_start:
.if IN_FLASH
        l.jal   _init_mc
        l.nop
 
        /* Wait for SDRAM */
        l.addi  r3,r0,0x0000  /* igor zmanjsal iz 0x7fff na 0x0000 */
1:      l.sfeqi r3,0
        l.bnf   1b
        l.addi  r3,r3,-1
.endif
        /* Copy form flash to sram */
.if IN_FLASH
        l.movhi r3,hi(_src_beg)
        l.ori   r3,r3,lo(_src_beg)
        l.movhi r4,hi(_vec_start)
        l.ori   r4,r4,lo(_vec_start)
        l.movhi r5,hi(_vec_end)
        l.ori   r5,r5,lo(_vec_end)
        l.sub   r5,r5,r4
        l.sfeqi r5,0
        l.bf    2f
        l.nop
1:      l.lwz   r6,0(r3)
        l.sw    0(r4),r6
        l.addi  r3,r3,4
        l.addi  r4,r4,4
        l.addi  r5,r5,-4
        l.sfgtsi r5,0
        l.bf    1b
        l.nop
2:
        l.movhi r4,hi(_dst_beg)
        l.ori   r4,r4,lo(_dst_beg)
        l.movhi r5,hi(_dst_end)
        l.ori   r5,r5,lo(_dst_end)
1:      l.sfgeu r4,r5
        l.bf    1f
        l.nop
        l.lwz   r8,0(r3)
        l.sw    0(r4),r8
        l.addi  r3,r3,4
        l.bnf   1b
        l.addi  r4,r4,4
1:
        l.addi  r3,r0,0
        l.addi  r4,r0,0
3:
.endif
 
.if IC_ENABLE
        l.jal   _ic_enable
        l.nop
.endif
 
.if DC_ENABLE
        l.jal   _dc_enable
        l.nop
.endif
 
        l.movhi r1,hi(_stack-4)
        l.addi  r1,r1,lo(_stack-4)
        l.addi  r2,r0,-3
        l.and   r1,r1,r2
 
        l.movhi r2,hi(_main)
        l.ori   r2,r2,lo(_main)
        l.jr    r2
        l.addi  r2,r0,0
 
_ic_enable:
 
        /* Flush IC */
        l.addi  r10,r0,0
        l.addi  r11,r0,IC_SIZE
1:
        l.mtspr r0,r10,SPR_ICBIR
        l.sfne  r10,r11
        l.bf    1b
        l.addi  r10,r10,16
 
        /* Enable IC */
        l.addi  r10,r0,(SPR_SR_ICE|SPR_SR_SM)
        l.mtspr r0,r10,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        l.jr    r9
        l.nop
 
_dc_enable:
 
        /* Flush DC */
        l.addi  r10,r0,0
        l.addi  r11,r0,DC_SIZE
1:
        l.mtspr r0,r10,SPR_DCBIR
        l.sfne  r10,r11
        l.bf    1b
        l.addi  r10,r10,16
 
        /* Enable DC */
        l.addi  r10,r0,(SPR_SR_DCE|SPR_SR_SM)
        l.mtspr r0,r10,SPR_SR
 
        l.jr    r9
        l.nop
 
.if IN_FLASH
_init_mc:
 
        l.movhi r3,hi(MC_BASE_ADD)
        l.ori   r3,r3,lo(MC_BASE_ADD)
 
        l.addi  r4,r3,MC_CSC(0)
        l.movhi r5,hi(FLASH_BASE_ADD)
        l.srai  r5,r5,5
        l.ori   r5,r5,0x0025
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_TMS(0)
        l.movhi r5,hi(FLASH_TMS_VAL)
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_BA_MASK
        l.addi  r5,r0,MC_MASK_VAL
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_CSR
        l.movhi r5,hi(MC_CSR_VAL)
        l.ori   r5,r5,lo(MC_CSR_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_TMS(1)
        l.movhi r5,hi(SDRAM_TMS_VAL)
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
        l.sw    0(r4),r5
 
        l.addi  r4,r3,MC_CSC(1)
        l.movhi r5,hi(SDRAM_BASE_ADD)
        l.srai  r5,r5,5
        l.ori   r5,r5,0x0411
        l.sw    0(r4),r5
 
        l.jr    r9
        l.nop
.endif
 
_int_wrapper:
        l.addi  r1,r1,-128
 
        l.sw    0x4(r1),r2
        l.sw    0x8(r1),r4
        l.sw    0xc(r1),r5
        l.sw    0x10(r1),r6
        l.sw    0x14(r1),r7
        l.sw    0x18(r1),r8
        l.sw    0x1c(r1),r9
        l.sw    0x20(r1),r10
        l.sw    0x24(r1),r11
        l.sw    0x28(r1),r12
        l.sw    0x2c(r1),r13
        l.sw    0x30(r1),r14
        l.sw    0x34(r1),r15
        l.sw    0x38(r1),r16
        l.sw    0x3c(r1),r17
        l.sw    0x40(r1),r18
        l.sw    0x44(r1),r19
        l.sw    0x48(r1),r20
        l.sw    0x4c(r1),r21
        l.sw    0x50(r1),r22
        l.sw    0x54(r1),r23
        l.sw    0x58(r1),r24
        l.sw    0x5c(r1),r25
        l.sw    0x60(r1),r26
        l.sw    0x64(r1),r27
        l.sw    0x68(r1),r28
        l.sw    0x6c(r1),r29
        l.sw    0x70(r1),r30
        l.sw    0x74(r1),r31
        l.sw    0x78(r1),r3
 
        l.movhi r3,hi(_eth_int)
        l.ori   r3,r3,lo(_eth_int)
        l.jalr  r3
        l.nop
 
        l.lwz   r2,0x4(r1)
        l.lwz   r4,0x8(r1)
        l.lwz   r5,0xc(r1)
        l.lwz   r6,0x10(r1)
        l.lwz   r7,0x14(r1)
        l.lwz   r8,0x18(r1)
        l.lwz   r9,0x1c(r1)
        l.lwz   r10,0x20(r1)
        l.lwz   r11,0x24(r1)
        l.lwz   r12,0x28(r1)
        l.lwz   r13,0x2c(r1)
        l.lwz   r14,0x30(r1)
        l.lwz   r15,0x34(r1)
        l.lwz   r16,0x38(r1)
        l.lwz   r17,0x3c(r1)
        l.lwz   r18,0x40(r1)
        l.lwz   r19,0x44(r1)
        l.lwz   r20,0x48(r1)
        l.lwz   r21,0x4c(r1)
        l.lwz   r22,0x50(r1)
        l.lwz   r23,0x54(r1)
        l.lwz   r24,0x58(r1)
        l.lwz   r25,0x5c(r1)
        l.lwz   r26,0x60(r1)
        l.lwz   r27,0x64(r1)
        l.lwz   r28,0x68(r1)
        l.lwz   r29,0x6c(r1)
        l.lwz   r30,0x70(r1)
        l.lwz   r31,0x74(r1)
#        l.lwz   r3,0x78(r1)
 
        l.mtspr r0,r0,SPR_PICSR
 
        l.mfspr r3,r0,SPR_ESR_BASE
        l.ori   r3,r3,SPR_SR_IEE
        l.mtspr r0,r3,SPR_ESR_BASE
 
        l.lwz   r3,0x78(r1)
 
        l.addi  r1,r1,128
        l.rfe
        l.nop
 
        .section .text
_lolev_ie:
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,SPR_SR_IEE
        l.mtspr r0,r3,SPR_SR
        l.movhi r3,hi(ETH0_INT)
        l.ori   r3,r3,lo(ETH0_INT)
        l.mtspr r0,r3,SPR_PICMR
 
        l.jr    r9
        l.nop
 
_lolev_idis:
        l.mtspr r0,r0,SPR_PICMR
 
        l.jr    r9
        l.nop

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[/] [or1k/] [trunk/] [orpmon/] [reset.S] - Blame information for rev 816

Line No.	Rev	Author	Line
1	809	simons	`#include "spr_defs.h"`
2			`#include "board.h"`
3			`#include "mc.h"`
4
5
6
7			`.extern _reset_support`
8			`.extern _eth_int`
9			`.extern _src_beg`
10			`.extern _dst_beg`
11			`.extern _dst_end`
12			`.extern _c_reset`
13			`.extern _int_main`
14	816	markom
15			`/* Used by global.src_addr for default value */`
16			`.extern _src_addr`
17	809	simons
18			`.global _lolev_ie`
19			`.global _lolev_idis`
20
21			`.section .stack, "aw", @nobits`
22			`.space STACK_SIZE`
23			`_stack:`
24
25			`.if IN_FLASH`
26			`.section .reset, "ax"`
27			`.else`
28			`.section .vectors, "ax"`
29			`.endif`
30
31			`.org 0x100`
32			`_reset:`
33			`.if IN_FLASH`
34			`l.movhi r3,hi(MC_BASE_ADD)`
35			`l.ori r3,r3,MC_BA_MASK`
36			`l.addi r5,r0,0x00`
37			`l.sw 0(r3),r5`
38			`.endif`
39			`l.movhi r3,hi(_start)`
40			`l.ori r3,r3,lo(_start)`
41			`l.jr r3`
42			`l.nop`
43
44			`.if IN_FLASH`
45			`.section .vectors, "ax"`
46			`.endif`
47			`.org 0x800`
48
49			`l.j _int_wrapper`
50			`l.nop`
51
52			`.section .text`
53
54			`_start:`
55			`.if IN_FLASH`
56			`l.jal _init_mc`
57			`l.nop`
58
59			`/* Wait for SDRAM */`
60			`l.addi r3,r0,0x0000 /* igor zmanjsal iz 0x7fff na 0x0000 */`
61			`1: l.sfeqi r3,0`
62			`l.bnf 1b`
63			`l.addi r3,r3,-1`
64			`.endif`
65			`/* Copy form flash to sram */`
66			`.if IN_FLASH`
67			`l.movhi r3,hi(_src_beg)`
68			`l.ori r3,r3,lo(_src_beg)`
69			`l.movhi r4,hi(_vec_start)`
70			`l.ori r4,r4,lo(_vec_start)`
71			`l.movhi r5,hi(_vec_end)`
72			`l.ori r5,r5,lo(_vec_end)`
73			`l.sub r5,r5,r4`
74			`l.sfeqi r5,0`
75			`l.bf 2f`
76			`l.nop`
77			`1: l.lwz r6,0(r3)`
78			`l.sw 0(r4),r6`
79			`l.addi r3,r3,4`
80			`l.addi r4,r4,4`
81			`l.addi r5,r5,-4`
82			`l.sfgtsi r5,0`
83			`l.bf 1b`
84			`l.nop`
85			`2:`
86			`l.movhi r4,hi(_dst_beg)`
87			`l.ori r4,r4,lo(_dst_beg)`
88			`l.movhi r5,hi(_dst_end)`
89			`l.ori r5,r5,lo(_dst_end)`
90			`1: l.sfgeu r4,r5`
91			`l.bf 1f`
92			`l.nop`
93			`l.lwz r8,0(r3)`
94			`l.sw 0(r4),r8`
95			`l.addi r3,r3,4`
96			`l.bnf 1b`
97			`l.addi r4,r4,4`
98			`1:`
99			`l.addi r3,r0,0`
100			`l.addi r4,r0,0`
101			`3:`
102			`.endif`
103
104			`.if IC_ENABLE`
105			`l.jal _ic_enable`
106			`l.nop`
107			`.endif`
108
109			`.if DC_ENABLE`
110			`l.jal _dc_enable`
111			`l.nop`
112			`.endif`
113
114			`l.movhi r1,hi(_stack-4)`
115			`l.addi r1,r1,lo(_stack-4)`
116			`l.addi r2,r0,-3`
117			`l.and r1,r1,r2`
118
119			`l.movhi r2,hi(_main)`
120			`l.ori r2,r2,lo(_main)`
121			`l.jr r2`
122			`l.addi r2,r0,0`
123
124			`_ic_enable:`
125
126			`/* Flush IC */`
127			`l.addi r10,r0,0`
128			`l.addi r11,r0,IC_SIZE`
129			`1:`
130			`l.mtspr r0,r10,SPR_ICBIR`
131			`l.sfne r10,r11`
132			`l.bf 1b`
133			`l.addi r10,r10,16`
134
135			`/* Enable IC */`
136			`l.addi r10,r0,(SPR_SR_ICE\|SPR_SR_SM)`
137			`l.mtspr r0,r10,SPR_SR`
138			`l.nop`
139			`l.nop`
140			`l.nop`
141			`l.nop`
142			`l.nop`
143
144			`l.jr r9`
145			`l.nop`
146
147			`_dc_enable:`
148
149			`/* Flush DC */`
150			`l.addi r10,r0,0`
151			`l.addi r11,r0,DC_SIZE`
152			`1:`
153			`l.mtspr r0,r10,SPR_DCBIR`
154			`l.sfne r10,r11`
155			`l.bf 1b`
156			`l.addi r10,r10,16`
157
158			`/* Enable DC */`
159			`l.addi r10,r0,(SPR_SR_DCE\|SPR_SR_SM)`
160			`l.mtspr r0,r10,SPR_SR`
161
162			`l.jr r9`
163			`l.nop`
164
165			`.if IN_FLASH`
166			`_init_mc:`
167
168			`l.movhi r3,hi(MC_BASE_ADD)`
169			`l.ori r3,r3,lo(MC_BASE_ADD)`
170
171			`l.addi r4,r3,MC_CSC(0)`
172			`l.movhi r5,hi(FLASH_BASE_ADD)`
173			`l.srai r5,r5,5`
174			`l.ori r5,r5,0x0025`
175			`l.sw 0(r4),r5`
176
177			`l.addi r4,r3,MC_TMS(0)`
178			`l.movhi r5,hi(FLASH_TMS_VAL)`
179			`l.ori r5,r5,lo(FLASH_TMS_VAL)`
180			`l.sw 0(r4),r5`
181
182			`l.addi r4,r3,MC_BA_MASK`
183			`l.addi r5,r0,MC_MASK_VAL`
184			`l.sw 0(r4),r5`
185
186			`l.addi r4,r3,MC_CSR`
187			`l.movhi r5,hi(MC_CSR_VAL)`
188			`l.ori r5,r5,lo(MC_CSR_VAL)`
189			`l.sw 0(r4),r5`
190
191			`l.addi r4,r3,MC_TMS(1)`
192			`l.movhi r5,hi(SDRAM_TMS_VAL)`
193			`l.ori r5,r5,lo(SDRAM_TMS_VAL)`
194			`l.sw 0(r4),r5`
195
196			`l.addi r4,r3,MC_CSC(1)`
197			`l.movhi r5,hi(SDRAM_BASE_ADD)`
198			`l.srai r5,r5,5`
199			`l.ori r5,r5,0x0411`
200			`l.sw 0(r4),r5`
201
202			`l.jr r9`
203			`l.nop`
204			`.endif`
205
206			`_int_wrapper:`
207			`l.addi r1,r1,-128`
208
209			`l.sw 0x4(r1),r2`
210			`l.sw 0x8(r1),r4`
211			`l.sw 0xc(r1),r5`
212			`l.sw 0x10(r1),r6`
213			`l.sw 0x14(r1),r7`
214			`l.sw 0x18(r1),r8`
215			`l.sw 0x1c(r1),r9`
216			`l.sw 0x20(r1),r10`
217			`l.sw 0x24(r1),r11`
218			`l.sw 0x28(r1),r12`
219			`l.sw 0x2c(r1),r13`
220			`l.sw 0x30(r1),r14`
221			`l.sw 0x34(r1),r15`
222			`l.sw 0x38(r1),r16`
223			`l.sw 0x3c(r1),r17`
224			`l.sw 0x40(r1),r18`
225			`l.sw 0x44(r1),r19`
226			`l.sw 0x48(r1),r20`
227			`l.sw 0x4c(r1),r21`
228			`l.sw 0x50(r1),r22`
229			`l.sw 0x54(r1),r23`
230			`l.sw 0x58(r1),r24`
231			`l.sw 0x5c(r1),r25`
232			`l.sw 0x60(r1),r26`
233			`l.sw 0x64(r1),r27`
234			`l.sw 0x68(r1),r28`
235			`l.sw 0x6c(r1),r29`
236			`l.sw 0x70(r1),r30`
237			`l.sw 0x74(r1),r31`
238			`l.sw 0x78(r1),r3`
239
240			`l.movhi r3,hi(_eth_int)`
241			`l.ori r3,r3,lo(_eth_int)`
242			`l.jalr r3`
243			`l.nop`
244
245			`l.lwz r2,0x4(r1)`
246			`l.lwz r4,0x8(r1)`
247			`l.lwz r5,0xc(r1)`
248			`l.lwz r6,0x10(r1)`
249			`l.lwz r7,0x14(r1)`
250			`l.lwz r8,0x18(r1)`
251			`l.lwz r9,0x1c(r1)`
252			`l.lwz r10,0x20(r1)`
253			`l.lwz r11,0x24(r1)`
254			`l.lwz r12,0x28(r1)`
255			`l.lwz r13,0x2c(r1)`
256			`l.lwz r14,0x30(r1)`
257			`l.lwz r15,0x34(r1)`
258			`l.lwz r16,0x38(r1)`
259			`l.lwz r17,0x3c(r1)`
260			`l.lwz r18,0x40(r1)`
261			`l.lwz r19,0x44(r1)`
262			`l.lwz r20,0x48(r1)`
263			`l.lwz r21,0x4c(r1)`
264			`l.lwz r22,0x50(r1)`
265			`l.lwz r23,0x54(r1)`
266			`l.lwz r24,0x58(r1)`
267			`l.lwz r25,0x5c(r1)`
268			`l.lwz r26,0x60(r1)`
269			`l.lwz r27,0x64(r1)`
270			`l.lwz r28,0x68(r1)`
271			`l.lwz r29,0x6c(r1)`
272			`l.lwz r30,0x70(r1)`
273			`l.lwz r31,0x74(r1)`
274			`# l.lwz r3,0x78(r1)`
275
276			`l.mtspr r0,r0,SPR_PICSR`
277
278			`l.mfspr r3,r0,SPR_ESR_BASE`
279			`l.ori r3,r3,SPR_SR_IEE`
280			`l.mtspr r0,r3,SPR_ESR_BASE`
281
282			`l.lwz r3,0x78(r1)`
283
284			`l.addi r1,r1,128`
285			`l.rfe`
286			`l.nop`
287
288			`.section .text`
289			`_lolev_ie:`
290			`l.mfspr r3,r0,SPR_SR`
291			`l.ori r3,r3,SPR_SR_IEE`
292			`l.mtspr r0,r3,SPR_SR`
293			`l.movhi r3,hi(ETH0_INT)`
294			`l.ori r3,r3,lo(ETH0_INT)`
295			`l.mtspr r0,r3,SPR_PICMR`
296
297			`l.jr r9`
298			`l.nop`
299
300			`_lolev_idis:`
301			`l.mtspr r0,r0,SPR_PICMR`
302
303			`l.jr r9`
304			`l.nop`