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[/] [or1k/] [trunk/] [orpmon/] [reset.S] - Blame information for rev 817

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Line No. Rev Author Line
1 809 simons 
#include "spr_defs.h"
2 
#include "board.h"
3 
#include "mc.h"
4 
 
5 
 
6 
 
7 
        .extern _reset_support
8 
        .extern _eth_int
9 
        .extern _src_beg
10 
        .extern _dst_beg
11 
        .extern _dst_end
12 
        .extern _c_reset
13 
        .extern _int_main
14 816 markom 
 
15 
        /* Used by global.src_addr for default value */
16 
        .extern _src_addr
17 809 simons 
 
18 
        .global _lolev_ie
19 
        .global _lolev_idis
20 817 simons 
        .global _align
21 809 simons 
 
22 817 simons 
        .section .stack, "aw", @nobits
23 
.space  STACK_SIZE
24 809 simons 
_stack:
25 
 
26 
.if IN_FLASH
27 
        .section .reset, "ax"
28 
.else
29 817 simons 
        .section .vectors, "ax"
30 809 simons 
.endif
31 
 
32 
        .org 0x100
33 
_reset:
34 
.if IN_FLASH
35 817 simons 
        l.movhi r3,hi(MC_BASE_ADDR)
36 809 simons 
        l.ori   r3,r3,MC_BA_MASK
37 
        l.addi  r5,r0,0x00
38 
        l.sw    0(r3),r5
39 
.endif
40 817 simons 
        l.movhi r3,hi(_start)
41 809 simons 
        l.ori   r3,r3,lo(_start)
42 
        l.jr    r3
43 
        l.nop
44 
 
45 
.if IN_FLASH
46 
        .section .vectors, "ax"
47 
.endif
48 817 simons 
        .org 0x600
49 809 simons 
 
50 817 simons 
        l.j     _align
51 
        l.nop
52 
 
53 
        .org 0x800
54 
 
55 809 simons 
        l.j     _int_wrapper
56 
        l.nop
57 
 
58 
        .section .text
59 
 
60 
_start:
61 
.if IN_FLASH
62 
        l.jal   _init_mc
63 
        l.nop
64 
 
65 
        /* Wait for SDRAM */
66 
        l.addi  r3,r0,0x0000  /* igor zmanjsal iz 0x7fff na 0x0000 */
67 
1:      l.sfeqi r3,0
68 
        l.bnf   1b
69 
        l.addi  r3,r3,-1
70 
.endif
71 817 simons 
        /* Copy form flash to sram */
72 809 simons 
.if IN_FLASH
73 
        l.movhi r3,hi(_src_beg)
74 
        l.ori   r3,r3,lo(_src_beg)
75 
        l.movhi r4,hi(_vec_start)
76 
        l.ori   r4,r4,lo(_vec_start)
77 
        l.movhi r5,hi(_vec_end)
78 
        l.ori   r5,r5,lo(_vec_end)
79 
        l.sub   r5,r5,r4
80 
        l.sfeqi r5,0
81 
        l.bf    2f
82 
        l.nop
83 
1:      l.lwz   r6,0(r3)
84 
        l.sw    0(r4),r6
85 
        l.addi  r3,r3,4
86 
        l.addi  r4,r4,4
87 
        l.addi  r5,r5,-4
88 
        l.sfgtsi r5,0
89 817 simons 
        l.bf    1b
90 809 simons 
        l.nop
91 
2:
92 
        l.movhi r4,hi(_dst_beg)
93 
        l.ori   r4,r4,lo(_dst_beg)
94 
        l.movhi r5,hi(_dst_end)
95 
        l.ori   r5,r5,lo(_dst_end)
96 
1:      l.sfgeu r4,r5
97 
        l.bf    1f
98 
        l.nop
99 
        l.lwz   r8,0(r3)
100 
        l.sw    0(r4),r8
101 
        l.addi  r3,r3,4
102 
        l.bnf   1b
103 
        l.addi  r4,r4,4
104 
1:
105 
        l.addi  r3,r0,0
106 
        l.addi  r4,r0,0
107 
3:
108 
.endif
109 
 
110 
.if IC_ENABLE
111 817 simons 
  l.jal _ic_enable
112 
  l.nop
113 809 simons 
.endif
114 
 
115 
.if DC_ENABLE
116 817 simons 
  l.jal _dc_enable
117 
  l.nop
118 809 simons 
.endif
119 
 
120 
        l.movhi r1,hi(_stack-4)
121 
        l.addi  r1,r1,lo(_stack-4)
122 817 simons 
  l.addi  r2,r0,-3
123 
  l.and r1,r1,r2
124 809 simons 
 
125 
        l.movhi r2,hi(_main)
126 
        l.ori   r2,r2,lo(_main)
127 
        l.jr    r2
128 
        l.addi  r2,r0,0
129 
 
130 
_ic_enable:
131 
 
132 
        /* Flush IC */
133 
        l.addi  r10,r0,0
134 
        l.addi  r11,r0,IC_SIZE
135 
1:
136 
        l.mtspr r0,r10,SPR_ICBIR
137 
        l.sfne  r10,r11
138 
        l.bf    1b
139 
        l.addi  r10,r10,16
140 
 
141 
        /* Enable IC */
142 
        l.addi  r10,r0,(SPR_SR_ICE|SPR_SR_SM)
143 
        l.mtspr r0,r10,SPR_SR
144 
        l.nop
145 
        l.nop
146 
        l.nop
147 
        l.nop
148 
        l.nop
149 
 
150 817 simons 
  l.jr  r9
151 
  l.nop
152 809 simons 
 
153 
_dc_enable:
154 
 
155 
        /* Flush DC */
156 
        l.addi  r10,r0,0
157 
        l.addi  r11,r0,DC_SIZE
158 
1:
159 
        l.mtspr r0,r10,SPR_DCBIR
160 
        l.sfne  r10,r11
161 
        l.bf    1b
162 
        l.addi  r10,r10,16
163 
 
164 
        /* Enable DC */
165 
        l.addi  r10,r0,(SPR_SR_DCE|SPR_SR_SM)
166 
        l.mtspr r0,r10,SPR_SR
167 
 
168 817 simons 
  l.jr  r9
169 
  l.nop
170 809 simons 
 
171 
.if IN_FLASH
172 
_init_mc:
173 
 
174 817 simons 
        l.movhi r3,hi(MC_BASE_ADDR)
175 
        l.ori   r3,r3,lo(MC_BASE_ADDR)
176 809 simons 
 
177 
        l.addi  r4,r3,MC_CSC(0)
178 817 simons 
        l.movhi r5,hi(FLASH_BASE_ADDR)
179 809 simons 
        l.srai  r5,r5,5
180 
        l.ori   r5,r5,0x0025
181 
        l.sw    0(r4),r5
182 
 
183 
        l.addi  r4,r3,MC_TMS(0)
184 
        l.movhi r5,hi(FLASH_TMS_VAL)
185 
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
186 
        l.sw    0(r4),r5
187 
 
188 
        l.addi  r4,r3,MC_BA_MASK
189 
        l.addi  r5,r0,MC_MASK_VAL
190 
        l.sw    0(r4),r5
191 
 
192 
        l.addi  r4,r3,MC_CSR
193 
        l.movhi r5,hi(MC_CSR_VAL)
194 
        l.ori   r5,r5,lo(MC_CSR_VAL)
195 
        l.sw    0(r4),r5
196 
 
197 
        l.addi  r4,r3,MC_TMS(1)
198 
        l.movhi r5,hi(SDRAM_TMS_VAL)
199 
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
200 
        l.sw    0(r4),r5
201 
 
202 
        l.addi  r4,r3,MC_CSC(1)
203 817 simons 
        l.movhi r5,hi(SDRAM_BASE_ADDR)
204 809 simons 
        l.srai  r5,r5,5
205 
        l.ori   r5,r5,0x0411
206 
        l.sw    0(r4),r5
207 
 
208 
        l.jr    r9
209 
        l.nop
210 
.endif
211 
 
212 
_int_wrapper:
213 
        l.addi  r1,r1,-128
214 
 
215 
        l.sw    0x4(r1),r2
216 
        l.sw    0x8(r1),r4
217 
        l.sw    0xc(r1),r5
218 
        l.sw    0x10(r1),r6
219 
        l.sw    0x14(r1),r7
220 
        l.sw    0x18(r1),r8
221 
        l.sw    0x1c(r1),r9
222 
        l.sw    0x20(r1),r10
223 
        l.sw    0x24(r1),r11
224 
        l.sw    0x28(r1),r12
225 
        l.sw    0x2c(r1),r13
226 
        l.sw    0x30(r1),r14
227 
        l.sw    0x34(r1),r15
228 
        l.sw    0x38(r1),r16
229 
        l.sw    0x3c(r1),r17
230 
        l.sw    0x40(r1),r18
231 
        l.sw    0x44(r1),r19
232 
        l.sw    0x48(r1),r20
233 
        l.sw    0x4c(r1),r21
234 
        l.sw    0x50(r1),r22
235 
        l.sw    0x54(r1),r23
236 
        l.sw    0x58(r1),r24
237 
        l.sw    0x5c(r1),r25
238 
        l.sw    0x60(r1),r26
239 
        l.sw    0x64(r1),r27
240 
        l.sw    0x68(r1),r28
241 
        l.sw    0x6c(r1),r29
242 
        l.sw    0x70(r1),r30
243 
        l.sw    0x74(r1),r31
244 
        l.sw    0x78(r1),r3
245 
 
246 
        l.movhi r3,hi(_eth_int)
247 
        l.ori   r3,r3,lo(_eth_int)
248 
        l.jalr  r3
249 
        l.nop
250 
 
251 
        l.lwz   r2,0x4(r1)
252 
        l.lwz   r4,0x8(r1)
253 
        l.lwz   r5,0xc(r1)
254 
        l.lwz   r6,0x10(r1)
255 
        l.lwz   r7,0x14(r1)
256 
        l.lwz   r8,0x18(r1)
257 
        l.lwz   r9,0x1c(r1)
258 
        l.lwz   r10,0x20(r1)
259 
        l.lwz   r11,0x24(r1)
260 
        l.lwz   r12,0x28(r1)
261 
        l.lwz   r13,0x2c(r1)
262 
        l.lwz   r14,0x30(r1)
263 
        l.lwz   r15,0x34(r1)
264 
        l.lwz   r16,0x38(r1)
265 
        l.lwz   r17,0x3c(r1)
266 
        l.lwz   r18,0x40(r1)
267 
        l.lwz   r19,0x44(r1)
268 
        l.lwz   r20,0x48(r1)
269 
        l.lwz   r21,0x4c(r1)
270 
        l.lwz   r22,0x50(r1)
271 
        l.lwz   r23,0x54(r1)
272 
        l.lwz   r24,0x58(r1)
273 
        l.lwz   r25,0x5c(r1)
274 
        l.lwz   r26,0x60(r1)
275 
        l.lwz   r27,0x64(r1)
276 
        l.lwz   r28,0x68(r1)
277 
        l.lwz   r29,0x6c(r1)
278 
        l.lwz   r30,0x70(r1)
279 
        l.lwz   r31,0x74(r1)
280 
#        l.lwz   r3,0x78(r1)
281 
 
282 
        l.mtspr r0,r0,SPR_PICSR
283 
 
284 
        l.mfspr r3,r0,SPR_ESR_BASE
285 
        l.ori   r3,r3,SPR_SR_IEE
286 
        l.mtspr r0,r3,SPR_ESR_BASE
287 
 
288 
        l.lwz   r3,0x78(r1)
289 
 
290 
        l.addi  r1,r1,128
291 
        l.rfe
292 
        l.nop
293 
 
294 817 simons 
_align:
295 
        l.addi  r1,r1,-128
296 
        l.sw    0x08(r1),r2
297 
        l.sw    0x0c(r1),r3
298 
        l.sw    0x10(r1),r4
299 
        l.sw    0x14(r1),r5
300 
        l.sw    0x18(r1),r6
301 
        l.sw    0x1c(r1),r7
302 
        l.sw    0x20(r1),r8
303 
        l.sw    0x24(r1),r9
304 
        l.sw    0x28(r1),r10
305 
        l.sw    0x2c(r1),r11
306 
        l.sw    0x30(r1),r12
307 
        l.sw    0x34(r1),r13
308 
        l.sw    0x38(r1),r14
309 
        l.sw    0x3c(r1),r15
310 
        l.sw    0x40(r1),r16
311 
        l.sw    0x44(r1),r17
312 
        l.sw    0x48(r1),r18
313 
        l.sw    0x4c(r1),r19
314 
        l.sw    0x50(r1),r20
315 
        l.sw    0x54(r1),r21
316 
        l.sw    0x58(r1),r22
317 
        l.sw    0x5c(r1),r23
318 
        l.sw    0x60(r1),r24
319 
        l.sw    0x64(r1),r25
320 
        l.sw    0x68(r1),r26
321 
        l.sw    0x6c(r1),r27
322 
        l.sw    0x70(r1),r28
323 
        l.sw    0x74(r1),r29
324 
        l.sw    0x78(r1),r30
325 
        l.sw    0x7c(r1),r31
326 
 
327 
        l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */
328 
        l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
329 
 
330 
        l.lwz r3,0(r5)      /* Load insn */
331 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
332 
 
333 
        l.sfeqi r4,0x00     /* Check if the load/store insn is in delay slot */
334 
        l.bf  jmp
335 
        l.sfeqi r4,0x01
336 
        l.bf  jmp
337 
        l.sfeqi r4,0x03
338 
        l.bf  jmp
339 
        l.sfeqi r4,0x04
340 
        l.bf  jmp
341 
        l.sfeqi r4,0x11
342 
        l.bf  jr
343 
        l.sfeqi r4,0x12
344 
        l.bf  jr
345 
        l.nop
346 
        l.j 1f
347 
        l.addi  r5,r5,4     /* Increment PC to get return insn address */
348 
 
349 
jmp:
350 
        l.slli  r4,r3,6     /* Get the signed extended jump length */
351 
        l.srai  r4,r4,4
352 
 
353 
        l.lwz r3,4(r5)      /* Load the real load/store insn */
354 
 
355 
        l.add r5,r5,r4      /* Calculate jump target address */
356 
 
357 
        l.j 1f
358 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
359 
 
360 
jr:
361 
        l.slli  r4,r3,9     /* Shift to get the reg nb */
362 
        l.andi  r4,r4,0x7c
363 
 
364 
        l.lwz r3,4(r5)    /* Load the real load/store insn */
365 
 
366 
        l.add r4,r4,r1    /* Load the jump register value from the stack */
367 
        l.lwz r5,0(r4)
368 
 
369 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
370 
 
371 
 
372 
1:      l.mtspr r0,r5,SPR_EPCR_BASE
373 
 
374 
        l.sfeqi r4,0x26
375 
        l.bf  lhs
376 
        l.sfeqi r4,0x25
377 
        l.bf  lhz
378 
        l.sfeqi r4,0x22
379 
        l.bf  lws
380 
        l.sfeqi r4,0x21
381 
        l.bf  lwz
382 
        l.sfeqi r4,0x37
383 
        l.bf  sh
384 
        l.sfeqi r4,0x35
385 
        l.bf  sw
386 
        l.nop
387 
 
388 
1:      l.j 1b      /* I don't know what to do */
389 
        l.nop
390 
 
391 
lhs:    l.lbs r5,0(r2)
392 
        l.slli  r5,r5,8
393 
        l.lbz r6,1(r2)
394 
        l.or  r5,r5,r6
395 
        l.srli  r4,r3,19
396 
        l.andi  r4,r4,0x7c
397 
        l.add r4,r4,r1
398 
        l.j align_end
399 
        l.sw  0(r4),r5
400 
 
401 
lhz:    l.lbz r5,0(r2)
402 
        l.slli  r5,r5,8
403 
        l.lbz r6,1(r2)
404 
        l.or  r5,r5,r6
405 
        l.srli  r4,r3,19
406 
        l.andi  r4,r4,0x7c
407 
        l.add r4,r4,r1
408 
        l.j align_end
409 
        l.sw  0(r4),r5
410 
 
411 
lws:    l.lbs r5,0(r2)
412 
        l.slli  r5,r5,24
413 
        l.lbz r6,1(r2)
414 
        l.slli  r6,r6,16
415 
        l.or  r5,r5,r6
416 
        l.lbz r6,2(r2)
417 
        l.slli  r6,r6,8
418 
        l.or  r5,r5,r6
419 
        l.lbz r6,3(r2)
420 
        l.or  r5,r5,r6
421 
        l.srli  r4,r3,19
422 
        l.andi  r4,r4,0x7c
423 
        l.add r4,r4,r1
424 
        l.j align_end
425 
        l.sw  0(r4),r5
426 
 
427 
lwz:    l.lbz r5,0(r2)
428 
        l.slli  r5,r5,24
429 
        l.lbz r6,1(r2)
430 
        l.slli  r6,r6,16
431 
        l.or  r5,r5,r6
432 
        l.lbz r6,2(r2)
433 
        l.slli  r6,r6,8
434 
        l.or  r5,r5,r6
435 
        l.lbz r6,3(r2)
436 
        l.or  r5,r5,r6
437 
        l.srli  r4,r3,19
438 
        l.andi  r4,r4,0x7c
439 
        l.add r4,r4,r1
440 
        l.j align_end
441 
        l.sw  0(r4),r5
442 
 
443 
sh:
444 
        l.srli  r4,r3,9
445 
        l.andi  r4,r4,0x7c
446 
        l.add r4,r4,r1
447 
        l.lwz r5,0(r4)
448 
        l.sb  1(r2),r5
449 
        l.slli  r5,r5,8
450 
        l.j align_end
451 
        l.sb  0(r2),r5
452 
 
453 
sw:
454 
        l.srli  r4,r3,9
455 
        l.andi  r4,r4,0x7c
456 
        l.add r4,r4,r1
457 
        l.lwz r5,0(r4)
458 
        l.sb  3(r2),r5
459 
        l.slli  r5,r5,8
460 
        l.sb  2(r2),r5
461 
        l.slli  r5,r5,8
462 
        l.sb  1(r2),r5
463 
        l.slli  r5,r5,8
464 
        l.j align_end
465 
        l.sb  0(r2),r5
466 
 
467 
align_end:
468 
        l.lwz   r2,0x08(r1)
469 
        l.lwz   r3,0x0c(r1)
470 
        l.lwz   r4,0x10(r1)
471 
        l.lwz   r5,0x14(r1)
472 
        l.lwz   r6,0x18(r1)
473 
        l.lwz   r7,0x1c(r1)
474 
        l.lwz   r8,0x20(r1)
475 
        l.lwz   r9,0x24(r1)
476 
        l.lwz   r10,0x28(r1)
477 
        l.lwz   r11,0x2c(r1)
478 
        l.lwz   r12,0x30(r1)
479 
        l.lwz   r13,0x34(r1)
480 
        l.lwz   r14,0x38(r1)
481 
        l.lwz   r15,0x3c(r1)
482 
        l.lwz   r16,0x40(r1)
483 
        l.lwz   r17,0x44(r1)
484 
        l.lwz   r18,0x48(r1)
485 
        l.lwz   r19,0x4c(r1)
486 
        l.lwz   r20,0x50(r1)
487 
        l.lwz   r21,0x54(r1)
488 
        l.lwz   r22,0x58(r1)
489 
        l.lwz   r23,0x5c(r1)
490 
        l.lwz   r24,0x60(r1)
491 
        l.lwz   r25,0x64(r1)
492 
        l.lwz   r26,0x68(r1)
493 
        l.lwz   r27,0x6c(r1)
494 
        l.lwz   r28,0x70(r1)
495 
        l.lwz   r29,0x74(r1)
496 
        l.lwz   r30,0x78(r1)
497 
        l.lwz   r31,0x7c(r1)
498 
        l.addi  r1,r1,128
499 
        l.rfe
500 
 
501 809 simons 
        .section .text
502 
_lolev_ie:
503 
        l.mfspr r3,r0,SPR_SR
504 
        l.ori   r3,r3,SPR_SR_IEE
505 
        l.mtspr r0,r3,SPR_SR
506 817 simons 
        l.movhi r3,hi(ETH0_INT)
507 
  l.ori r3,r3,lo(ETH0_INT)
508 809 simons 
        l.mtspr r0,r3,SPR_PICMR
509 
 
510 
        l.jr    r9
511 
        l.nop
512 
 
513 
_lolev_idis:
514 
        l.mtspr r0,r0,SPR_PICMR
515 
 
516 
        l.jr    r9
517 
        l.nop

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