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[/] [or1k/] [trunk/] [orpmon/] [reset.S] - Blame information for rev 820

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Line No. Rev Author Line
1 809 simons 
#include "spr_defs.h"
2 
#include "board.h"
3 
#include "mc.h"
4 
 
5 
 
6 
 
7 
        .extern _reset_support
8 
        .extern _eth_int
9 
        .extern _src_beg
10 
        .extern _dst_beg
11 
        .extern _dst_end
12 
        .extern _c_reset
13 
        .extern _int_main
14 820 markom 
        .extern _crc32
15 816 markom 
 
16 
        /* Used by global.src_addr for default value */
17 
        .extern _src_addr
18 809 simons 
 
19 
        .global _lolev_ie
20 
        .global _lolev_idis
21 817 simons 
        .global _align
22 820 markom 
        .global _calc_mycrc32
23 809 simons 
 
24 817 simons 
        .section .stack, "aw", @nobits
25 
.space  STACK_SIZE
26 809 simons 
_stack:
27 820 markom 
                                .section .crc
28 
_mycrc32:
29 
        .word   0xcccccccc
30 
_mysize:
31 
        .word 0xdddddddd
32 809 simons 
 
33 820 markom 
_calc_mycrc32:
34 
                                l.addi  r3,r0,0
35 
        l.movhi r4,hi(_calc_mycrc32)
36 
        l.ori   r4,r4,lo(_calc_mycrc32)
37 
        l.movhi r5,hi(_mysize)
38 
        l.ori   r5,r5,lo(_mysize)
39 
        l.lwz   r5,0(r5)
40 
 
41 
        /* unsigned long crc32 (unsigned long crc, const unsigned char *buf, unsigned long len); */
42 
                                l.jal           _crc32
43 
                                l.nop
44 
 
45 
                                l.movhi r3,hi(_mycrc32)
46 
        l.ori   r3,r3,lo(_mycrc32)
47 
        l.lwz   r3,0(r3)
48 
 
49 
        l.jr            r9
50 
                                l.xor     r11,r3,r11
51 
                                .org 0x100
52 
 
53 809 simons 
.if IN_FLASH
54 
        .section .reset, "ax"
55 
.else
56 817 simons 
        .section .vectors, "ax"
57 809 simons 
.endif
58 
 
59 
_reset:
60 
.if IN_FLASH
61 817 simons 
        l.movhi r3,hi(MC_BASE_ADDR)
62 809 simons 
        l.ori   r3,r3,MC_BA_MASK
63 
        l.addi  r5,r0,0x00
64 
        l.sw    0(r3),r5
65 
.endif
66 817 simons 
        l.movhi r3,hi(_start)
67 809 simons 
        l.ori   r3,r3,lo(_start)
68 
        l.jr    r3
69 
        l.nop
70 
 
71 
.if IN_FLASH
72 
        .section .vectors, "ax"
73 
.endif
74 817 simons 
        .org 0x600
75 809 simons 
 
76 817 simons 
        l.j     _align
77 
        l.nop
78 
 
79 
        .org 0x800
80 
 
81 809 simons 
        l.j     _int_wrapper
82 
        l.nop
83 
 
84 
        .section .text
85 
 
86 
_start:
87 
.if IN_FLASH
88 
        l.jal   _init_mc
89 
        l.nop
90 
 
91 
        /* Wait for SDRAM */
92 
        l.addi  r3,r0,0x0000  /* igor zmanjsal iz 0x7fff na 0x0000 */
93 
1:      l.sfeqi r3,0
94 
        l.bnf   1b
95 
        l.addi  r3,r3,-1
96 
.endif
97 817 simons 
        /* Copy form flash to sram */
98 809 simons 
.if IN_FLASH
99 
        l.movhi r3,hi(_src_beg)
100 
        l.ori   r3,r3,lo(_src_beg)
101 
        l.movhi r4,hi(_vec_start)
102 
        l.ori   r4,r4,lo(_vec_start)
103 
        l.movhi r5,hi(_vec_end)
104 
        l.ori   r5,r5,lo(_vec_end)
105 
        l.sub   r5,r5,r4
106 
        l.sfeqi r5,0
107 
        l.bf    2f
108 
        l.nop
109 
1:      l.lwz   r6,0(r3)
110 
        l.sw    0(r4),r6
111 
        l.addi  r3,r3,4
112 
        l.addi  r4,r4,4
113 
        l.addi  r5,r5,-4
114 
        l.sfgtsi r5,0
115 817 simons 
        l.bf    1b
116 809 simons 
        l.nop
117 
2:
118 
        l.movhi r4,hi(_dst_beg)
119 
        l.ori   r4,r4,lo(_dst_beg)
120 
        l.movhi r5,hi(_dst_end)
121 
        l.ori   r5,r5,lo(_dst_end)
122 
1:      l.sfgeu r4,r5
123 
        l.bf    1f
124 
        l.nop
125 
        l.lwz   r8,0(r3)
126 
        l.sw    0(r4),r8
127 
        l.addi  r3,r3,4
128 
        l.bnf   1b
129 
        l.addi  r4,r4,4
130 
1:
131 
        l.addi  r3,r0,0
132 
        l.addi  r4,r0,0
133 
3:
134 
.endif
135 
 
136 
.if IC_ENABLE
137 817 simons 
  l.jal _ic_enable
138 
  l.nop
139 809 simons 
.endif
140 
 
141 
.if DC_ENABLE
142 817 simons 
  l.jal _dc_enable
143 
  l.nop
144 809 simons 
.endif
145 
 
146 
        l.movhi r1,hi(_stack-4)
147 
        l.addi  r1,r1,lo(_stack-4)
148 817 simons 
  l.addi  r2,r0,-3
149 
  l.and r1,r1,r2
150 809 simons 
 
151 
        l.movhi r2,hi(_main)
152 
        l.ori   r2,r2,lo(_main)
153 
        l.jr    r2
154 
        l.addi  r2,r0,0
155 
 
156 
_ic_enable:
157 
 
158 
        /* Flush IC */
159 
        l.addi  r10,r0,0
160 
        l.addi  r11,r0,IC_SIZE
161 
1:
162 
        l.mtspr r0,r10,SPR_ICBIR
163 
        l.sfne  r10,r11
164 
        l.bf    1b
165 
        l.addi  r10,r10,16
166 
 
167 
        /* Enable IC */
168 
        l.addi  r10,r0,(SPR_SR_ICE|SPR_SR_SM)
169 
        l.mtspr r0,r10,SPR_SR
170 
        l.nop
171 
        l.nop
172 
        l.nop
173 
        l.nop
174 
        l.nop
175 
 
176 817 simons 
  l.jr  r9
177 
  l.nop
178 809 simons 
 
179 
_dc_enable:
180 
 
181 
        /* Flush DC */
182 
        l.addi  r10,r0,0
183 
        l.addi  r11,r0,DC_SIZE
184 
1:
185 
        l.mtspr r0,r10,SPR_DCBIR
186 
        l.sfne  r10,r11
187 
        l.bf    1b
188 
        l.addi  r10,r10,16
189 
 
190 
        /* Enable DC */
191 
        l.addi  r10,r0,(SPR_SR_DCE|SPR_SR_SM)
192 
        l.mtspr r0,r10,SPR_SR
193 
 
194 817 simons 
  l.jr  r9
195 
  l.nop
196 809 simons 
 
197 
.if IN_FLASH
198 
_init_mc:
199 
 
200 817 simons 
        l.movhi r3,hi(MC_BASE_ADDR)
201 
        l.ori   r3,r3,lo(MC_BASE_ADDR)
202 809 simons 
 
203 
        l.addi  r4,r3,MC_CSC(0)
204 817 simons 
        l.movhi r5,hi(FLASH_BASE_ADDR)
205 809 simons 
        l.srai  r5,r5,5
206 
        l.ori   r5,r5,0x0025
207 
        l.sw    0(r4),r5
208 
 
209 
        l.addi  r4,r3,MC_TMS(0)
210 
        l.movhi r5,hi(FLASH_TMS_VAL)
211 
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
212 
        l.sw    0(r4),r5
213 
 
214 
        l.addi  r4,r3,MC_BA_MASK
215 
        l.addi  r5,r0,MC_MASK_VAL
216 
        l.sw    0(r4),r5
217 
 
218 
        l.addi  r4,r3,MC_CSR
219 
        l.movhi r5,hi(MC_CSR_VAL)
220 
        l.ori   r5,r5,lo(MC_CSR_VAL)
221 
        l.sw    0(r4),r5
222 
 
223 
        l.addi  r4,r3,MC_TMS(1)
224 
        l.movhi r5,hi(SDRAM_TMS_VAL)
225 
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
226 
        l.sw    0(r4),r5
227 
 
228 
        l.addi  r4,r3,MC_CSC(1)
229 817 simons 
        l.movhi r5,hi(SDRAM_BASE_ADDR)
230 809 simons 
        l.srai  r5,r5,5
231 
        l.ori   r5,r5,0x0411
232 
        l.sw    0(r4),r5
233 
 
234 
        l.jr    r9
235 
        l.nop
236 
.endif
237 
 
238 
_int_wrapper:
239 
        l.addi  r1,r1,-128
240 
 
241 
        l.sw    0x4(r1),r2
242 
        l.sw    0x8(r1),r4
243 
        l.sw    0xc(r1),r5
244 
        l.sw    0x10(r1),r6
245 
        l.sw    0x14(r1),r7
246 
        l.sw    0x18(r1),r8
247 
        l.sw    0x1c(r1),r9
248 
        l.sw    0x20(r1),r10
249 
        l.sw    0x24(r1),r11
250 
        l.sw    0x28(r1),r12
251 
        l.sw    0x2c(r1),r13
252 
        l.sw    0x30(r1),r14
253 
        l.sw    0x34(r1),r15
254 
        l.sw    0x38(r1),r16
255 
        l.sw    0x3c(r1),r17
256 
        l.sw    0x40(r1),r18
257 
        l.sw    0x44(r1),r19
258 
        l.sw    0x48(r1),r20
259 
        l.sw    0x4c(r1),r21
260 
        l.sw    0x50(r1),r22
261 
        l.sw    0x54(r1),r23
262 
        l.sw    0x58(r1),r24
263 
        l.sw    0x5c(r1),r25
264 
        l.sw    0x60(r1),r26
265 
        l.sw    0x64(r1),r27
266 
        l.sw    0x68(r1),r28
267 
        l.sw    0x6c(r1),r29
268 
        l.sw    0x70(r1),r30
269 
        l.sw    0x74(r1),r31
270 
        l.sw    0x78(r1),r3
271 
 
272 
        l.movhi r3,hi(_eth_int)
273 
        l.ori   r3,r3,lo(_eth_int)
274 
        l.jalr  r3
275 
        l.nop
276 
 
277 
        l.lwz   r2,0x4(r1)
278 
        l.lwz   r4,0x8(r1)
279 
        l.lwz   r5,0xc(r1)
280 
        l.lwz   r6,0x10(r1)
281 
        l.lwz   r7,0x14(r1)
282 
        l.lwz   r8,0x18(r1)
283 
        l.lwz   r9,0x1c(r1)
284 
        l.lwz   r10,0x20(r1)
285 
        l.lwz   r11,0x24(r1)
286 
        l.lwz   r12,0x28(r1)
287 
        l.lwz   r13,0x2c(r1)
288 
        l.lwz   r14,0x30(r1)
289 
        l.lwz   r15,0x34(r1)
290 
        l.lwz   r16,0x38(r1)
291 
        l.lwz   r17,0x3c(r1)
292 
        l.lwz   r18,0x40(r1)
293 
        l.lwz   r19,0x44(r1)
294 
        l.lwz   r20,0x48(r1)
295 
        l.lwz   r21,0x4c(r1)
296 
        l.lwz   r22,0x50(r1)
297 
        l.lwz   r23,0x54(r1)
298 
        l.lwz   r24,0x58(r1)
299 
        l.lwz   r25,0x5c(r1)
300 
        l.lwz   r26,0x60(r1)
301 
        l.lwz   r27,0x64(r1)
302 
        l.lwz   r28,0x68(r1)
303 
        l.lwz   r29,0x6c(r1)
304 
        l.lwz   r30,0x70(r1)
305 
        l.lwz   r31,0x74(r1)
306 
#        l.lwz   r3,0x78(r1)
307 
 
308 
        l.mtspr r0,r0,SPR_PICSR
309 
 
310 
        l.mfspr r3,r0,SPR_ESR_BASE
311 
        l.ori   r3,r3,SPR_SR_IEE
312 
        l.mtspr r0,r3,SPR_ESR_BASE
313 
 
314 
        l.lwz   r3,0x78(r1)
315 
 
316 
        l.addi  r1,r1,128
317 
        l.rfe
318 
        l.nop
319 
 
320 817 simons 
_align:
321 
        l.addi  r1,r1,-128
322 
        l.sw    0x08(r1),r2
323 
        l.sw    0x0c(r1),r3
324 
        l.sw    0x10(r1),r4
325 
        l.sw    0x14(r1),r5
326 
        l.sw    0x18(r1),r6
327 
        l.sw    0x1c(r1),r7
328 
        l.sw    0x20(r1),r8
329 
        l.sw    0x24(r1),r9
330 
        l.sw    0x28(r1),r10
331 
        l.sw    0x2c(r1),r11
332 
        l.sw    0x30(r1),r12
333 
        l.sw    0x34(r1),r13
334 
        l.sw    0x38(r1),r14
335 
        l.sw    0x3c(r1),r15
336 
        l.sw    0x40(r1),r16
337 
        l.sw    0x44(r1),r17
338 
        l.sw    0x48(r1),r18
339 
        l.sw    0x4c(r1),r19
340 
        l.sw    0x50(r1),r20
341 
        l.sw    0x54(r1),r21
342 
        l.sw    0x58(r1),r22
343 
        l.sw    0x5c(r1),r23
344 
        l.sw    0x60(r1),r24
345 
        l.sw    0x64(r1),r25
346 
        l.sw    0x68(r1),r26
347 
        l.sw    0x6c(r1),r27
348 
        l.sw    0x70(r1),r28
349 
        l.sw    0x74(r1),r29
350 
        l.sw    0x78(r1),r30
351 
        l.sw    0x7c(r1),r31
352 
 
353 
        l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */
354 
        l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
355 
 
356 
        l.lwz r3,0(r5)      /* Load insn */
357 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
358 
 
359 
        l.sfeqi r4,0x00     /* Check if the load/store insn is in delay slot */
360 
        l.bf  jmp
361 
        l.sfeqi r4,0x01
362 
        l.bf  jmp
363 
        l.sfeqi r4,0x03
364 
        l.bf  jmp
365 
        l.sfeqi r4,0x04
366 
        l.bf  jmp
367 
        l.sfeqi r4,0x11
368 
        l.bf  jr
369 
        l.sfeqi r4,0x12
370 
        l.bf  jr
371 
        l.nop
372 
        l.j 1f
373 
        l.addi  r5,r5,4     /* Increment PC to get return insn address */
374 
 
375 
jmp:
376 
        l.slli  r4,r3,6     /* Get the signed extended jump length */
377 
        l.srai  r4,r4,4
378 
 
379 
        l.lwz r3,4(r5)      /* Load the real load/store insn */
380 
 
381 
        l.add r5,r5,r4      /* Calculate jump target address */
382 
 
383 
        l.j 1f
384 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
385 
 
386 
jr:
387 
        l.slli  r4,r3,9     /* Shift to get the reg nb */
388 
        l.andi  r4,r4,0x7c
389 
 
390 
        l.lwz r3,4(r5)    /* Load the real load/store insn */
391 
 
392 
        l.add r4,r4,r1    /* Load the jump register value from the stack */
393 
        l.lwz r5,0(r4)
394 
 
395 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
396 
 
397 
 
398 
1:      l.mtspr r0,r5,SPR_EPCR_BASE
399 
 
400 
        l.sfeqi r4,0x26
401 
        l.bf  lhs
402 
        l.sfeqi r4,0x25
403 
        l.bf  lhz
404 
        l.sfeqi r4,0x22
405 
        l.bf  lws
406 
        l.sfeqi r4,0x21
407 
        l.bf  lwz
408 
        l.sfeqi r4,0x37
409 
        l.bf  sh
410 
        l.sfeqi r4,0x35
411 
        l.bf  sw
412 
        l.nop
413 
 
414 
1:      l.j 1b      /* I don't know what to do */
415 
        l.nop
416 
 
417 
lhs:    l.lbs r5,0(r2)
418 
        l.slli  r5,r5,8
419 
        l.lbz r6,1(r2)
420 
        l.or  r5,r5,r6
421 
        l.srli  r4,r3,19
422 
        l.andi  r4,r4,0x7c
423 
        l.add r4,r4,r1
424 
        l.j align_end
425 
        l.sw  0(r4),r5
426 
 
427 
lhz:    l.lbz r5,0(r2)
428 
        l.slli  r5,r5,8
429 
        l.lbz r6,1(r2)
430 
        l.or  r5,r5,r6
431 
        l.srli  r4,r3,19
432 
        l.andi  r4,r4,0x7c
433 
        l.add r4,r4,r1
434 
        l.j align_end
435 
        l.sw  0(r4),r5
436 
 
437 
lws:    l.lbs r5,0(r2)
438 
        l.slli  r5,r5,24
439 
        l.lbz r6,1(r2)
440 
        l.slli  r6,r6,16
441 
        l.or  r5,r5,r6
442 
        l.lbz r6,2(r2)
443 
        l.slli  r6,r6,8
444 
        l.or  r5,r5,r6
445 
        l.lbz r6,3(r2)
446 
        l.or  r5,r5,r6
447 
        l.srli  r4,r3,19
448 
        l.andi  r4,r4,0x7c
449 
        l.add r4,r4,r1
450 
        l.j align_end
451 
        l.sw  0(r4),r5
452 
 
453 
lwz:    l.lbz r5,0(r2)
454 
        l.slli  r5,r5,24
455 
        l.lbz r6,1(r2)
456 
        l.slli  r6,r6,16
457 
        l.or  r5,r5,r6
458 
        l.lbz r6,2(r2)
459 
        l.slli  r6,r6,8
460 
        l.or  r5,r5,r6
461 
        l.lbz r6,3(r2)
462 
        l.or  r5,r5,r6
463 
        l.srli  r4,r3,19
464 
        l.andi  r4,r4,0x7c
465 
        l.add r4,r4,r1
466 
        l.j align_end
467 
        l.sw  0(r4),r5
468 
 
469 
sh:
470 
        l.srli  r4,r3,9
471 
        l.andi  r4,r4,0x7c
472 
        l.add r4,r4,r1
473 
        l.lwz r5,0(r4)
474 
        l.sb  1(r2),r5
475 
        l.slli  r5,r5,8
476 
        l.j align_end
477 
        l.sb  0(r2),r5
478 
 
479 
sw:
480 
        l.srli  r4,r3,9
481 
        l.andi  r4,r4,0x7c
482 
        l.add r4,r4,r1
483 
        l.lwz r5,0(r4)
484 
        l.sb  3(r2),r5
485 
        l.slli  r5,r5,8
486 
        l.sb  2(r2),r5
487 
        l.slli  r5,r5,8
488 
        l.sb  1(r2),r5
489 
        l.slli  r5,r5,8
490 
        l.j align_end
491 
        l.sb  0(r2),r5
492 
 
493 
align_end:
494 
        l.lwz   r2,0x08(r1)
495 
        l.lwz   r3,0x0c(r1)
496 
        l.lwz   r4,0x10(r1)
497 
        l.lwz   r5,0x14(r1)
498 
        l.lwz   r6,0x18(r1)
499 
        l.lwz   r7,0x1c(r1)
500 
        l.lwz   r8,0x20(r1)
501 
        l.lwz   r9,0x24(r1)
502 
        l.lwz   r10,0x28(r1)
503 
        l.lwz   r11,0x2c(r1)
504 
        l.lwz   r12,0x30(r1)
505 
        l.lwz   r13,0x34(r1)
506 
        l.lwz   r14,0x38(r1)
507 
        l.lwz   r15,0x3c(r1)
508 
        l.lwz   r16,0x40(r1)
509 
        l.lwz   r17,0x44(r1)
510 
        l.lwz   r18,0x48(r1)
511 
        l.lwz   r19,0x4c(r1)
512 
        l.lwz   r20,0x50(r1)
513 
        l.lwz   r21,0x54(r1)
514 
        l.lwz   r22,0x58(r1)
515 
        l.lwz   r23,0x5c(r1)
516 
        l.lwz   r24,0x60(r1)
517 
        l.lwz   r25,0x64(r1)
518 
        l.lwz   r26,0x68(r1)
519 
        l.lwz   r27,0x6c(r1)
520 
        l.lwz   r28,0x70(r1)
521 
        l.lwz   r29,0x74(r1)
522 
        l.lwz   r30,0x78(r1)
523 
        l.lwz   r31,0x7c(r1)
524 
        l.addi  r1,r1,128
525 
        l.rfe
526 
 
527 809 simons 
        .section .text
528 
_lolev_ie:
529 
        l.mfspr r3,r0,SPR_SR
530 
        l.ori   r3,r3,SPR_SR_IEE
531 
        l.mtspr r0,r3,SPR_SR
532 817 simons 
        l.movhi r3,hi(ETH0_INT)
533 
  l.ori r3,r3,lo(ETH0_INT)
534 809 simons 
        l.mtspr r0,r3,SPR_PICMR
535 
 
536 
        l.jr    r9
537 
        l.nop
538 
 
539 
_lolev_idis:
540 
        l.mtspr r0,r0,SPR_PICMR
541 
 
542 
        l.jr    r9
543 
        l.nop

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