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[/] [or1k/] [trunk/] [orpmon/] [reset.S] - Blame information for rev 834

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Line No. Rev Author Line
1 809 simons 
#include "spr_defs.h"
2 
#include "board.h"
3 
#include "mc.h"
4 
 
5 
 
6 
 
7 
        .extern _reset_support
8 
        .extern _eth_int
9 
        .extern _src_beg
10 
        .extern _dst_beg
11 
        .extern _dst_end
12 
        .extern _c_reset
13 
        .extern _int_main
14 833 simons 
        .extern _tick_interrupt
15 820 markom 
        .extern _crc32
16 816 markom 
 
17 
        /* Used by global.src_addr for default value */
18 
        .extern _src_addr
19 809 simons 
 
20 
        .global _lolev_ie
21 
        .global _lolev_idis
22 817 simons 
        .global _align
23 820 markom 
        .global _calc_mycrc32
24 822 markom 
        .global _mycrc32
25 
        .global _mysize
26 809 simons 
 
27 817 simons 
        .section .stack, "aw", @nobits
28 
.space  STACK_SIZE
29 809 simons 
_stack:
30 834 simons 
        .section .crc
31 820 markom 
_mycrc32:
32 833 simons 
        .word   0xcccccccc
33 820 markom 
_mysize:
34 
        .word 0xdddddddd
35 809 simons 
 
36 829 markom 
.if SELF_CHECK
37 820 markom 
_calc_mycrc32:
38 833 simons 
        l.addi  r3,r0,0
39 820 markom 
        l.movhi r4,hi(_calc_mycrc32)
40 
        l.ori   r4,r4,lo(_calc_mycrc32)
41 
        l.movhi r5,hi(_mysize)
42 
        l.ori   r5,r5,lo(_mysize)
43 
        l.lwz   r5,0(r5)
44 822 markom 
        l.addi  r1,r1,-4
45 833 simons 
        l.sw    0(r1),r9
46 820 markom 
 
47 
        /* unsigned long crc32 (unsigned long crc, const unsigned char *buf, unsigned long len); */
48 833 simons 
        l.jal           _crc32
49 
        l.nop
50 
 
51 
        l.movhi r3,hi(_mycrc32)
52 820 markom 
        l.ori   r3,r3,lo(_mycrc32)
53 
        l.lwz   r3,0(r3)
54 
 
55 833 simons 
        l.xor     r11,r3,r11
56 822 markom 
        l.lwz   r9,0(r1)
57 
        l.jr    r9
58 
        l.addi  r1,r1,4
59 829 markom 
.endif
60 
 
61 833 simons 
        .org 0x100
62 809 simons 
.if IN_FLASH
63 
        .section .reset, "ax"
64 
.else
65 817 simons 
        .section .vectors, "ax"
66 809 simons 
.endif
67 
 
68 
_reset:
69 
.if IN_FLASH
70 817 simons 
        l.movhi r3,hi(MC_BASE_ADDR)
71 809 simons 
        l.ori   r3,r3,MC_BA_MASK
72 
        l.addi  r5,r0,0x00
73 
        l.sw    0(r3),r5
74 
.endif
75 833 simons 
        l.movhi r3,hi(_start)
76 
        l.ori   r3,r3,lo(_start)
77 829 markom 
        l.jr    r3
78 833 simons 
        l.nop
79 809 simons 
 
80 
.if IN_FLASH
81 
        .section .vectors, "ax"
82 833 simons 
        .org 0x500
83 
.else
84 
        .org (0x500 - 0x100 + _reset)
85 
.endif
86 
 
87 
        l.j     _tick
88 
        l.nop
89 
 
90 
.if IN_FLASH
91 
        .section .vectors, "ax"
92 824 markom 
        .org 0x600
93 
.else
94 
        .org (0x600 - 0x100 + _reset)
95 809 simons 
.endif
96 
 
97 817 simons 
        l.j     _align
98 
        l.nop
99 
 
100 824 markom 
.if IN_FLASH
101 817 simons 
        .org 0x800
102 824 markom 
.else
103 
        .org (0x800 - 0x100 + _reset)
104 
.endif
105 817 simons 
 
106 809 simons 
        l.j     _int_wrapper
107 
        l.nop
108 
 
109 
        .section .text
110 833 simons 
_start:
111 809 simons 
.if IN_FLASH
112 
        l.jal   _init_mc
113 
        l.nop
114 
 
115 
        /* Wait for SDRAM */
116 833 simons 
        l.addi  r3,r0,0x1000
117 809 simons 
1:      l.sfeqi r3,0
118 
        l.bnf   1b
119 
        l.addi  r3,r3,-1
120 
.endif
121 817 simons 
        /* Copy form flash to sram */
122 809 simons 
.if IN_FLASH
123 
        l.movhi r3,hi(_src_beg)
124 
        l.ori   r3,r3,lo(_src_beg)
125 
        l.movhi r4,hi(_vec_start)
126 
        l.ori   r4,r4,lo(_vec_start)
127 
        l.movhi r5,hi(_vec_end)
128 
        l.ori   r5,r5,lo(_vec_end)
129 
        l.sub   r5,r5,r4
130 
        l.sfeqi r5,0
131 
        l.bf    2f
132 
        l.nop
133 
1:      l.lwz   r6,0(r3)
134 
        l.sw    0(r4),r6
135 
        l.addi  r3,r3,4
136 
        l.addi  r4,r4,4
137 
        l.addi  r5,r5,-4
138 
        l.sfgtsi r5,0
139 817 simons 
        l.bf    1b
140 809 simons 
        l.nop
141 
2:
142 
        l.movhi r4,hi(_dst_beg)
143 
        l.ori   r4,r4,lo(_dst_beg)
144 
        l.movhi r5,hi(_dst_end)
145 
        l.ori   r5,r5,lo(_dst_end)
146 
1:      l.sfgeu r4,r5
147 
        l.bf    1f
148 
        l.nop
149 
        l.lwz   r8,0(r3)
150 
        l.sw    0(r4),r8
151 
        l.addi  r3,r3,4
152 
        l.bnf   1b
153 
        l.addi  r4,r4,4
154 
1:
155 
        l.addi  r3,r0,0
156 
        l.addi  r4,r0,0
157 
3:
158 
.endif
159 
 
160 
.if IC_ENABLE
161 833 simons 
        l.jal   _ic_enable
162 
        l.nop
163 809 simons 
.endif
164 
 
165 
.if DC_ENABLE
166 833 simons 
        l.jal   _dc_enable
167 
        l.nop
168 809 simons 
.endif
169 
 
170 
        l.movhi r1,hi(_stack-4)
171 
        l.addi  r1,r1,lo(_stack-4)
172 833 simons 
        l.addi  r2,r0,-3
173 
        l.and   r1,r1,r2
174 809 simons 
 
175 
        l.movhi r2,hi(_main)
176 
        l.ori   r2,r2,lo(_main)
177 
        l.jr    r2
178 
        l.addi  r2,r0,0
179 
 
180 
_ic_enable:
181 
 
182 
        /* Flush IC */
183 
        l.addi  r10,r0,0
184 
        l.addi  r11,r0,IC_SIZE
185 
1:
186 
        l.mtspr r0,r10,SPR_ICBIR
187 
        l.sfne  r10,r11
188 
        l.bf    1b
189 
        l.addi  r10,r10,16
190 
 
191 
        /* Enable IC */
192 
        l.addi  r10,r0,(SPR_SR_ICE|SPR_SR_SM)
193 
        l.mtspr r0,r10,SPR_SR
194 
        l.nop
195 
        l.nop
196 
        l.nop
197 
        l.nop
198 
        l.nop
199 
 
200 833 simons 
        l.jr    r9
201 
        l.nop
202 809 simons 
 
203 
_dc_enable:
204 
 
205 
        /* Flush DC */
206 
        l.addi  r10,r0,0
207 
        l.addi  r11,r0,DC_SIZE
208 
1:
209 
        l.mtspr r0,r10,SPR_DCBIR
210 
        l.sfne  r10,r11
211 
        l.bf    1b
212 
        l.addi  r10,r10,16
213 
 
214 
        /* Enable DC */
215 
        l.addi  r10,r0,(SPR_SR_DCE|SPR_SR_SM)
216 
        l.mtspr r0,r10,SPR_SR
217 
 
218 833 simons 
        l.jr    r9
219 
        l.nop
220 809 simons 
 
221 
.if IN_FLASH
222 
_init_mc:
223 
 
224 817 simons 
        l.movhi r3,hi(MC_BASE_ADDR)
225 
        l.ori   r3,r3,lo(MC_BASE_ADDR)
226 809 simons 
 
227 
        l.addi  r4,r3,MC_CSC(0)
228 817 simons 
        l.movhi r5,hi(FLASH_BASE_ADDR)
229 809 simons 
        l.srai  r5,r5,5
230 
        l.ori   r5,r5,0x0025
231 
        l.sw    0(r4),r5
232 
 
233 
        l.addi  r4,r3,MC_TMS(0)
234 
        l.movhi r5,hi(FLASH_TMS_VAL)
235 
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
236 
        l.sw    0(r4),r5
237 
 
238 
        l.addi  r4,r3,MC_BA_MASK
239 
        l.addi  r5,r0,MC_MASK_VAL
240 
        l.sw    0(r4),r5
241 
 
242 
        l.addi  r4,r3,MC_CSR
243 
        l.movhi r5,hi(MC_CSR_VAL)
244 
        l.ori   r5,r5,lo(MC_CSR_VAL)
245 
        l.sw    0(r4),r5
246 
 
247 
        l.addi  r4,r3,MC_TMS(1)
248 
        l.movhi r5,hi(SDRAM_TMS_VAL)
249 
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
250 
        l.sw    0(r4),r5
251 
 
252 
        l.addi  r4,r3,MC_CSC(1)
253 817 simons 
        l.movhi r5,hi(SDRAM_BASE_ADDR)
254 809 simons 
        l.srai  r5,r5,5
255 
        l.ori   r5,r5,0x0411
256 
        l.sw    0(r4),r5
257 
 
258 833 simons 
#ifdef ETH_DATA_BASE
259 
        l.addi  r4,r3,MC_CSC(2)
260 
        l.movhi r5,hi(ETH_DATA_BASE)
261 
        l.srai  r5,r5,5
262 
        l.ori   r5,r5,0x0005
263 
        l.sw    0(r4),r5
264 
 
265 
        l.addi  r4,r3,MC_TMS(2)
266 
        l.movhi r5,0xffff
267 
        l.ori   r5,r5,0xffff
268 
        l.sw    0(r4),r5
269 
#endif
270 
 
271 809 simons 
        l.jr    r9
272 
        l.nop
273 
.endif
274 
 
275 833 simons 
_tick:
276 
        l.addi  r1,r1,-128
277 
 
278 
        l.sw    0x4(r1),r2
279 
        l.sw    0x8(r1),r4
280 
        l.sw    0xc(r1),r5
281 
        l.sw    0x10(r1),r6
282 
        l.sw    0x14(r1),r7
283 
        l.sw    0x18(r1),r8
284 
        l.sw    0x1c(r1),r9
285 
        l.sw    0x20(r1),r10
286 
        l.sw    0x24(r1),r11
287 
        l.sw    0x28(r1),r12
288 
        l.sw    0x2c(r1),r13
289 
        l.sw    0x30(r1),r14
290 
        l.sw    0x34(r1),r15
291 
        l.sw    0x38(r1),r16
292 
        l.sw    0x3c(r1),r17
293 
        l.sw    0x40(r1),r18
294 
        l.sw    0x44(r1),r19
295 
        l.sw    0x48(r1),r20
296 
        l.sw    0x4c(r1),r21
297 
        l.sw    0x50(r1),r22
298 
        l.sw    0x54(r1),r23
299 
        l.sw    0x58(r1),r24
300 
        l.sw    0x5c(r1),r25
301 
        l.sw    0x60(r1),r26
302 
        l.sw    0x64(r1),r27
303 
        l.sw    0x68(r1),r28
304 
        l.sw    0x6c(r1),r29
305 
        l.sw    0x70(r1),r30
306 
        l.sw    0x74(r1),r31
307 
        l.sw    0x78(r1),r3
308 
 
309 
        l.movhi r3,hi(_tick_interrupt)
310 
        l.ori   r3,r3,lo(_tick_interrupt)
311 
        l.jalr  r3
312 
        l.nop
313 
 
314 
        l.lwz   r2,0x4(r1)
315 
        l.lwz   r4,0x8(r1)
316 
        l.lwz   r5,0xc(r1)
317 
        l.lwz   r6,0x10(r1)
318 
        l.lwz   r7,0x14(r1)
319 
        l.lwz   r8,0x18(r1)
320 
        l.lwz   r9,0x1c(r1)
321 
        l.lwz   r10,0x20(r1)
322 
        l.lwz   r11,0x24(r1)
323 
        l.lwz   r12,0x28(r1)
324 
        l.lwz   r13,0x2c(r1)
325 
        l.lwz   r14,0x30(r1)
326 
        l.lwz   r15,0x34(r1)
327 
        l.lwz   r16,0x38(r1)
328 
        l.lwz   r17,0x3c(r1)
329 
        l.lwz   r18,0x40(r1)
330 
        l.lwz   r19,0x44(r1)
331 
        l.lwz   r20,0x48(r1)
332 
        l.lwz   r21,0x4c(r1)
333 
        l.lwz   r22,0x50(r1)
334 
        l.lwz   r23,0x54(r1)
335 
        l.lwz   r24,0x58(r1)
336 
        l.lwz   r25,0x5c(r1)
337 
        l.lwz   r26,0x60(r1)
338 
        l.lwz   r27,0x64(r1)
339 
        l.lwz   r28,0x68(r1)
340 
        l.lwz   r29,0x6c(r1)
341 
        l.lwz   r30,0x70(r1)
342 
        l.mfspr r31,r0,0x40
343 
        l.lwz   r31,0x74(r1)
344 
        l.lwz   r3,0x78(r1)
345 
 
346 
        l.addi  r1,r1,128
347 
        l.rfe
348 
        l.nop
349 
 
350 809 simons 
_int_wrapper:
351 
        l.addi  r1,r1,-128
352 
 
353 
        l.sw    0x4(r1),r2
354 
        l.sw    0x8(r1),r4
355 
        l.sw    0xc(r1),r5
356 
        l.sw    0x10(r1),r6
357 
        l.sw    0x14(r1),r7
358 
        l.sw    0x18(r1),r8
359 
        l.sw    0x1c(r1),r9
360 
        l.sw    0x20(r1),r10
361 
        l.sw    0x24(r1),r11
362 
        l.sw    0x28(r1),r12
363 
        l.sw    0x2c(r1),r13
364 
        l.sw    0x30(r1),r14
365 
        l.sw    0x34(r1),r15
366 
        l.sw    0x38(r1),r16
367 
        l.sw    0x3c(r1),r17
368 
        l.sw    0x40(r1),r18
369 
        l.sw    0x44(r1),r19
370 
        l.sw    0x48(r1),r20
371 
        l.sw    0x4c(r1),r21
372 
        l.sw    0x50(r1),r22
373 
        l.sw    0x54(r1),r23
374 
        l.sw    0x58(r1),r24
375 
        l.sw    0x5c(r1),r25
376 
        l.sw    0x60(r1),r26
377 
        l.sw    0x64(r1),r27
378 
        l.sw    0x68(r1),r28
379 
        l.sw    0x6c(r1),r29
380 
        l.sw    0x70(r1),r30
381 
        l.sw    0x74(r1),r31
382 
        l.sw    0x78(r1),r3
383 
 
384 
        l.movhi r3,hi(_eth_int)
385 
        l.ori   r3,r3,lo(_eth_int)
386 
        l.jalr  r3
387 
        l.nop
388 
 
389 
        l.lwz   r2,0x4(r1)
390 
        l.lwz   r4,0x8(r1)
391 
        l.lwz   r5,0xc(r1)
392 
        l.lwz   r6,0x10(r1)
393 
        l.lwz   r7,0x14(r1)
394 
        l.lwz   r8,0x18(r1)
395 
        l.lwz   r9,0x1c(r1)
396 
        l.lwz   r10,0x20(r1)
397 
        l.lwz   r11,0x24(r1)
398 
        l.lwz   r12,0x28(r1)
399 
        l.lwz   r13,0x2c(r1)
400 
        l.lwz   r14,0x30(r1)
401 
        l.lwz   r15,0x34(r1)
402 
        l.lwz   r16,0x38(r1)
403 
        l.lwz   r17,0x3c(r1)
404 
        l.lwz   r18,0x40(r1)
405 
        l.lwz   r19,0x44(r1)
406 
        l.lwz   r20,0x48(r1)
407 
        l.lwz   r21,0x4c(r1)
408 
        l.lwz   r22,0x50(r1)
409 
        l.lwz   r23,0x54(r1)
410 
        l.lwz   r24,0x58(r1)
411 
        l.lwz   r25,0x5c(r1)
412 
        l.lwz   r26,0x60(r1)
413 
        l.lwz   r27,0x64(r1)
414 
        l.lwz   r28,0x68(r1)
415 
        l.lwz   r29,0x6c(r1)
416 
        l.lwz   r30,0x70(r1)
417 
        l.lwz   r31,0x74(r1)
418 833 simons 
        l.lwz   r3,0x78(r1)
419 809 simons 
 
420 
        l.mtspr r0,r0,SPR_PICSR
421 
 
422 
        l.addi  r1,r1,128
423 
        l.rfe
424 
        l.nop
425 
 
426 817 simons 
_align:
427 
        l.addi  r1,r1,-128
428 
        l.sw    0x08(r1),r2
429 
        l.sw    0x0c(r1),r3
430 
        l.sw    0x10(r1),r4
431 
        l.sw    0x14(r1),r5
432 
        l.sw    0x18(r1),r6
433 
        l.sw    0x1c(r1),r7
434 
        l.sw    0x20(r1),r8
435 
        l.sw    0x24(r1),r9
436 
        l.sw    0x28(r1),r10
437 
        l.sw    0x2c(r1),r11
438 
        l.sw    0x30(r1),r12
439 
        l.sw    0x34(r1),r13
440 
        l.sw    0x38(r1),r14
441 
        l.sw    0x3c(r1),r15
442 
        l.sw    0x40(r1),r16
443 
        l.sw    0x44(r1),r17
444 
        l.sw    0x48(r1),r18
445 
        l.sw    0x4c(r1),r19
446 
        l.sw    0x50(r1),r20
447 
        l.sw    0x54(r1),r21
448 
        l.sw    0x58(r1),r22
449 
        l.sw    0x5c(r1),r23
450 
        l.sw    0x60(r1),r24
451 
        l.sw    0x64(r1),r25
452 
        l.sw    0x68(r1),r26
453 
        l.sw    0x6c(r1),r27
454 
        l.sw    0x70(r1),r28
455 
        l.sw    0x74(r1),r29
456 
        l.sw    0x78(r1),r30
457 
        l.sw    0x7c(r1),r31
458 
 
459 
        l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */
460 
        l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
461 
 
462 833 simons 
        l.lwz   r3,0(r5)    /* Load insn */
463 817 simons 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
464 
 
465 
        l.sfeqi r4,0x00     /* Check if the load/store insn is in delay slot */
466 833 simons 
        l.bf    jmp
467 817 simons 
        l.sfeqi r4,0x01
468 833 simons 
        l.bf    jmp
469 817 simons 
        l.sfeqi r4,0x03
470 833 simons 
        l.bf    jmp
471 817 simons 
        l.sfeqi r4,0x04
472 833 simons 
        l.bf    jmp
473 817 simons 
        l.sfeqi r4,0x11
474 833 simons 
        l.bf    jr
475 817 simons 
        l.sfeqi r4,0x12
476 833 simons 
        l.bf    jr
477 817 simons 
        l.nop
478 833 simons 
        l.j     1f
479 817 simons 
        l.addi  r5,r5,4     /* Increment PC to get return insn address */
480 
 
481 
jmp:
482 
        l.slli  r4,r3,6     /* Get the signed extended jump length */
483 
        l.srai  r4,r4,4
484 
 
485 833 simons 
        l.lwz   r3,4(r5)      /* Load the real load/store insn */
486 817 simons 
 
487 833 simons 
        l.add   r5,r5,r4      /* Calculate jump target address */
488 817 simons 
 
489 833 simons 
        l.j     1f
490 817 simons 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
491 
 
492 
jr:
493 
        l.slli  r4,r3,9     /* Shift to get the reg nb */
494 
        l.andi  r4,r4,0x7c
495 
 
496 833 simons 
        l.lwz   r3,4(r5)    /* Load the real load/store insn */
497 817 simons 
 
498 833 simons 
        l.add   r4,r4,r1    /* Load the jump register value from the stack */
499 
        l.lwz   r5,0(r4)
500 817 simons 
 
501 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
502 
 
503 
 
504 
1:      l.mtspr r0,r5,SPR_EPCR_BASE
505 
 
506 
        l.sfeqi r4,0x26
507 833 simons 
        l.bf    lhs
508 817 simons 
        l.sfeqi r4,0x25
509 833 simons 
        l.bf    lhz
510 817 simons 
        l.sfeqi r4,0x22
511 833 simons 
        l.bf    lws
512 817 simons 
        l.sfeqi r4,0x21
513 833 simons 
        l.bf    lwz
514 817 simons 
        l.sfeqi r4,0x37
515 833 simons 
        l.bf    sh
516 817 simons 
        l.sfeqi r4,0x35
517 833 simons 
        l.bf    sw
518 817 simons 
        l.nop
519 
 
520 833 simons 
1:      l.j     1b      /* I don't know what to do */
521 817 simons 
        l.nop
522 
 
523 833 simons 
lhs:    l.lbs   r5,0(r2)
524 817 simons 
        l.slli  r5,r5,8
525 833 simons 
        l.lbz   r6,1(r2)
526 
        l.or    r5,r5,r6
527 817 simons 
        l.srli  r4,r3,19
528 
        l.andi  r4,r4,0x7c
529 833 simons 
        l.add   r4,r4,r1
530 
        l.j     align_end
531 
        l.sw    0(r4),r5
532 817 simons 
 
533 833 simons 
lhz:    l.lbz   r5,0(r2)
534 817 simons 
        l.slli  r5,r5,8
535 833 simons 
        l.lbz   r6,1(r2)
536 
        l.or    r5,r5,r6
537 817 simons 
        l.srli  r4,r3,19
538 
        l.andi  r4,r4,0x7c
539 833 simons 
        l.add   r4,r4,r1
540 
        l.j     align_end
541 
        l.sw    0(r4),r5
542 817 simons 
 
543 833 simons 
lws:    l.lbs   r5,0(r2)
544 817 simons 
        l.slli  r5,r5,24
545 833 simons 
        l.lbz   r6,1(r2)
546 817 simons 
        l.slli  r6,r6,16
547 833 simons 
        l.or    r5,r5,r6
548 
        l.lbz   r6,2(r2)
549 817 simons 
        l.slli  r6,r6,8
550 833 simons 
        l.or    r5,r5,r6
551 
        l.lbz   r6,3(r2)
552 
        l.or    r5,r5,r6
553 817 simons 
        l.srli  r4,r3,19
554 
        l.andi  r4,r4,0x7c
555 833 simons 
        l.add   r4,r4,r1
556 
        l.j     align_end
557 
        l.sw    0(r4),r5
558 817 simons 
 
559 833 simons 
lwz:    l.lbz   r5,0(r2)
560 817 simons 
        l.slli  r5,r5,24
561 833 simons 
        l.lbz   r6,1(r2)
562 817 simons 
        l.slli  r6,r6,16
563 833 simons 
        l.or    r5,r5,r6
564 
        l.lbz   r6,2(r2)
565 817 simons 
        l.slli  r6,r6,8
566 833 simons 
        l.or    r5,r5,r6
567 
        l.lbz   r6,3(r2)
568 
        l.or    r5,r5,r6
569 817 simons 
        l.srli  r4,r3,19
570 
        l.andi  r4,r4,0x7c
571 833 simons 
        l.add   r4,r4,r1
572 
        l.j     align_end
573 
        l.sw    0(r4),r5
574 817 simons 
 
575 
sh:
576 
        l.srli  r4,r3,9
577 
        l.andi  r4,r4,0x7c
578 833 simons 
        l.add   r4,r4,r1
579 
        l.lwz   r5,0(r4)
580 
        l.sb    1(r2),r5
581 
        l.srli  r5,r5,8
582 
        l.j     align_end
583 
        l.sb    0(r2),r5
584 817 simons 
 
585 
sw:
586 
        l.srli  r4,r3,9
587 
        l.andi  r4,r4,0x7c
588 833 simons 
        l.add   r4,r4,r1
589 
        l.lwz   r5,0(r4)
590 
        l.sb    3(r2),r5
591 
        l.srli  r5,r5,8
592 
        l.sb    2(r2),r5
593 
        l.srli  r5,r5,8
594 
        l.sb    1(r2),r5
595 
        l.srli  r5,r5,8
596 
        l.j     align_end
597 
        l.sb    0(r2),r5
598 817 simons 
 
599 
align_end:
600 
        l.lwz   r2,0x08(r1)
601 
        l.lwz   r3,0x0c(r1)
602 
        l.lwz   r4,0x10(r1)
603 
        l.lwz   r5,0x14(r1)
604 
        l.lwz   r6,0x18(r1)
605 
        l.lwz   r7,0x1c(r1)
606 
        l.lwz   r8,0x20(r1)
607 
        l.lwz   r9,0x24(r1)
608 
        l.lwz   r10,0x28(r1)
609 
        l.lwz   r11,0x2c(r1)
610 
        l.lwz   r12,0x30(r1)
611 
        l.lwz   r13,0x34(r1)
612 
        l.lwz   r14,0x38(r1)
613 
        l.lwz   r15,0x3c(r1)
614 
        l.lwz   r16,0x40(r1)
615 
        l.lwz   r17,0x44(r1)
616 
        l.lwz   r18,0x48(r1)
617 
        l.lwz   r19,0x4c(r1)
618 
        l.lwz   r20,0x50(r1)
619 
        l.lwz   r21,0x54(r1)
620 
        l.lwz   r22,0x58(r1)
621 
        l.lwz   r23,0x5c(r1)
622 
        l.lwz   r24,0x60(r1)
623 
        l.lwz   r25,0x64(r1)
624 
        l.lwz   r26,0x68(r1)
625 
        l.lwz   r27,0x6c(r1)
626 
        l.lwz   r28,0x70(r1)
627 
        l.lwz   r29,0x74(r1)
628 
        l.lwz   r30,0x78(r1)
629 833 simons 
        l.mfspr r31,r0,0x40
630 817 simons 
        l.lwz   r31,0x7c(r1)
631 
        l.addi  r1,r1,128
632 
        l.rfe
633 
 
634 809 simons 
        .section .text
635 
_lolev_ie:
636 
        l.mfspr r3,r0,SPR_SR
637 
        l.ori   r3,r3,SPR_SR_IEE
638 
        l.mtspr r0,r3,SPR_SR
639 817 simons 
        l.movhi r3,hi(ETH0_INT)
640 
  l.ori r3,r3,lo(ETH0_INT)
641 809 simons 
        l.mtspr r0,r3,SPR_PICMR
642 
 
643 
        l.jr    r9
644 
        l.nop
645 
 
646 
_lolev_idis:
647 
        l.mtspr r0,r0,SPR_PICMR
648 
 
649 
        l.jr    r9
650 
        l.nop

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