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[/] [or1k/] [trunk/] [orpmon/] [reset.S] - Blame information for rev 855

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Line No. Rev Author Line
1 809 simons 
#include "spr_defs.h"
2 
#include "board.h"
3 
#include "mc.h"
4 
 
5 
 
6 
 
7 
        .extern _reset_support
8 
        .extern _eth_int
9 
        .extern _src_beg
10 
        .extern _dst_beg
11 
        .extern _dst_end
12 
        .extern _c_reset
13 
        .extern _int_main
14 833 simons 
        .extern _tick_interrupt
15 820 markom 
        .extern _crc32
16 816 markom 
 
17 
        /* Used by global.src_addr for default value */
18 
        .extern _src_addr
19 809 simons 
 
20 817 simons 
        .global _align
21 820 markom 
        .global _calc_mycrc32
22 822 markom 
        .global _mycrc32
23 
        .global _mysize
24 809 simons 
 
25 817 simons 
        .section .stack, "aw", @nobits
26 
.space  STACK_SIZE
27 809 simons 
_stack:
28 834 simons 
        .section .crc
29 820 markom 
_mycrc32:
30 833 simons 
        .word   0xcccccccc
31 820 markom 
_mysize:
32 
        .word 0xdddddddd
33 809 simons 
 
34 829 markom 
.if SELF_CHECK
35 820 markom 
_calc_mycrc32:
36 833 simons 
        l.addi  r3,r0,0
37 820 markom 
        l.movhi r4,hi(_calc_mycrc32)
38 
        l.ori   r4,r4,lo(_calc_mycrc32)
39 
        l.movhi r5,hi(_mysize)
40 
        l.ori   r5,r5,lo(_mysize)
41 
        l.lwz   r5,0(r5)
42 822 markom 
        l.addi  r1,r1,-4
43 833 simons 
        l.sw    0(r1),r9
44 820 markom 
 
45 
        /* unsigned long crc32 (unsigned long crc, const unsigned char *buf, unsigned long len); */
46 833 simons 
        l.jal           _crc32
47 
        l.nop
48 
 
49 
        l.movhi r3,hi(_mycrc32)
50 820 markom 
        l.ori   r3,r3,lo(_mycrc32)
51 
        l.lwz   r3,0(r3)
52 
 
53 833 simons 
        l.xor     r11,r3,r11
54 822 markom 
        l.lwz   r9,0(r1)
55 
        l.jr    r9
56 
        l.addi  r1,r1,4
57 829 markom 
.endif
58 
 
59 833 simons 
        .org 0x100
60 809 simons 
.if IN_FLASH
61 
        .section .reset, "ax"
62 
.else
63 817 simons 
        .section .vectors, "ax"
64 809 simons 
.endif
65 
 
66 
_reset:
67 
.if IN_FLASH
68 817 simons 
        l.movhi r3,hi(MC_BASE_ADDR)
69 809 simons 
        l.ori   r3,r3,MC_BA_MASK
70 
        l.addi  r5,r0,0x00
71 
        l.sw    0(r3),r5
72 
.endif
73 833 simons 
        l.movhi r3,hi(_start)
74 
        l.ori   r3,r3,lo(_start)
75 829 markom 
        l.jr    r3
76 833 simons 
        l.nop
77 809 simons 
 
78 
.if IN_FLASH
79 
        .section .vectors, "ax"
80 833 simons 
        .org 0x500
81 
.else
82 
        .org (0x500 - 0x100 + _reset)
83 
.endif
84 
 
85 
        l.j     _tick
86 
        l.nop
87 
 
88 
.if IN_FLASH
89 
        .section .vectors, "ax"
90 824 markom 
        .org 0x600
91 
.else
92 
        .org (0x600 - 0x100 + _reset)
93 809 simons 
.endif
94 
 
95 817 simons 
        l.j     _align
96 
        l.nop
97 
 
98 824 markom 
.if IN_FLASH
99 817 simons 
        .org 0x800
100 824 markom 
.else
101 
        .org (0x800 - 0x100 + _reset)
102 
.endif
103 817 simons 
 
104 809 simons 
        l.j     _int_wrapper
105 
        l.nop
106 
 
107 
        .section .text
108 833 simons 
_start:
109 809 simons 
.if IN_FLASH
110 
        l.jal   _init_mc
111 
        l.nop
112 
 
113 
        /* Wait for SDRAM */
114 833 simons 
        l.addi  r3,r0,0x1000
115 809 simons 
1:      l.sfeqi r3,0
116 
        l.bnf   1b
117 
        l.addi  r3,r3,-1
118 
.endif
119 817 simons 
        /* Copy form flash to sram */
120 809 simons 
.if IN_FLASH
121 
        l.movhi r3,hi(_src_beg)
122 
        l.ori   r3,r3,lo(_src_beg)
123 
        l.movhi r4,hi(_vec_start)
124 
        l.ori   r4,r4,lo(_vec_start)
125 
        l.movhi r5,hi(_vec_end)
126 
        l.ori   r5,r5,lo(_vec_end)
127 
        l.sub   r5,r5,r4
128 
        l.sfeqi r5,0
129 
        l.bf    2f
130 
        l.nop
131 
1:      l.lwz   r6,0(r3)
132 
        l.sw    0(r4),r6
133 
        l.addi  r3,r3,4
134 
        l.addi  r4,r4,4
135 
        l.addi  r5,r5,-4
136 
        l.sfgtsi r5,0
137 817 simons 
        l.bf    1b
138 809 simons 
        l.nop
139 
2:
140 
        l.movhi r4,hi(_dst_beg)
141 
        l.ori   r4,r4,lo(_dst_beg)
142 
        l.movhi r5,hi(_dst_end)
143 
        l.ori   r5,r5,lo(_dst_end)
144 
1:      l.sfgeu r4,r5
145 
        l.bf    1f
146 
        l.nop
147 
        l.lwz   r8,0(r3)
148 
        l.sw    0(r4),r8
149 
        l.addi  r3,r3,4
150 
        l.bnf   1b
151 
        l.addi  r4,r4,4
152 
1:
153 
        l.addi  r3,r0,0
154 
        l.addi  r4,r0,0
155 
3:
156 
.endif
157 
 
158 
.if IC_ENABLE
159 833 simons 
        l.jal   _ic_enable
160 
        l.nop
161 809 simons 
.endif
162 
 
163 
.if DC_ENABLE
164 833 simons 
        l.jal   _dc_enable
165 
        l.nop
166 809 simons 
.endif
167 
 
168 
        l.movhi r1,hi(_stack-4)
169 
        l.addi  r1,r1,lo(_stack-4)
170 833 simons 
        l.addi  r2,r0,-3
171 
        l.and   r1,r1,r2
172 809 simons 
 
173 
        l.movhi r2,hi(_main)
174 
        l.ori   r2,r2,lo(_main)
175 
        l.jr    r2
176 
        l.addi  r2,r0,0
177 
 
178 
_ic_enable:
179 
 
180 
        /* Flush IC */
181 
        l.addi  r10,r0,0
182 
        l.addi  r11,r0,IC_SIZE
183 
1:
184 
        l.mtspr r0,r10,SPR_ICBIR
185 
        l.sfne  r10,r11
186 
        l.bf    1b
187 
        l.addi  r10,r10,16
188 
 
189 
        /* Enable IC */
190 
        l.addi  r10,r0,(SPR_SR_ICE|SPR_SR_SM)
191 
        l.mtspr r0,r10,SPR_SR
192 
        l.nop
193 
        l.nop
194 
        l.nop
195 
        l.nop
196 
        l.nop
197 
 
198 833 simons 
        l.jr    r9
199 
        l.nop
200 809 simons 
 
201 
_dc_enable:
202 
 
203 
        /* Flush DC */
204 
        l.addi  r10,r0,0
205 
        l.addi  r11,r0,DC_SIZE
206 
1:
207 
        l.mtspr r0,r10,SPR_DCBIR
208 
        l.sfne  r10,r11
209 
        l.bf    1b
210 
        l.addi  r10,r10,16
211 
 
212 
        /* Enable DC */
213 
        l.addi  r10,r0,(SPR_SR_DCE|SPR_SR_SM)
214 
        l.mtspr r0,r10,SPR_SR
215 
 
216 833 simons 
        l.jr    r9
217 
        l.nop
218 809 simons 
 
219 
.if IN_FLASH
220 
_init_mc:
221 
 
222 817 simons 
        l.movhi r3,hi(MC_BASE_ADDR)
223 
        l.ori   r3,r3,lo(MC_BASE_ADDR)
224 809 simons 
 
225 
        l.addi  r4,r3,MC_CSC(0)
226 817 simons 
        l.movhi r5,hi(FLASH_BASE_ADDR)
227 809 simons 
        l.srai  r5,r5,5
228 
        l.ori   r5,r5,0x0025
229 
        l.sw    0(r4),r5
230 
 
231 
        l.addi  r4,r3,MC_TMS(0)
232 
        l.movhi r5,hi(FLASH_TMS_VAL)
233 
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
234 
        l.sw    0(r4),r5
235 
 
236 
        l.addi  r4,r3,MC_BA_MASK
237 
        l.addi  r5,r0,MC_MASK_VAL
238 
        l.sw    0(r4),r5
239 
 
240 
        l.addi  r4,r3,MC_CSR
241 
        l.movhi r5,hi(MC_CSR_VAL)
242 
        l.ori   r5,r5,lo(MC_CSR_VAL)
243 
        l.sw    0(r4),r5
244 
 
245 
        l.addi  r4,r3,MC_TMS(1)
246 
        l.movhi r5,hi(SDRAM_TMS_VAL)
247 
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
248 
        l.sw    0(r4),r5
249 
 
250 
        l.addi  r4,r3,MC_CSC(1)
251 817 simons 
        l.movhi r5,hi(SDRAM_BASE_ADDR)
252 809 simons 
        l.srai  r5,r5,5
253 
        l.ori   r5,r5,0x0411
254 
        l.sw    0(r4),r5
255 
 
256 833 simons 
#ifdef ETH_DATA_BASE
257 
        l.addi  r4,r3,MC_CSC(2)
258 
        l.movhi r5,hi(ETH_DATA_BASE)
259 
        l.srai  r5,r5,5
260 
        l.ori   r5,r5,0x0005
261 
        l.sw    0(r4),r5
262 
 
263 
        l.addi  r4,r3,MC_TMS(2)
264 
        l.movhi r5,0xffff
265 
        l.ori   r5,r5,0xffff
266 
        l.sw    0(r4),r5
267 
#endif
268 
 
269 809 simons 
        l.jr    r9
270 
        l.nop
271 
.endif
272 
 
273 833 simons 
_tick:
274 
        l.addi  r1,r1,-128
275 
 
276 
        l.sw    0x4(r1),r2
277 
        l.sw    0x8(r1),r4
278 
        l.sw    0xc(r1),r5
279 
        l.sw    0x10(r1),r6
280 
        l.sw    0x14(r1),r7
281 
        l.sw    0x18(r1),r8
282 
        l.sw    0x1c(r1),r9
283 
        l.sw    0x20(r1),r10
284 
        l.sw    0x24(r1),r11
285 
        l.sw    0x28(r1),r12
286 
        l.sw    0x2c(r1),r13
287 
        l.sw    0x30(r1),r14
288 
        l.sw    0x34(r1),r15
289 
        l.sw    0x38(r1),r16
290 
        l.sw    0x3c(r1),r17
291 
        l.sw    0x40(r1),r18
292 
        l.sw    0x44(r1),r19
293 
        l.sw    0x48(r1),r20
294 
        l.sw    0x4c(r1),r21
295 
        l.sw    0x50(r1),r22
296 
        l.sw    0x54(r1),r23
297 
        l.sw    0x58(r1),r24
298 
        l.sw    0x5c(r1),r25
299 
        l.sw    0x60(r1),r26
300 
        l.sw    0x64(r1),r27
301 
        l.sw    0x68(r1),r28
302 
        l.sw    0x6c(r1),r29
303 
        l.sw    0x70(r1),r30
304 
        l.sw    0x74(r1),r31
305 
        l.sw    0x78(r1),r3
306 
 
307 
        l.movhi r3,hi(_tick_interrupt)
308 
        l.ori   r3,r3,lo(_tick_interrupt)
309 
        l.jalr  r3
310 
        l.nop
311 
 
312 
        l.lwz   r2,0x4(r1)
313 
        l.lwz   r4,0x8(r1)
314 
        l.lwz   r5,0xc(r1)
315 
        l.lwz   r6,0x10(r1)
316 
        l.lwz   r7,0x14(r1)
317 
        l.lwz   r8,0x18(r1)
318 
        l.lwz   r9,0x1c(r1)
319 
        l.lwz   r10,0x20(r1)
320 
        l.lwz   r11,0x24(r1)
321 
        l.lwz   r12,0x28(r1)
322 
        l.lwz   r13,0x2c(r1)
323 
        l.lwz   r14,0x30(r1)
324 
        l.lwz   r15,0x34(r1)
325 
        l.lwz   r16,0x38(r1)
326 
        l.lwz   r17,0x3c(r1)
327 
        l.lwz   r18,0x40(r1)
328 
        l.lwz   r19,0x44(r1)
329 
        l.lwz   r20,0x48(r1)
330 
        l.lwz   r21,0x4c(r1)
331 
        l.lwz   r22,0x50(r1)
332 
        l.lwz   r23,0x54(r1)
333 
        l.lwz   r24,0x58(r1)
334 
        l.lwz   r25,0x5c(r1)
335 
        l.lwz   r26,0x60(r1)
336 
        l.lwz   r27,0x64(r1)
337 
        l.lwz   r28,0x68(r1)
338 
        l.lwz   r29,0x6c(r1)
339 
        l.lwz   r30,0x70(r1)
340 
        l.mfspr r31,r0,0x40
341 
        l.lwz   r31,0x74(r1)
342 
        l.lwz   r3,0x78(r1)
343 
 
344 
        l.addi  r1,r1,128
345 
        l.rfe
346 
        l.nop
347 
 
348 809 simons 
_int_wrapper:
349 
        l.addi  r1,r1,-128
350 
 
351 
        l.sw    0x4(r1),r2
352 
        l.sw    0x8(r1),r4
353 
        l.sw    0xc(r1),r5
354 
        l.sw    0x10(r1),r6
355 
        l.sw    0x14(r1),r7
356 
        l.sw    0x18(r1),r8
357 
        l.sw    0x1c(r1),r9
358 
        l.sw    0x20(r1),r10
359 
        l.sw    0x24(r1),r11
360 
        l.sw    0x28(r1),r12
361 
        l.sw    0x2c(r1),r13
362 
        l.sw    0x30(r1),r14
363 
        l.sw    0x34(r1),r15
364 
        l.sw    0x38(r1),r16
365 
        l.sw    0x3c(r1),r17
366 
        l.sw    0x40(r1),r18
367 
        l.sw    0x44(r1),r19
368 
        l.sw    0x48(r1),r20
369 
        l.sw    0x4c(r1),r21
370 
        l.sw    0x50(r1),r22
371 
        l.sw    0x54(r1),r23
372 
        l.sw    0x58(r1),r24
373 
        l.sw    0x5c(r1),r25
374 
        l.sw    0x60(r1),r26
375 
        l.sw    0x64(r1),r27
376 
        l.sw    0x68(r1),r28
377 
        l.sw    0x6c(r1),r29
378 
        l.sw    0x70(r1),r30
379 
        l.sw    0x74(r1),r31
380 
        l.sw    0x78(r1),r3
381 
 
382 855 markom 
        l.movhi r3,hi(_int_main)
383 
        l.ori   r3,r3,lo(_int_main)
384 809 simons 
        l.jalr  r3
385 
        l.nop
386 
 
387 
        l.lwz   r2,0x4(r1)
388 
        l.lwz   r4,0x8(r1)
389 
        l.lwz   r5,0xc(r1)
390 
        l.lwz   r6,0x10(r1)
391 
        l.lwz   r7,0x14(r1)
392 
        l.lwz   r8,0x18(r1)
393 
        l.lwz   r9,0x1c(r1)
394 
        l.lwz   r10,0x20(r1)
395 
        l.lwz   r11,0x24(r1)
396 
        l.lwz   r12,0x28(r1)
397 
        l.lwz   r13,0x2c(r1)
398 
        l.lwz   r14,0x30(r1)
399 
        l.lwz   r15,0x34(r1)
400 
        l.lwz   r16,0x38(r1)
401 
        l.lwz   r17,0x3c(r1)
402 
        l.lwz   r18,0x40(r1)
403 
        l.lwz   r19,0x44(r1)
404 
        l.lwz   r20,0x48(r1)
405 
        l.lwz   r21,0x4c(r1)
406 
        l.lwz   r22,0x50(r1)
407 
        l.lwz   r23,0x54(r1)
408 
        l.lwz   r24,0x58(r1)
409 
        l.lwz   r25,0x5c(r1)
410 
        l.lwz   r26,0x60(r1)
411 
        l.lwz   r27,0x64(r1)
412 
        l.lwz   r28,0x68(r1)
413 
        l.lwz   r29,0x6c(r1)
414 
        l.lwz   r30,0x70(r1)
415 
        l.lwz   r31,0x74(r1)
416 833 simons 
        l.lwz   r3,0x78(r1)
417 809 simons 
 
418 
        l.mtspr r0,r0,SPR_PICSR
419 
 
420 
        l.addi  r1,r1,128
421 
        l.rfe
422 
        l.nop
423 
 
424 817 simons 
_align:
425 
        l.addi  r1,r1,-128
426 
        l.sw    0x08(r1),r2
427 
        l.sw    0x0c(r1),r3
428 
        l.sw    0x10(r1),r4
429 
        l.sw    0x14(r1),r5
430 
        l.sw    0x18(r1),r6
431 
        l.sw    0x1c(r1),r7
432 
        l.sw    0x20(r1),r8
433 
        l.sw    0x24(r1),r9
434 
        l.sw    0x28(r1),r10
435 
        l.sw    0x2c(r1),r11
436 
        l.sw    0x30(r1),r12
437 
        l.sw    0x34(r1),r13
438 
        l.sw    0x38(r1),r14
439 
        l.sw    0x3c(r1),r15
440 
        l.sw    0x40(r1),r16
441 
        l.sw    0x44(r1),r17
442 
        l.sw    0x48(r1),r18
443 
        l.sw    0x4c(r1),r19
444 
        l.sw    0x50(r1),r20
445 
        l.sw    0x54(r1),r21
446 
        l.sw    0x58(r1),r22
447 
        l.sw    0x5c(r1),r23
448 
        l.sw    0x60(r1),r24
449 
        l.sw    0x64(r1),r25
450 
        l.sw    0x68(r1),r26
451 
        l.sw    0x6c(r1),r27
452 
        l.sw    0x70(r1),r28
453 
        l.sw    0x74(r1),r29
454 
        l.sw    0x78(r1),r30
455 
        l.sw    0x7c(r1),r31
456 
 
457 
        l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */
458 
        l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
459 
 
460 833 simons 
        l.lwz   r3,0(r5)    /* Load insn */
461 817 simons 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
462 
 
463 
        l.sfeqi r4,0x00     /* Check if the load/store insn is in delay slot */
464 833 simons 
        l.bf    jmp
465 817 simons 
        l.sfeqi r4,0x01
466 833 simons 
        l.bf    jmp
467 817 simons 
        l.sfeqi r4,0x03
468 833 simons 
        l.bf    jmp
469 817 simons 
        l.sfeqi r4,0x04
470 833 simons 
        l.bf    jmp
471 817 simons 
        l.sfeqi r4,0x11
472 833 simons 
        l.bf    jr
473 817 simons 
        l.sfeqi r4,0x12
474 833 simons 
        l.bf    jr
475 817 simons 
        l.nop
476 833 simons 
        l.j     1f
477 817 simons 
        l.addi  r5,r5,4     /* Increment PC to get return insn address */
478 
 
479 
jmp:
480 
        l.slli  r4,r3,6     /* Get the signed extended jump length */
481 
        l.srai  r4,r4,4
482 
 
483 833 simons 
        l.lwz   r3,4(r5)      /* Load the real load/store insn */
484 817 simons 
 
485 833 simons 
        l.add   r5,r5,r4      /* Calculate jump target address */
486 817 simons 
 
487 833 simons 
        l.j     1f
488 817 simons 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
489 
 
490 
jr:
491 
        l.slli  r4,r3,9     /* Shift to get the reg nb */
492 
        l.andi  r4,r4,0x7c
493 
 
494 833 simons 
        l.lwz   r3,4(r5)    /* Load the real load/store insn */
495 817 simons 
 
496 833 simons 
        l.add   r4,r4,r1    /* Load the jump register value from the stack */
497 
        l.lwz   r5,0(r4)
498 817 simons 
 
499 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
500 
 
501 
 
502 
1:      l.mtspr r0,r5,SPR_EPCR_BASE
503 
 
504 
        l.sfeqi r4,0x26
505 833 simons 
        l.bf    lhs
506 817 simons 
        l.sfeqi r4,0x25
507 833 simons 
        l.bf    lhz
508 817 simons 
        l.sfeqi r4,0x22
509 833 simons 
        l.bf    lws
510 817 simons 
        l.sfeqi r4,0x21
511 833 simons 
        l.bf    lwz
512 817 simons 
        l.sfeqi r4,0x37
513 833 simons 
        l.bf    sh
514 817 simons 
        l.sfeqi r4,0x35
515 833 simons 
        l.bf    sw
516 817 simons 
        l.nop
517 
 
518 833 simons 
1:      l.j     1b      /* I don't know what to do */
519 817 simons 
        l.nop
520 
 
521 833 simons 
lhs:    l.lbs   r5,0(r2)
522 817 simons 
        l.slli  r5,r5,8
523 833 simons 
        l.lbz   r6,1(r2)
524 
        l.or    r5,r5,r6
525 817 simons 
        l.srli  r4,r3,19
526 
        l.andi  r4,r4,0x7c
527 833 simons 
        l.add   r4,r4,r1
528 
        l.j     align_end
529 
        l.sw    0(r4),r5
530 817 simons 
 
531 833 simons 
lhz:    l.lbz   r5,0(r2)
532 817 simons 
        l.slli  r5,r5,8
533 833 simons 
        l.lbz   r6,1(r2)
534 
        l.or    r5,r5,r6
535 817 simons 
        l.srli  r4,r3,19
536 
        l.andi  r4,r4,0x7c
537 833 simons 
        l.add   r4,r4,r1
538 
        l.j     align_end
539 
        l.sw    0(r4),r5
540 817 simons 
 
541 833 simons 
lws:    l.lbs   r5,0(r2)
542 817 simons 
        l.slli  r5,r5,24
543 833 simons 
        l.lbz   r6,1(r2)
544 817 simons 
        l.slli  r6,r6,16
545 833 simons 
        l.or    r5,r5,r6
546 
        l.lbz   r6,2(r2)
547 817 simons 
        l.slli  r6,r6,8
548 833 simons 
        l.or    r5,r5,r6
549 
        l.lbz   r6,3(r2)
550 
        l.or    r5,r5,r6
551 817 simons 
        l.srli  r4,r3,19
552 
        l.andi  r4,r4,0x7c
553 833 simons 
        l.add   r4,r4,r1
554 
        l.j     align_end
555 
        l.sw    0(r4),r5
556 817 simons 
 
557 833 simons 
lwz:    l.lbz   r5,0(r2)
558 817 simons 
        l.slli  r5,r5,24
559 833 simons 
        l.lbz   r6,1(r2)
560 817 simons 
        l.slli  r6,r6,16
561 833 simons 
        l.or    r5,r5,r6
562 
        l.lbz   r6,2(r2)
563 817 simons 
        l.slli  r6,r6,8
564 833 simons 
        l.or    r5,r5,r6
565 
        l.lbz   r6,3(r2)
566 
        l.or    r5,r5,r6
567 817 simons 
        l.srli  r4,r3,19
568 
        l.andi  r4,r4,0x7c
569 833 simons 
        l.add   r4,r4,r1
570 
        l.j     align_end
571 
        l.sw    0(r4),r5
572 817 simons 
 
573 
sh:
574 
        l.srli  r4,r3,9
575 
        l.andi  r4,r4,0x7c
576 833 simons 
        l.add   r4,r4,r1
577 
        l.lwz   r5,0(r4)
578 
        l.sb    1(r2),r5
579 
        l.srli  r5,r5,8
580 
        l.j     align_end
581 
        l.sb    0(r2),r5
582 817 simons 
 
583 
sw:
584 
        l.srli  r4,r3,9
585 
        l.andi  r4,r4,0x7c
586 833 simons 
        l.add   r4,r4,r1
587 
        l.lwz   r5,0(r4)
588 
        l.sb    3(r2),r5
589 
        l.srli  r5,r5,8
590 
        l.sb    2(r2),r5
591 
        l.srli  r5,r5,8
592 
        l.sb    1(r2),r5
593 
        l.srli  r5,r5,8
594 
        l.j     align_end
595 
        l.sb    0(r2),r5
596 817 simons 
 
597 
align_end:
598 
        l.lwz   r2,0x08(r1)
599 
        l.lwz   r3,0x0c(r1)
600 
        l.lwz   r4,0x10(r1)
601 
        l.lwz   r5,0x14(r1)
602 
        l.lwz   r6,0x18(r1)
603 
        l.lwz   r7,0x1c(r1)
604 
        l.lwz   r8,0x20(r1)
605 
        l.lwz   r9,0x24(r1)
606 
        l.lwz   r10,0x28(r1)
607 
        l.lwz   r11,0x2c(r1)
608 
        l.lwz   r12,0x30(r1)
609 
        l.lwz   r13,0x34(r1)
610 
        l.lwz   r14,0x38(r1)
611 
        l.lwz   r15,0x3c(r1)
612 
        l.lwz   r16,0x40(r1)
613 
        l.lwz   r17,0x44(r1)
614 
        l.lwz   r18,0x48(r1)
615 
        l.lwz   r19,0x4c(r1)
616 
        l.lwz   r20,0x50(r1)
617 
        l.lwz   r21,0x54(r1)
618 
        l.lwz   r22,0x58(r1)
619 
        l.lwz   r23,0x5c(r1)
620 
        l.lwz   r24,0x60(r1)
621 
        l.lwz   r25,0x64(r1)
622 
        l.lwz   r26,0x68(r1)
623 
        l.lwz   r27,0x6c(r1)
624 
        l.lwz   r28,0x70(r1)
625 
        l.lwz   r29,0x74(r1)
626 
        l.lwz   r30,0x78(r1)
627 833 simons 
        l.mfspr r31,r0,0x40
628 817 simons 
        l.lwz   r31,0x7c(r1)
629 
        l.addi  r1,r1,128
630 
        l.rfe

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