OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [orpmon/] [reset.S] - Blame information for rev 987

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 809 simons 
#include "spr_defs.h"
2 
#include "board.h"
3 
#include "mc.h"
4 
 
5 
 
6 
 
7 
        .extern _reset_support
8 
        .extern _eth_int
9 
        .extern _src_beg
10 
        .extern _dst_beg
11 
        .extern _dst_end
12 
        .extern _c_reset
13 
        .extern _int_main
14 833 simons 
        .extern _tick_interrupt
15 820 markom 
        .extern _crc32
16 816 markom 
 
17 
        /* Used by global.src_addr for default value */
18 
        .extern _src_addr
19 809 simons 
 
20 817 simons 
        .global _align
21 820 markom 
        .global _calc_mycrc32
22 822 markom 
        .global _mycrc32
23 
        .global _mysize
24 809 simons 
 
25 817 simons 
        .section .stack, "aw", @nobits
26 
.space  STACK_SIZE
27 809 simons 
_stack:
28 834 simons 
        .section .crc
29 820 markom 
_mycrc32:
30 833 simons 
        .word   0xcccccccc
31 820 markom 
_mysize:
32 
        .word 0xdddddddd
33 809 simons 
 
34 829 markom 
.if SELF_CHECK
35 820 markom 
_calc_mycrc32:
36 833 simons 
        l.addi  r3,r0,0
37 820 markom 
        l.movhi r4,hi(_calc_mycrc32)
38 
        l.ori   r4,r4,lo(_calc_mycrc32)
39 
        l.movhi r5,hi(_mysize)
40 
        l.ori   r5,r5,lo(_mysize)
41 
        l.lwz   r5,0(r5)
42 822 markom 
        l.addi  r1,r1,-4
43 833 simons 
        l.sw    0(r1),r9
44 820 markom 
 
45 
        /* unsigned long crc32 (unsigned long crc, const unsigned char *buf, unsigned long len); */
46 833 simons 
        l.jal           _crc32
47 
        l.nop
48 
 
49 
        l.movhi r3,hi(_mycrc32)
50 820 markom 
        l.ori   r3,r3,lo(_mycrc32)
51 
        l.lwz   r3,0(r3)
52 
 
53 833 simons 
        l.xor     r11,r3,r11
54 822 markom 
        l.lwz   r9,0(r1)
55 
        l.jr    r9
56 
        l.addi  r1,r1,4
57 829 markom 
.endif
58 
 
59 833 simons 
        .org 0x100
60 809 simons 
.if IN_FLASH
61 
        .section .reset, "ax"
62 
.else
63 817 simons 
        .section .vectors, "ax"
64 809 simons 
.endif
65 
 
66 
_reset:
67 
.if IN_FLASH
68 817 simons 
        l.movhi r3,hi(MC_BASE_ADDR)
69 809 simons 
        l.ori   r3,r3,MC_BA_MASK
70 
        l.addi  r5,r0,0x00
71 
        l.sw    0(r3),r5
72 
.endif
73 833 simons 
        l.movhi r3,hi(_start)
74 
        l.ori   r3,r3,lo(_start)
75 829 markom 
        l.jr    r3
76 833 simons 
        l.nop
77 809 simons 
 
78 
.if IN_FLASH
79 
        .section .vectors, "ax"
80 833 simons 
        .org 0x500
81 
.else
82 
        .org (0x500 - 0x100 + _reset)
83 
.endif
84 
 
85 987 simons 
        l.addi  r1,r1,-128
86 
        l.sw    0x4(r1),r2
87 
        l.movhi r2,hi(_tick)
88 
        l.ori   r2,r2,lo(_tick)
89 
        l.jr    r2
90 833 simons 
        l.nop
91 
 
92 
.if IN_FLASH
93 
        .section .vectors, "ax"
94 824 markom 
        .org 0x600
95 
.else
96 
        .org (0x600 - 0x100 + _reset)
97 809 simons 
.endif
98 
 
99 987 simons 
        l.addi  r1,r1,-128
100 
        l.sw    0x08(r1),r2
101 
        l.movhi r2,hi(_align)
102 
        l.ori   r2,r2,lo(_align)
103 
        l.jr    r2
104 817 simons 
        l.nop
105 
 
106 824 markom 
.if IN_FLASH
107 817 simons 
        .org 0x800
108 824 markom 
.else
109 
        .org (0x800 - 0x100 + _reset)
110 
.endif
111 817 simons 
 
112 987 simons 
        l.addi  r1,r1,-128
113 
        l.sw    0x4(r1),r2
114 
        l.movhi r2,hi(_int_wrapper)
115 
        l.ori   r2,r2,lo(_int_wrapper)
116 
        l.jr    r2
117 809 simons 
        l.nop
118 
 
119 
        .section .text
120 833 simons 
_start:
121 809 simons 
.if IN_FLASH
122 
        l.jal   _init_mc
123 
        l.nop
124 
 
125 
        /* Wait for SDRAM */
126 833 simons 
        l.addi  r3,r0,0x1000
127 809 simons 
1:      l.sfeqi r3,0
128 
        l.bnf   1b
129 
        l.addi  r3,r3,-1
130 
.endif
131 817 simons 
        /* Copy form flash to sram */
132 809 simons 
.if IN_FLASH
133 
        l.movhi r3,hi(_src_beg)
134 
        l.ori   r3,r3,lo(_src_beg)
135 
        l.movhi r4,hi(_vec_start)
136 
        l.ori   r4,r4,lo(_vec_start)
137 
        l.movhi r5,hi(_vec_end)
138 
        l.ori   r5,r5,lo(_vec_end)
139 
        l.sub   r5,r5,r4
140 
        l.sfeqi r5,0
141 
        l.bf    2f
142 
        l.nop
143 
1:      l.lwz   r6,0(r3)
144 
        l.sw    0(r4),r6
145 
        l.addi  r3,r3,4
146 
        l.addi  r4,r4,4
147 
        l.addi  r5,r5,-4
148 
        l.sfgtsi r5,0
149 817 simons 
        l.bf    1b
150 809 simons 
        l.nop
151 
2:
152 
        l.movhi r4,hi(_dst_beg)
153 
        l.ori   r4,r4,lo(_dst_beg)
154 
        l.movhi r5,hi(_dst_end)
155 
        l.ori   r5,r5,lo(_dst_end)
156 
1:      l.sfgeu r4,r5
157 
        l.bf    1f
158 
        l.nop
159 
        l.lwz   r8,0(r3)
160 
        l.sw    0(r4),r8
161 
        l.addi  r3,r3,4
162 
        l.bnf   1b
163 
        l.addi  r4,r4,4
164 
1:
165 
        l.addi  r3,r0,0
166 
        l.addi  r4,r0,0
167 
3:
168 
.endif
169 
 
170 
.if IC_ENABLE
171 833 simons 
        l.jal   _ic_enable
172 
        l.nop
173 809 simons 
.endif
174 
 
175 
.if DC_ENABLE
176 833 simons 
        l.jal   _dc_enable
177 
        l.nop
178 809 simons 
.endif
179 
 
180 
        l.movhi r1,hi(_stack-4)
181 858 markom 
        l.ori   r1,r1,lo(_stack-4)
182 833 simons 
        l.addi  r2,r0,-3
183 
        l.and   r1,r1,r2
184 809 simons 
 
185 
        l.movhi r2,hi(_main)
186 
        l.ori   r2,r2,lo(_main)
187 
        l.jr    r2
188 
        l.addi  r2,r0,0
189 
 
190 
_ic_enable:
191 
 
192 
        /* Flush IC */
193 
        l.addi  r10,r0,0
194 
        l.addi  r11,r0,IC_SIZE
195 
1:
196 
        l.mtspr r0,r10,SPR_ICBIR
197 
        l.sfne  r10,r11
198 
        l.bf    1b
199 
        l.addi  r10,r10,16
200 
 
201 
        /* Enable IC */
202 
        l.addi  r10,r0,(SPR_SR_ICE|SPR_SR_SM)
203 
        l.mtspr r0,r10,SPR_SR
204 
        l.nop
205 
        l.nop
206 
        l.nop
207 
        l.nop
208 
        l.nop
209 
 
210 833 simons 
        l.jr    r9
211 
        l.nop
212 809 simons 
 
213 
_dc_enable:
214 
 
215 
        /* Flush DC */
216 
        l.addi  r10,r0,0
217 
        l.addi  r11,r0,DC_SIZE
218 
1:
219 
        l.mtspr r0,r10,SPR_DCBIR
220 
        l.sfne  r10,r11
221 
        l.bf    1b
222 
        l.addi  r10,r10,16
223 
 
224 
        /* Enable DC */
225 
        l.addi  r10,r0,(SPR_SR_DCE|SPR_SR_SM)
226 
        l.mtspr r0,r10,SPR_SR
227 
 
228 833 simons 
        l.jr    r9
229 
        l.nop
230 809 simons 
 
231 
.if IN_FLASH
232 
_init_mc:
233 
 
234 817 simons 
        l.movhi r3,hi(MC_BASE_ADDR)
235 
        l.ori   r3,r3,lo(MC_BASE_ADDR)
236 809 simons 
 
237 
        l.addi  r4,r3,MC_CSC(0)
238 817 simons 
        l.movhi r5,hi(FLASH_BASE_ADDR)
239 987 simons 
        l.srai  r5,r5,6
240 809 simons 
        l.ori   r5,r5,0x0025
241 
        l.sw    0(r4),r5
242 
 
243 
        l.addi  r4,r3,MC_TMS(0)
244 
        l.movhi r5,hi(FLASH_TMS_VAL)
245 
        l.ori   r5,r5,lo(FLASH_TMS_VAL)
246 
        l.sw    0(r4),r5
247 
 
248 
        l.addi  r4,r3,MC_BA_MASK
249 
        l.addi  r5,r0,MC_MASK_VAL
250 
        l.sw    0(r4),r5
251 
 
252 
        l.addi  r4,r3,MC_CSR
253 
        l.movhi r5,hi(MC_CSR_VAL)
254 
        l.ori   r5,r5,lo(MC_CSR_VAL)
255 
        l.sw    0(r4),r5
256 
 
257 
        l.addi  r4,r3,MC_TMS(1)
258 
        l.movhi r5,hi(SDRAM_TMS_VAL)
259 
        l.ori   r5,r5,lo(SDRAM_TMS_VAL)
260 
        l.sw    0(r4),r5
261 
 
262 
        l.addi  r4,r3,MC_CSC(1)
263 817 simons 
        l.movhi r5,hi(SDRAM_BASE_ADDR)
264 987 simons 
        l.srai  r5,r5,6
265 809 simons 
        l.ori   r5,r5,0x0411
266 
        l.sw    0(r4),r5
267 
 
268 833 simons 
#ifdef ETH_DATA_BASE
269 
        l.addi  r4,r3,MC_CSC(2)
270 
        l.movhi r5,hi(ETH_DATA_BASE)
271 987 simons 
        l.srai  r5,r5,6
272 833 simons 
        l.ori   r5,r5,0x0005
273 
        l.sw    0(r4),r5
274 
 
275 
        l.addi  r4,r3,MC_TMS(2)
276 
        l.movhi r5,0xffff
277 
        l.ori   r5,r5,0xffff
278 
        l.sw    0(r4),r5
279 
#endif
280 
 
281 809 simons 
        l.jr    r9
282 
        l.nop
283 
.endif
284 
 
285 833 simons 
_tick:
286 
        l.sw    0x8(r1),r4
287 
        l.sw    0xc(r1),r5
288 
        l.sw    0x10(r1),r6
289 
        l.sw    0x14(r1),r7
290 
        l.sw    0x18(r1),r8
291 
        l.sw    0x1c(r1),r9
292 
        l.sw    0x20(r1),r10
293 
        l.sw    0x24(r1),r11
294 
        l.sw    0x28(r1),r12
295 
        l.sw    0x2c(r1),r13
296 
        l.sw    0x30(r1),r14
297 
        l.sw    0x34(r1),r15
298 
        l.sw    0x38(r1),r16
299 
        l.sw    0x3c(r1),r17
300 
        l.sw    0x40(r1),r18
301 
        l.sw    0x44(r1),r19
302 
        l.sw    0x48(r1),r20
303 
        l.sw    0x4c(r1),r21
304 
        l.sw    0x50(r1),r22
305 
        l.sw    0x54(r1),r23
306 
        l.sw    0x58(r1),r24
307 
        l.sw    0x5c(r1),r25
308 
        l.sw    0x60(r1),r26
309 
        l.sw    0x64(r1),r27
310 
        l.sw    0x68(r1),r28
311 
        l.sw    0x6c(r1),r29
312 
        l.sw    0x70(r1),r30
313 
        l.sw    0x74(r1),r31
314 
        l.sw    0x78(r1),r3
315 
 
316 
        l.movhi r3,hi(_tick_interrupt)
317 
        l.ori   r3,r3,lo(_tick_interrupt)
318 
        l.jalr  r3
319 
        l.nop
320 
 
321 
        l.lwz   r2,0x4(r1)
322 
        l.lwz   r4,0x8(r1)
323 
        l.lwz   r5,0xc(r1)
324 
        l.lwz   r6,0x10(r1)
325 
        l.lwz   r7,0x14(r1)
326 
        l.lwz   r8,0x18(r1)
327 
        l.lwz   r9,0x1c(r1)
328 
        l.lwz   r10,0x20(r1)
329 
        l.lwz   r11,0x24(r1)
330 
        l.lwz   r12,0x28(r1)
331 
        l.lwz   r13,0x2c(r1)
332 
        l.lwz   r14,0x30(r1)
333 
        l.lwz   r15,0x34(r1)
334 
        l.lwz   r16,0x38(r1)
335 
        l.lwz   r17,0x3c(r1)
336 
        l.lwz   r18,0x40(r1)
337 
        l.lwz   r19,0x44(r1)
338 
        l.lwz   r20,0x48(r1)
339 
        l.lwz   r21,0x4c(r1)
340 
        l.lwz   r22,0x50(r1)
341 
        l.lwz   r23,0x54(r1)
342 
        l.lwz   r24,0x58(r1)
343 
        l.lwz   r25,0x5c(r1)
344 
        l.lwz   r26,0x60(r1)
345 
        l.lwz   r27,0x64(r1)
346 
        l.lwz   r28,0x68(r1)
347 
        l.lwz   r29,0x6c(r1)
348 
        l.lwz   r30,0x70(r1)
349 
        l.mfspr r31,r0,0x40
350 
        l.lwz   r31,0x74(r1)
351 
        l.lwz   r3,0x78(r1)
352 
 
353 
        l.addi  r1,r1,128
354 
        l.rfe
355 
        l.nop
356 
 
357 809 simons 
_int_wrapper:
358 
        l.sw    0x8(r1),r4
359 
        l.sw    0xc(r1),r5
360 
        l.sw    0x10(r1),r6
361 
        l.sw    0x14(r1),r7
362 
        l.sw    0x18(r1),r8
363 
        l.sw    0x1c(r1),r9
364 
        l.sw    0x20(r1),r10
365 
        l.sw    0x24(r1),r11
366 
        l.sw    0x28(r1),r12
367 
        l.sw    0x2c(r1),r13
368 
        l.sw    0x30(r1),r14
369 
        l.sw    0x34(r1),r15
370 
        l.sw    0x38(r1),r16
371 
        l.sw    0x3c(r1),r17
372 
        l.sw    0x40(r1),r18
373 
        l.sw    0x44(r1),r19
374 
        l.sw    0x48(r1),r20
375 
        l.sw    0x4c(r1),r21
376 
        l.sw    0x50(r1),r22
377 
        l.sw    0x54(r1),r23
378 
        l.sw    0x58(r1),r24
379 
        l.sw    0x5c(r1),r25
380 
        l.sw    0x60(r1),r26
381 
        l.sw    0x64(r1),r27
382 
        l.sw    0x68(r1),r28
383 
        l.sw    0x6c(r1),r29
384 
        l.sw    0x70(r1),r30
385 
        l.sw    0x74(r1),r31
386 
        l.sw    0x78(r1),r3
387 
 
388 855 markom 
        l.movhi r3,hi(_int_main)
389 
        l.ori   r3,r3,lo(_int_main)
390 809 simons 
        l.jalr  r3
391 
        l.nop
392 
 
393 
        l.lwz   r2,0x4(r1)
394 
        l.lwz   r4,0x8(r1)
395 
        l.lwz   r5,0xc(r1)
396 
        l.lwz   r6,0x10(r1)
397 
        l.lwz   r7,0x14(r1)
398 
        l.lwz   r8,0x18(r1)
399 
        l.lwz   r9,0x1c(r1)
400 
        l.lwz   r10,0x20(r1)
401 
        l.lwz   r11,0x24(r1)
402 
        l.lwz   r12,0x28(r1)
403 
        l.lwz   r13,0x2c(r1)
404 
        l.lwz   r14,0x30(r1)
405 
        l.lwz   r15,0x34(r1)
406 
        l.lwz   r16,0x38(r1)
407 
        l.lwz   r17,0x3c(r1)
408 
        l.lwz   r18,0x40(r1)
409 
        l.lwz   r19,0x44(r1)
410 
        l.lwz   r20,0x48(r1)
411 
        l.lwz   r21,0x4c(r1)
412 
        l.lwz   r22,0x50(r1)
413 
        l.lwz   r23,0x54(r1)
414 
        l.lwz   r24,0x58(r1)
415 
        l.lwz   r25,0x5c(r1)
416 
        l.lwz   r26,0x60(r1)
417 
        l.lwz   r27,0x64(r1)
418 
        l.lwz   r28,0x68(r1)
419 
        l.lwz   r29,0x6c(r1)
420 
        l.lwz   r30,0x70(r1)
421 
        l.lwz   r31,0x74(r1)
422 833 simons 
        l.lwz   r3,0x78(r1)
423 809 simons 
 
424 
        l.mtspr r0,r0,SPR_PICSR
425 
 
426 
        l.addi  r1,r1,128
427 
        l.rfe
428 
        l.nop
429 
 
430 817 simons 
_align:
431 
        l.sw    0x0c(r1),r3
432 
        l.sw    0x10(r1),r4
433 
        l.sw    0x14(r1),r5
434 
        l.sw    0x18(r1),r6
435 
        l.sw    0x1c(r1),r7
436 
        l.sw    0x20(r1),r8
437 
        l.sw    0x24(r1),r9
438 
        l.sw    0x28(r1),r10
439 
        l.sw    0x2c(r1),r11
440 
        l.sw    0x30(r1),r12
441 
        l.sw    0x34(r1),r13
442 
        l.sw    0x38(r1),r14
443 
        l.sw    0x3c(r1),r15
444 
        l.sw    0x40(r1),r16
445 
        l.sw    0x44(r1),r17
446 
        l.sw    0x48(r1),r18
447 
        l.sw    0x4c(r1),r19
448 
        l.sw    0x50(r1),r20
449 
        l.sw    0x54(r1),r21
450 
        l.sw    0x58(r1),r22
451 
        l.sw    0x5c(r1),r23
452 
        l.sw    0x60(r1),r24
453 
        l.sw    0x64(r1),r25
454 
        l.sw    0x68(r1),r26
455 
        l.sw    0x6c(r1),r27
456 
        l.sw    0x70(r1),r28
457 
        l.sw    0x74(r1),r29
458 
        l.sw    0x78(r1),r30
459 
        l.sw    0x7c(r1),r31
460 
 
461 
        l.mfspr r2,r0,SPR_EEAR_BASE /* Load the efective addres */
462 
        l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
463 
 
464 833 simons 
        l.lwz   r3,0(r5)    /* Load insn */
465 817 simons 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
466 
 
467 
        l.sfeqi r4,0x00     /* Check if the load/store insn is in delay slot */
468 833 simons 
        l.bf    jmp
469 817 simons 
        l.sfeqi r4,0x01
470 833 simons 
        l.bf    jmp
471 817 simons 
        l.sfeqi r4,0x03
472 833 simons 
        l.bf    jmp
473 817 simons 
        l.sfeqi r4,0x04
474 833 simons 
        l.bf    jmp
475 817 simons 
        l.sfeqi r4,0x11
476 833 simons 
        l.bf    jr
477 817 simons 
        l.sfeqi r4,0x12
478 833 simons 
        l.bf    jr
479 817 simons 
        l.nop
480 833 simons 
        l.j     1f
481 817 simons 
        l.addi  r5,r5,4     /* Increment PC to get return insn address */
482 
 
483 
jmp:
484 
        l.slli  r4,r3,6     /* Get the signed extended jump length */
485 
        l.srai  r4,r4,4
486 
 
487 833 simons 
        l.lwz   r3,4(r5)      /* Load the real load/store insn */
488 817 simons 
 
489 833 simons 
        l.add   r5,r5,r4      /* Calculate jump target address */
490 817 simons 
 
491 833 simons 
        l.j     1f
492 817 simons 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
493 
 
494 
jr:
495 
        l.slli  r4,r3,9     /* Shift to get the reg nb */
496 
        l.andi  r4,r4,0x7c
497 
 
498 833 simons 
        l.lwz   r3,4(r5)    /* Load the real load/store insn */
499 817 simons 
 
500 833 simons 
        l.add   r4,r4,r1    /* Load the jump register value from the stack */
501 
        l.lwz   r5,0(r4)
502 817 simons 
 
503 
        l.srli  r4,r3,26    /* Shift left to get the insn opcode */
504 
 
505 
 
506 
1:      l.mtspr r0,r5,SPR_EPCR_BASE
507 
 
508 
        l.sfeqi r4,0x26
509 833 simons 
        l.bf    lhs
510 817 simons 
        l.sfeqi r4,0x25
511 833 simons 
        l.bf    lhz
512 817 simons 
        l.sfeqi r4,0x22
513 833 simons 
        l.bf    lws
514 817 simons 
        l.sfeqi r4,0x21
515 833 simons 
        l.bf    lwz
516 817 simons 
        l.sfeqi r4,0x37
517 833 simons 
        l.bf    sh
518 817 simons 
        l.sfeqi r4,0x35
519 833 simons 
        l.bf    sw
520 817 simons 
        l.nop
521 
 
522 833 simons 
1:      l.j     1b      /* I don't know what to do */
523 817 simons 
        l.nop
524 
 
525 833 simons 
lhs:    l.lbs   r5,0(r2)
526 817 simons 
        l.slli  r5,r5,8
527 833 simons 
        l.lbz   r6,1(r2)
528 
        l.or    r5,r5,r6
529 817 simons 
        l.srli  r4,r3,19
530 
        l.andi  r4,r4,0x7c
531 833 simons 
        l.add   r4,r4,r1
532 
        l.j     align_end
533 
        l.sw    0(r4),r5
534 817 simons 
 
535 833 simons 
lhz:    l.lbz   r5,0(r2)
536 817 simons 
        l.slli  r5,r5,8
537 833 simons 
        l.lbz   r6,1(r2)
538 
        l.or    r5,r5,r6
539 817 simons 
        l.srli  r4,r3,19
540 
        l.andi  r4,r4,0x7c
541 833 simons 
        l.add   r4,r4,r1
542 
        l.j     align_end
543 
        l.sw    0(r4),r5
544 817 simons 
 
545 833 simons 
lws:    l.lbs   r5,0(r2)
546 817 simons 
        l.slli  r5,r5,24
547 833 simons 
        l.lbz   r6,1(r2)
548 817 simons 
        l.slli  r6,r6,16
549 833 simons 
        l.or    r5,r5,r6
550 
        l.lbz   r6,2(r2)
551 817 simons 
        l.slli  r6,r6,8
552 833 simons 
        l.or    r5,r5,r6
553 
        l.lbz   r6,3(r2)
554 
        l.or    r5,r5,r6
555 817 simons 
        l.srli  r4,r3,19
556 
        l.andi  r4,r4,0x7c
557 833 simons 
        l.add   r4,r4,r1
558 
        l.j     align_end
559 
        l.sw    0(r4),r5
560 817 simons 
 
561 833 simons 
lwz:    l.lbz   r5,0(r2)
562 817 simons 
        l.slli  r5,r5,24
563 833 simons 
        l.lbz   r6,1(r2)
564 817 simons 
        l.slli  r6,r6,16
565 833 simons 
        l.or    r5,r5,r6
566 
        l.lbz   r6,2(r2)
567 817 simons 
        l.slli  r6,r6,8
568 833 simons 
        l.or    r5,r5,r6
569 
        l.lbz   r6,3(r2)
570 
        l.or    r5,r5,r6
571 817 simons 
        l.srli  r4,r3,19
572 
        l.andi  r4,r4,0x7c
573 833 simons 
        l.add   r4,r4,r1
574 
        l.j     align_end
575 
        l.sw    0(r4),r5
576 817 simons 
 
577 
sh:
578 
        l.srli  r4,r3,9
579 
        l.andi  r4,r4,0x7c
580 833 simons 
        l.add   r4,r4,r1
581 
        l.lwz   r5,0(r4)
582 
        l.sb    1(r2),r5
583 
        l.srli  r5,r5,8
584 
        l.j     align_end
585 
        l.sb    0(r2),r5
586 817 simons 
 
587 
sw:
588 
        l.srli  r4,r3,9
589 
        l.andi  r4,r4,0x7c
590 833 simons 
        l.add   r4,r4,r1
591 
        l.lwz   r5,0(r4)
592 
        l.sb    3(r2),r5
593 
        l.srli  r5,r5,8
594 
        l.sb    2(r2),r5
595 
        l.srli  r5,r5,8
596 
        l.sb    1(r2),r5
597 
        l.srli  r5,r5,8
598 
        l.j     align_end
599 
        l.sb    0(r2),r5
600 817 simons 
 
601 
align_end:
602 
        l.lwz   r2,0x08(r1)
603 
        l.lwz   r3,0x0c(r1)
604 
        l.lwz   r4,0x10(r1)
605 
        l.lwz   r5,0x14(r1)
606 
        l.lwz   r6,0x18(r1)
607 
        l.lwz   r7,0x1c(r1)
608 
        l.lwz   r8,0x20(r1)
609 
        l.lwz   r9,0x24(r1)
610 
        l.lwz   r10,0x28(r1)
611 
        l.lwz   r11,0x2c(r1)
612 
        l.lwz   r12,0x30(r1)
613 
        l.lwz   r13,0x34(r1)
614 
        l.lwz   r14,0x38(r1)
615 
        l.lwz   r15,0x3c(r1)
616 
        l.lwz   r16,0x40(r1)
617 
        l.lwz   r17,0x44(r1)
618 
        l.lwz   r18,0x48(r1)
619 
        l.lwz   r19,0x4c(r1)
620 
        l.lwz   r20,0x50(r1)
621 
        l.lwz   r21,0x54(r1)
622 
        l.lwz   r22,0x58(r1)
623 
        l.lwz   r23,0x5c(r1)
624 
        l.lwz   r24,0x60(r1)
625 
        l.lwz   r25,0x64(r1)
626 
        l.lwz   r26,0x68(r1)
627 
        l.lwz   r27,0x6c(r1)
628 
        l.lwz   r28,0x70(r1)
629 
        l.lwz   r29,0x74(r1)
630 
        l.lwz   r30,0x78(r1)
631 833 simons 
        l.mfspr r31,r0,0x40
632 817 simons 
        l.lwz   r31,0x7c(r1)
633 
        l.addi  r1,r1,128
634 
        l.rfe

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.