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[/] [or1k/] [trunk/] [orpmon/] [sim.cfg] - Blame information for rev 878

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1 809 simons
/* sim.cfg -- Simulator configuration script file
2
   Copyright (C) 2001, Marko Mlinar, markom@opencores.org
3
 
4
This file is part of OpenRISC 1000 Architectural Simulator.
5 878 rherveille
It contains the default configuration and help about configuring
6
the simulator.
7 809 simons
 
8
This program is free software; you can redistribute it and/or modify
9
it under the terms of the GNU General Public License as published by
10
the Free Software Foundation; either version 2 of the License, or
11
(at your option) any later version.
12
 
13
This program is distributed in the hope that it will be useful,
14
but WITHOUT ANY WARRANTY; without even the implied warranty of
15
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16
GNU General Public License for more details.
17
 
18
You should have received a copy of the GNU General Public License
19
along with this program; if not, write to the Free Software
20
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
21
 
22
 
23
/* INTRODUCTION
24
 
25 878 rherveille
   The ork1sim has various parameters, that are set in configuration files
26
   like this one. The user can switch between configurations at startup by
27
   specifying the required configuration file with the -f  option.
28
   If no configuration file is specified or1ksim searches for the default
29
   configuration file sim.cfg. First it searches for './sim.cfg'. If this
30
   file is not found, it searches for '~/or1k/sim.cfg'. If this file is
31
   not found too, it reverts to the built-in default configuration.
32
 
33
   NOTE: Users should not rely on the built-in configuration, since the
34
         default configuration may differ between version.
35
         Rather create a configuration file that sets all critical values.
36 809 simons
 
37 878 rherveille
   This file may contain (standard C) comments only - no // support.
38
 
39
   Configure files may be be included, using:
40
   include "file_name_to_include"
41 809 simons
 
42 878 rherveille
   Like normal configuration files, the included file is divided into
43
   sections. Each section is described in detail also.
44 809 simons
 
45 878 rherveille
   Some section have subsections. One example of such a subsection is:
46 809 simons
 
47
   device 
48
     instance specific parameters...
49
   enddevice
50
 
51
   which creates a device instance.
52
*/
53
 
54 833 simons
 
55 809 simons
/* MEMORY SECTION
56
 
57 878 rherveille
   This section specifies how the memory is generated and the blocks
58
   it consists of.
59 809 simons
 
60
   type = random/unknown/pattern
61 878 rherveille
      Specifies the initial memory values.
62
      'random' generates random memory using seed 'random_seed'.
63
      'pattern' fills memory with 'pattern'.
64
      'unknown' does not specify how memory should be generated,
65
      leaving the memory in a undefined state. This is the fastest
66
      option.
67 809 simons
 
68
   random_seed = 
69 878 rherveille
      random seed for randomizer, used if type = 'random'.
70 809 simons
 
71
   pattern = 
72 878 rherveille
      pattern to fill memory, used if type = 'pattern'.
73 809 simons
 
74
   nmemories = 
75
      number of memory instances connected
76
 
77
   instance specific:
78
     baseaddr = 
79
        memory start address
80
 
81
     size = 
82
        memory size
83
 
84
     name = ""
85
        memory block name
86
 
87
     ce = 
88
        chip enable index of the memory instance
89
 
90
     delayr = 
91
        cycles, required for read access, -1 if instance does not support reading
92
 
93
     delayw = 
94
        cycles, required for write access, -1 if instance does not support writing
95
 
96
     log = ""
97
        filename, where to log memory accesses to, no log, if log command is not specified
98
*/
99
 
100 878 rherveille
 
101 809 simons
section memory
102
  /*random_seed = 12345
103
  type = random*/
104
  pattern = 0x00
105
  type = unknown /* Fastest */
106
 
107 878 rherveille
 
108 833 simons
  nmemories = 3
109 809 simons
  device 0
110
    name = "FLASH"
111
    ce = 0
112
    baseaddr = 0x04000000
113 833 simons
    size = 0x00800000
114 809 simons
    delayr = 10
115
    delayw = -1
116
  enddevice
117
 
118
  device 1
119
    name = "RAM"
120
    ce = 1
121
    baseaddr = 0x00000000
122 833 simons
    size = 0x00400000
123
    delayr = 1
124
    delayw = 2
125 809 simons
  enddevice
126 878 rherveille
 
127 833 simons
  device 2
128
    name = "SRAM"
129
    ce = 2
130
    baseaddr = 0x08000000
131
    size = 0x00400000
132
    delayr = 1
133
    delayw = 2
134
  enddevice
135 809 simons
end
136
 
137 878 rherveille
 
138 809 simons
/* IMMU SECTION
139
 
140 878 rherveille
    This section configures the Instruction Memory Manangement Unit
141 809 simons
 
142
    enabled = 0/1
143 878 rherveille
       '0': disabled
144
       '1': enabled
145 809 simons
       (NOTE: UPR bit is set)
146
 
147
    nsets = 
148
       number of ITLB sets; must be power of two
149
 
150
    nways = 
151
       number of ITLB ways
152
 
153
    pagesize = 
154
       instruction page size; must be power of two
155
 
156
    entrysize = 
157
       instruction entry size in bytes
158
 
159
    ustates = 
160
       number of ITLB usage states (2, 3, 4 etc., max is 4)
161 878 rherveille
 
162
    hitdelay = 
163
       number of cycles immu hit costs
164
 
165
    missdelay = 
166
       number of cycles immu miss costs
167 809 simons
*/
168
 
169
section immu
170 833 simons
  enabled = 1
171
  nsets = 64
172 809 simons
  nways = 1
173
  pagesize = 8192
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  hitdelay = 0
175
  missdelay = 0
176 809 simons
end
177
 
178 878 rherveille
 
179 809 simons
/* DMMU SECTION
180
 
181 878 rherveille
    This section configures the Data Memory Manangement Unit
182 809 simons
 
183
    enabled = 0/1
184 878 rherveille
       '0': disabled
185
       '1': enabled
186 809 simons
       (NOTE: UPR bit is set)
187
 
188
    nsets = 
189
       number of DTLB sets; must be power of two
190
 
191
    nways = 
192
       number of DTLB ways
193
 
194
    pagesize = 
195
       data page size; must be power of two
196
 
197
    entrysize = 
198
       data entry size in bytes
199
 
200
    ustates = 
201
       number of DTLB usage states (2, 3, 4 etc., max is 4)
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203
    hitdelay = 
204
       number of cycles dmmu hit costs
205
 
206
    missdelay = 
207
       number of cycles dmmu miss costs
208 809 simons
*/
209
 
210
section dmmu
211 833 simons
  enabled = 1
212
  nsets = 64
213 809 simons
  nways = 1
214
  pagesize = 8192
215 878 rherveille
  hitdelay = 0
216
  missdelay = 0
217 809 simons
end
218
 
219
 
220
/* IC SECTION
221
 
222 878 rherveille
   This section configures the Instruction Cache
223 809 simons
 
224 878 rherveille
   enabled = 0/1
225
       '0': disabled
226
       '1': enabled
227
      (NOTE: UPR bit is set)
228 809 simons
 
229 878 rherveille
   nsets = 
230
      number of IC sets; must be power of two
231 809 simons
 
232 878 rherveille
   nways = 
233
      number of IC ways
234 809 simons
 
235 878 rherveille
   blocksize = 
236
      IC block size in bytes; must be power of two
237 809 simons
 
238 878 rherveille
   ustates = 
239
      number of IC usage states (2, 3, 4 etc., max is 4)
240
 
241
   hitdelay = 
242
      number of cycles ic hit costs
243
 
244
    missdelay = 
245
      number of cycles ic miss costs
246 809 simons
*/
247
 
248
section ic
249 833 simons
  enabled = 1
250
  nsets = 256
251 809 simons
  nways = 1
252
  blocksize = 16
253 878 rherveille
  hitdelay = 0
254
  missdelay = 0
255 809 simons
end
256
 
257 878 rherveille
 
258 809 simons
/* DC SECTION
259
 
260 878 rherveille
   This section configures the Data Cache
261 809 simons
 
262 878 rherveille
   enabled = 0/1
263
       '0': disabled
264
       '1': enabled
265
      (NOTE: UPR bit is set)
266 809 simons
 
267 878 rherveille
   nsets = 
268
      number of DC sets; must be power of two
269 809 simons
 
270 878 rherveille
   nways = 
271
      number of DC ways
272 809 simons
 
273 878 rherveille
   blocksize = 
274
      DC block size in bytes; must be power of two
275 809 simons
 
276 878 rherveille
   ustates = 
277
      number of DC usage states (2, 3, 4 etc., max is 4)
278
 
279
   load_hitdelay = 
280
      number of cycles dc load hit costs
281
 
282
   load_missdelay = 
283
      number of cycles dc load miss costs
284
 
285
   store_hitdelay = 
286
      number of cycles dc load hit costs
287
 
288
   store_missdelay = 
289
      number of cycles dc load miss costs
290 809 simons
*/
291
 
292
section dc
293 833 simons
  enabled = 1
294
  nsets = 256
295 809 simons
  nways = 1
296
  blocksize = 16
297 878 rherveille
  load_hitdelay = 0
298
  load_missdelay = 0
299
  store_hitdelay = 0
300
  store_missdelay = 0
301 809 simons
end
302
 
303 878 rherveille
 
304 809 simons
/* SIM SECTION
305
 
306 878 rherveille
  This section specifies how or1ksim should behave.
307 809 simons
 
308
  verbose = 0/1
309 878 rherveille
       '0': don't print extra messages
310
       '1': print extra messages
311 809 simons
 
312
  debug = 0-9
313 878 rherveille
 
314
      1-9: debug message level.
315
           higher numbers produce more messages
316 809 simons
 
317
  profile = 0/1
318 878 rherveille
      '0': don't generate profiling file 'sim.profile'
319
      '1': don't generate profiling file 'sim.profile'
320 809 simons
 
321
  prof_fn = ""
322 878 rherveille
      optional filename for the profiling file.
323
      valid only if 'profile' is set
324
 
325
  mprofile = 0/1
326
      '0': don't generate memory profiling file 'sim.mprofile'
327
      '1': generate memory profiling file 'sim.mprofile'
328 809 simons
 
329 878 rherveille
  mprof_fn = ""
330
      optional filename for the memory profiling file.
331
      valid only if 'mprofile' is set
332
 
333 809 simons
  history = 0/1
334 878 rherveille
      '0': don't track execution flow
335
      '1': track execution flow
336
      Execution flow can be tracked for the simulator's
337
      'hist' command. Useful for back-trace debugging.
338 809 simons
 
339
  iprompt = 0/1
340 878 rherveille
     '0': start in  (so what do we start in ???)
341
     '1': start in interactive prompt.
342 809 simons
 
343
  exe_log = 0/1
344 878 rherveille
      '0': don't generate execution log.
345
      '1': generate execution log.
346
 
347
  exe_log = default/hardware/simple/software
348
      type of execution log, default is used when not specified
349
 
350
  exe_log_start = 
351
      index of first instruction to start logging, default = 0
352
 
353
  exe_log_end = 
354
      index of last instruction to end logging; not limited, if omitted
355
 
356
  exe_log_marker = 
357
       specifies number of instructions before horizontal marker is
358
      printed; if zero, markers are disabled (default)
359 809 simons
 
360
  exe_log_fn = ""
361 878 rherveille
      filename for the exection log file.
362
      valid only if 'exe_log' is set
363
 
364
  spr_log = 0/1
365
      '0': log reads/writes to/from sprs
366
      '1': don't log reads/write to/from sprs
367
 
368
  spr_log_fn = ""
369
      filename for the sprs log file.
370
      valid only if 'spr_log' is set
371 809 simons
 
372
  clkcycle = [ps|ns|us|ms]
373
      specifies time measurement for one cycle
374
*/
375
 
376
section sim
377 833 simons
  verbose = 0
378
  debug = 0
379 809 simons
  profile = 0
380
  prof_fn = "sim.profile"
381
 
382 878 rherveille
  history = 1
383 809 simons
  /* iprompt = 0 */
384 829 markom
  exe_log = 0
385 809 simons
  exe_log_type = software
386 858 markom
  exe_log_start = 0
387 833 simons
/*  exe_log_end = 20000000*/
388
  exe_log_marker = 10000
389 809 simons
  exe_log_fn = "executed.log"
390 878 rherveille
 
391
  spr_log = 0
392
  spr_log_fn = "spr.log"
393
  clkcycle = 100ns
394 809 simons
end
395
 
396
 
397
/* SECTION VAPI
398
 
399 878 rherveille
    This section configures the Verification API, used for Advanced
400 809 simons
    Core Verification.
401
 
402
    enabled = 0/1
403 878 rherveille
        '0': disbable VAPI server
404
        '1': enable/start VAPI server
405 809 simons
 
406
    server_port = 
407
        TCP/IP port to start VAPI server on
408
 
409
    log_enabled = 0/1
410 878 rherveille
       '0': disable VAPI requests logging
411
       '1': enable VAPI requests logging
412 809 simons
 
413 878 rherveille
    hide_device_id = 0/1
414
       '0': don't log device id (for compatability with old version)
415
       '1': log device id
416
 
417
 
418 809 simons
    vapi_fn = 
419 878 rherveille
       filename for the log file.
420
       valid only if log_enabled is set
421 809 simons
*/
422
 
423
section VAPI
424
  enabled = 0
425
  server_port = 9998
426
  log_enabled = 0
427
  vapi_log_fn = "vapi.log"
428
end
429
 
430
 
431
/* CPU SECTION
432
 
433
   This section specifies various CPU parameters.
434
 
435
   ver = 
436
   rev = 
437
      specifies version and revision of the CPU used
438
 
439
   upr = 
440
      changes the upr register
441 878 rherveille
 
442
   sr = 
443
      sets the initial Supervision Register value
444 809 simons
 
445
   superscalar = 0/1
446 878 rherveille
      '0': CPU is scalar
447
      '1': CPU is superscalar
448 809 simons
      (modify cpu/or32/execute.c to tune superscalar model)
449
 
450
   hazards = 0/1
451 878 rherveille
      '0': don't track data hazards in superscalar CPU
452
      '1': track data hazards in superscalar CPU
453
      If tracked, data hazards can be displayed using the
454
      simulator's 'r' command.
455 809 simons
 
456
   dependstats = 0/1
457 878 rherveille
      '0': don't calculate inter-instruction dependencies.
458
      '1': calculate inter-instruction dependencies.
459
      If calculated, inter-instruction dependencies can be
460
      displayed using the simulator's 'stat' command.
461 809 simons
 
462 878 rherveille
   raw_range = 
463
      range in cycles for raw register over time analysis, 0 = disabled
464
 
465
   sbuf_len = 
466
      length of store buffer (<= 256), 0 = disabled
467 809 simons
*/
468
 
469
section cpu
470
  ver = 0x1200
471
  rev = 0x0001
472
  /* upr = */
473
  superscalar = 0
474
  hazards = 0
475
  dependstats = 0
476 878 rherveille
end
477
 
478
 
479
/* PM SECTION
480
 
481
   This section specifies Power Management parameters
482
 
483
   enabled = 0/1
484
      '0': disable power management
485
      '1': enable power management
486
*/
487
 
488
section pm
489
  enabled = 0
490
end
491
 
492
 
493
/* BPB SECTION
494
 
495
   This section specifies how branch prediction should behave.
496
 
497
   enabled = 0/1
498
     '0': disable branch prediction
499
     '1': enable branch prediction
500
 
501
   btic = 0/1
502
     '0': disable branch target instruction cache model
503
     '1': enable branch target instruction cache model
504
 
505
   sbp_bf_fwd = 0/1
506
     Static branch prediction for 'l.bf'
507
     '0': don't use forward prediction
508
     '1': use forward prediction
509
 
510
   sbp_bnf_fwd = 0/1
511
     Static branch prediction for 'l.bnf'
512
     '0': don't use forward prediction
513
     '1': use forward prediction
514
 
515
   hitdelay = 
516
       number of cycles bpb hit costs
517
 
518
   missdelay = 
519
       number of cycles bpb miss costs
520
*/
521
 
522
section bpb
523
  enabled = 0
524 809 simons
  btic = 0
525 878 rherveille
  sbp_bf_fwd = 0
526
  sbp_bnf_fwd = 0
527
  hitdelay = 0
528
  missdelay = 0
529 809 simons
end
530
 
531
 
532
/* DEBUG SECTION
533
 
534 878 rherveille
   This sections specifies how the debug unit should behave.
535 809 simons
 
536
   enabled = 0/1
537 878 rherveille
      '0': disable debug unit
538
      '1': enable debug unit
539 809 simons
 
540
   gdb_enabled = 0/1
541 878 rherveille
      '0': don't start gdb server
542
      '1': start gdb server at port 'server_port'
543 809 simons
 
544
   server_port = 
545 878 rherveille
      TCP/IP port to start gdb server on
546
      valid only if gdb_enabled is set
547 809 simons
 
548 878 rherveille
   vapi_id = 
549
      Used to create "fake" vapi log file containing the JTAG proxy messages.
550
*/
551
 
552 809 simons
section debug
553 833 simons
  enabled = 0
554 809 simons
  gdb_enabled = 0
555
  server_port = 9999
556
end
557
 
558
 
559
/* MC SECTION
560
 
561
   This section configures the memory controller
562
 
563
   enabled = 0/1
564 878 rherveille
     '0': disable memory controller
565
     '1': enable memory controller
566 809 simons
 
567
   baseaddr = 
568
      address of first MC register
569
 
570
   POC = 
571
      Power On Configuration register
572
*/
573
 
574
section mc
575 858 markom
  enabled = 1
576 809 simons
  baseaddr = 0x60000000
577
  POC = 0x00000008                 /* Power on configuration register */
578
end
579
 
580
 
581
/* UART SECTION
582
 
583 878 rherveille
   This section configures the UARTs
584 809 simons
 
585
   nuarts = 
586
      make specified number of instances, configure each
587
      instance within device - enddevice construct.
588
 
589
   instance specific:
590
     baseaddr = 
591
        address of first UART register for this device
592
 
593 878 rherveille
     rxfile = ""
594 809 simons
        filename, where to read data from
595
 
596 878 rherveille
     txfile = ""
597 809 simons
        filename, where to write data to
598
 
599
     irq = 
600
        irq number for this device
601
 
602
     16550 = 0/1
603 878 rherveille
        '0': this device is a UART16450
604
        '1': this device is a UART16550
605 809 simons
 
606
     jitter = 
607
        in msecs... time to block, -1 to disable it
608
 
609
     vapi_id = 
610
        VAPI id of this instance
611
*/
612
 
613
section uart
614
  nuarts = 1
615
 
616
  device 0
617
    baseaddr = 0x90000000
618 833 simons
    irq = 19
619 878 rherveille
    rxfile = "/tmp/uart0.rx"
620
    txfile = "/tmp/uart0.tx"
621 809 simons
    jitter = -1                     /* async behaviour */
622 833 simons
    16550 = 1
623 809 simons
  enddevice
624
end
625
 
626
 
627
/* DMA SECTION
628
 
629 878 rherveille
   This section configures the DMAs
630 809 simons
 
631
   ndmas = 
632
      make specified number of instances, configure each
633
      instance within device - enddevice construct.
634
 
635
   instance specific:
636
     baseaddr = 
637
        address of first DMA register for this device
638
 
639
     irq = 
640
        irq number for this device
641
 
642
     vapi_id = 
643
        VAPI id of this instance
644
*/
645
 
646
section dma
647 878 rherveille
  ndmas = 0
648 833 simons
 
649 878 rherveille
  /*
650 809 simons
  device 0
651 833 simons
    baseaddr = 0xa0000000
652 809 simons
    irq = 4
653
  enddevice
654 878 rherveille
  */
655 809 simons
end
656
 
657
 
658
/* ETHERNET SECTION
659
 
660 878 rherveille
   This section configures the ETHERNETs
661 809 simons
 
662
   nethernets = 
663
      make specified number of instances, configure each
664
      instance within device - enddevice construct.
665
 
666
   instance specific:
667
     baseaddr = 
668
        address of first ethernet register for this device
669
 
670
     dma = 
671
        which controller is this ethernet "connected" to
672
 
673 878 rherveille
     irq = 
674
        ethernet mac IRQ level
675
 
676
     rtx_type = 
677
        use 0 - file interface, 1 - socket interface
678
 
679 809 simons
     rx_channel = 
680
        DMA channel used for RX
681
 
682
     tx_channel = 
683
        DMA channel used for TX
684
 
685 878 rherveille
     rxfile = ""
686 809 simons
        filename, where to read data from
687
 
688 878 rherveille
     txfile = ""
689 809 simons
        filename, where to write data to
690
 
691 878 rherveille
     sockif = ""
692
        interface name of ethernet socket
693
 
694 809 simons
     vapi_id = 
695
        VAPI id of this instance
696
*/
697
 
698
section ethernet
699
  nethernets = 1
700
 
701
  device 0
702 833 simons
    baseaddr = 0xd0000000
703 809 simons
    dma = 0
704 817 simons
    irq = 15
705
    rtx_type = 1
706 809 simons
    tx_channel = 0
707
    rx_channel = 1
708 817 simons
    rxfile = "eth0.rx"
709
    txfile = "eth0.tx"
710
    sockif = "eth0"
711 809 simons
  enddevice
712
end
713
 
714 878 rherveille
 
715
/* GPIO SECTION
716
 
717
   This section configures the GPIOs
718
 
719
   ngpios = 
720
      make specified number of instances, configure each
721
      instance within device - enddevice construct.
722
 
723
   instance specific:
724
     baseaddr = 
725
        address of first GPIO register for this device
726
 
727
     irq = 
728
        irq number for this device
729
 
730
     base_vapi_id = 
731
        first VAPI id of this instance
732
        GPIO uses 8 consecutive VAPI IDs
733
*/
734
 
735
section gpio
736
  ngpios = 1
737
 
738
  device 0
739
    baseaddr = 0xA1000000
740
    irq = 23
741
    base_vapi_id = 0x0200
742
  enddevice
743
end
744
 
745
/* VGA SECTION
746
 
747
    This section configures the VGA/LCD controller
748
 
749
    nvgas = 
750
       number of VGA devices connected
751
 
752
    instance specific:
753
      baseaddr = 
754
        address of first VGA register
755
 
756
      irq = 
757
        irq number for this device
758
 
759
      refresh_rate = 
760
        number of cycles between screen dumps
761
 
762
      filename = ""
763
        template name for generated names (e.g. "primary" produces "primary0023.bmp")
764
*/
765
 
766
section vga
767
  nvgas = 1
768
 
769
  device 0
770
    baseaddr = 0xb0000000
771
    irq = 20
772
    refresh_rate = 100000
773
    filename = "primary"
774
  enddevice
775
end
776
 
777
 
778 833 simons
/* TICK TIMER SECTION
779 809 simons
 
780 833 simons
    This section configures tick timer
781 809 simons
 
782 833 simons
    enabled = 0/1
783
      whether tick timer is enabled
784 809 simons
 
785 833 simons
    irq = 
786
      irq number
787 809 simons
*/
788 878 rherveille
/*
789 833 simons
section tick
790
  enabled = 1
791
  irq = 0
792 809 simons
end
793 878 rherveille
*/
794 809 simons
 
795 878 rherveille
/* FB SECTION
796
 
797
    This section configures the frame buffer
798
 
799
    enabled = 0/1
800
      whether frame buffer is enabled
801
 
802
    baseaddr = 
803
      base address of frame buffer
804
 
805
    paladdr = 
806
      base address of first palette entry
807
 
808
    refresh_rate = 
809
      number of cycles between screen dumps
810
 
811
    filename = ""
812
      template name for generated names (e.g. "primary" produces "primary0023.bmp")
813
*/
814
 
815 809 simons
section fb
816
  enabled = 1
817 833 simons
  baseaddr = 0xc0000000
818
  refresh_rate = 1000000
819 809 simons
  filename = "primary"
820
end
821
 
822 878 rherveille
 
823 809 simons
/* KBD SECTION
824
 
825 878 rherveille
    This section configures the PS/2 compatible keyboard
826
 
827 809 simons
    enabled = 0/1
828
      whether keyboard is enabled
829 878 rherveille
 
830 809 simons
    baseaddr = 
831
      base address of the keyboard device
832 878 rherveille
 
833 809 simons
    rxfile = ""
834
      filename, where to read data from
835
*/
836
 
837
section kbd
838
  enabled = 1
839 833 simons
  irq = 12
840
  baseaddr = 0x98000000
841
  rxfile = "kbd.rx"
842 809 simons
end
843 833 simons
 
844 878 rherveille
 
845
/* ATA SECTION
846
 
847
    This section configures the ATA/ATAPI host controller
848
 
849
    natas = 
850
       number of ATA hosts connected
851
 
852
    instance specific:
853
      baseaddr = 
854
        address of first ATA register
855
 
856
      irq = 
857
        irq number for this device
858
 
859
      debug = 
860
        debug level for ata models.
861
        0: no debug messages
862
        1: verbose messages
863
        3: normal messages (more messages than verbose)
864
        5: debug messages (normal debug messages)
865
        7: flow control messages (debug statemachine flows)
866
        9: low priority message (display everything the code does)
867
 
868
      dev_type0/1 = 
869
        ata device 0 type
870
        0: NO_CONNeCT: none (not connected)
871
        1: FILE      : simulated harddisk
872
        2: LOCAL     : local system harddisk
873
 
874
      dev_file0/1 = ""
875
        filename for simulated ATA device
876
        valid only if dev_type0 == 1
877
 
878
      dev_size0/1 = 
879
        size of simulated hard-disk (in MBytes)
880
        valid only if dev_type0 == 1
881
 
882
      dev_packet0/1 = 
883
        0: simulated ATA device does NOT implement PACKET command feature set
884
        1: simulated ATA device does implement PACKET command feature set
885
 
886
   FIXME: irq number
887
*/
888
 
889
section ata
890
  natas = 1
891
 
892
  device 0
893
    baseaddr = 0xc8000000
894
    irq = 21
895
 
896
    dev_type0   = 1
897
    dev_file0   = "/tmp/sim_atadev0"
898
    dev_size0   = 1
899
    dev_packet0 = 0
900
 
901
    dev_type1   = 0
902
    dev_file1   = ""
903
    dev_size1   = 0
904
    dev_packet1 = 0
905
  enddevice
906
end

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