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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Testbench for the system                                    ////

////                                                              ////

////                                                              ////

////  Description                                                 ////

////  Resets the system, applies the clk and moves the TAP        ////

////  around some states. If you have loaded a program in the     ////

////  ZBT RAM model, it will run                                  ////

////                                                              ////

////  To Do:                                                      ////

////   - nothing really                                           ////

////                                                              ////

////  Author(s):                                                  ////

////      - Javier Castillo, jcastillo@opensocdesign.com          ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2004 OpenCores                                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// synopsys translate_off

`include "timescale.v"

// synopsys translate_on

`include "or1200_defines.v"

module rc203_test;

   reg    clk_i;

   reg    rst_i;

   wire   [19:0] sram_address;

   wire   [3:0] sram_nBW;

   wire   sram_nRW;

   wire   sram_nCS;

   wire   sram_clk;

   tri    [31:0] sram_data;

   wire   uart_stx;

   reg    uart_srx;

   reg    jtag_tdi;

   reg    jtag_tms;

   reg    jtag_tck;

   wire   jtag_tdo;

soc soc(

   .clk(clk_i),

   .reset(rst_i),

   .sram_nRW(sram_nRW),

   .sram_nBW(sram_nBW),

   .sram_address(sram_address),

   .sram_nCS(sram_nCS),

   .sram_data(sram_data),

   .sram_clk(sram_clk),

   .uart_srx(uart_srx),

   .uart_stx(uart_stx),

   .jtag_tdi(jtag_tdi),

   .jtag_tms(jtag_tms),

   .jtag_tck(jtag_tck),

   .jtag_tdo(jtag_tdo)

  );

//

// If you load a hex file in the RAM model 

// OR1200 will boot from here

//

zbtram zbtram(

   .clk(sram_clk),

   .nBW(sram_nBW),

   .address(sram_address),

   .data(sram_data),

   .nCS(sram_nCS),

   .nRW(sram_nRW)

   );

   initial

   begin

     $display("Beggining");

     uart_srx=1;

     jtag_tck=1;

     jtag_tdi=0;

     jtag_tms=0;

     clk_i='b1;

     rst_i='b1;

     rst_i=#101'b0;

     #100;

     //JTAG IR DEBUG

     jtag_tms=1;

     #100;

     jtag_tck=0;

     #100;

     jtag_tck=1;

     #100;

     jtag_tck=0;

     #100;

     jtag_tck=1;

     #100;

     jtag_tck=0;

     #100;

     jtag_tck=1;

     #100;

     jtag_tck=0;

     #100;

     jtag_tck=1;

     #100;

     jtag_tck=0;

     #100;

     //TAP reseted

     jtag_tms=0;

     jtag_tck=1;

     #100;

     jtag_tck=0;

     #100;

     //RUN state

     jtag_tms=1;

     jtag_tck=1;

     #100;

     jtag_tck=0;

     #100;

     jtag_tck=1;

     #100;

     jtag_tck=0;

     #100;

     //SelectIR

     jtag_tms=0;

     jtag_tck=1;

     #100;

     jtag_tck=0;

     #100;

     jtag_tck=1;

     #100;

     jtag_tck=0;

     #100;

     //Shift IR

     jtag_tms=0;

     jtag_tck=1;

     jtag_tdi=0;

     #100;

     jtag_tck=0;

     #100;

     jtag_tck=1;

     #100;

     jtag_tck=0;

     #100;

     jtag_tck=1;

     #100;

     jtag_tck=0;

     #100;

     jtag_tck=1;

     jtag_tdi=1;

     jtag_tms=1;

     #100;

     jtag_tck=0;

     #100;

     //Exit

     jtag_tck=1;

     jtag_tms=1;

     #100

     jtag_tck=0;

     #100;

     jtag_tck=1;

     jtag_tms=0;

     #100;

     jtag_tck=0;

     #100;

     jtag_tck=1;

     #100;

   end

always #5 clk_i=!clk_i;

endmodule