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[/] [or1k/] [trunk/] [rc203soc/] [rtl/] [verilog/] [or1200/] [rtl/] [verilog/] [or1200_dc_ram.v] - Blame information for rev 1765

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's DC RAMs                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Instatiation of DC RAM blocks.                              ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.6  2004/06/08 18:17:36  lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.5  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2.4.2  2003/12/10 15:28:28  simons
// Support for ram with byte selects added.
//
// Revision 1.2.4.1  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.2  2002/10/17 20:04:40  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.2  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.1  2001/07/20 00:46:03  lampret
// Development version of RTL. Libraries are missing.
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_dc_ram(
        // Reset and clock
        clk, rst,
 
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
        // Internal i/f
        addr, en, we, datain, dataout
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_DCINDX;
 
//
// I/O
//
input                           clk;
input                           rst;
input   [aw-1:0]         addr;
input                           en;
input   [3:0]                    we;
input   [dw-1:0]         datain;
output  [dw-1:0]         dataout;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input                           mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
output                          mbist_so_o;
`endif
 
`ifdef OR1200_NO_DC
 
//
// Data cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
 
`else
 
//
// Instantiation of RAM block
//
`ifdef OR1200_DC_1W_4KB
or1200_spram_1024x32_bw dc_ram(
`endif
`ifdef OR1200_DC_1W_8KB
or1200_spram_2048x32_bw dc_ram(
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .clk(clk),
        .rst(rst),
        .ce(en),
        .we(we),
        .oe(1'b1),
        .addr(addr),
        .di(datain),
        .doq(dataout)
);
`endif
endmodule

Line No.	Rev	Author	Line
1	1327	jcastillo
2			`//////////////////////////////////////////////////////////////////////`
3			`//// ////`
4			`//// OR1200's DC RAMs ////`
5			`//// ////`
6			`//// This file is part of the OpenRISC 1200 project ////`
7			`//// http://www.opencores.org/cores/or1k/ ////`
8			`//// ////`
9			`//// Description ////`
10			`//// Instatiation of DC RAM blocks. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - make it smaller and faster ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`// Revision 1.6 2004/06/08 18:17:36 lampret`
49			`// Non-functional changes. Coding style fixes.`
50			`//`
51			`// Revision 1.5 2004/04/05 08:29:57 lampret`
52			`// Merged branch_qmem into main tree.`
53			`//`
54			`// Revision 1.2.4.2 2003/12/10 15:28:28 simons`
55			`// Support for ram with byte selects added.`
56			`//`
57			`// Revision 1.2.4.1 2003/12/09 11:46:48 simons`
58			`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
59			`//`
60			`// Revision 1.2 2002/10/17 20:04:40 lampret`
61			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
62			`//`
63			`// Revision 1.1 2002/01/03 08:16:15 lampret`
64			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
65			`//`
66			`// Revision 1.8 2001/10/21 17:57:16 lampret`
67			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
68			`//`
69			`// Revision 1.7 2001/10/14 13:12:09 lampret`
70			`// MP3 version.`
71			`//`
72			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
73			`// no message`
74			`//`
75			`// Revision 1.2 2001/08/09 13:39:33 lampret`
76			`// Major clean-up.`
77			`//`
78			`// Revision 1.1 2001/07/20 00:46:03 lampret`
79			`// Development version of RTL. Libraries are missing.`
80			`//`
81			`//`
82
83			`// synopsys translate_off`
84			`include "timescale.v"
85			`// synopsys translate_on`
86			`include "or1200_defines.v"
87
88			`module or1200_dc_ram(`
89			`// Reset and clock`
90			`clk, rst,`
91
92			`ifdef OR1200_BIST
93			`// RAM BIST`
94			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
95			`endif
96
97			`// Internal i/f`
98			`addr, en, we, datain, dataout`
99			`);`
100
101			parameter dw = `OR1200_OPERAND_WIDTH;
102			parameter aw = `OR1200_DCINDX;
103
104			`//`
105			`// I/O`
106			`//`
107			`input clk;`
108			`input rst;`
109			`input [aw-1:0] addr;`
110			`input en;`
111			`input [3:0] we;`
112			`input [dw-1:0] datain;`
113			`output [dw-1:0] dataout;`
114
115			`ifdef OR1200_BIST
116			`//`
117			`// RAM BIST`
118			`//`
119			`input mbist_si_i;`
120			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
121			`output mbist_so_o;`
122			`endif
123
124			`ifdef OR1200_NO_DC
125
126			`//`
127			`// Data cache not implemented`
128			`//`
129			`assign dataout = {dw{1'b0}};`
130			`ifdef OR1200_BIST
131			`assign mbist_so_o = mbist_si_i;`
132			`endif
133
134			`else
135
136			`//`
137			`// Instantiation of RAM block`
138			`//`
139			`ifdef OR1200_DC_1W_4KB
140			`or1200_spram_1024x32_bw dc_ram(`
141			`endif
142			`ifdef OR1200_DC_1W_8KB
143			`or1200_spram_2048x32_bw dc_ram(`
144			`endif
145			`ifdef OR1200_BIST
146			`// RAM BIST`
147			`.mbist_si_i(mbist_si_i),`
148			`.mbist_so_o(mbist_so_o),`
149			`.mbist_ctrl_i(mbist_ctrl_i),`
150			`endif
151			`.clk(clk),`
152			`.rst(rst),`
153			`.ce(en),`
154			`.we(we),`
155			`.oe(1'b1),`
156			`.addr(addr),`
157			`.di(datain),`
158			`.doq(dataout)`
159			`);`
160			`endif
161			`endmodule`

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[/] [or1k/] [trunk/] [rc203soc/] [rtl/] [verilog/] [or1200/] [rtl/] [verilog/] [or1200_dc_ram.v] - Blame information for rev 1765