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[/] [or1k/] [trunk/] [rc203soc/] [rtl/] [verilog/] [or1200/] [rtl/] [verilog/] [or1200_mult_mac.v] - Blame information for rev 1765

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Top level multiplier and MAC                       ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/cores/or1k/                        ////
////                                                              ////
////  Description                                                 ////
////  Multiplier is 32x32 however multiply instructions only      ////
////  use lower 32 bits of the result. MAC is 32x32=64+64.        ////
////                                                              ////
////  To Do:                                                      ////
////   - make signed division better, w/o negating the operands   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2004/06/08 18:17:36  lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.3  2003/04/24 00:16:07  lampret
// No functional changes. Added defines to disable implementation of multiplier/MAC
//
// Revision 1.2  2002/09/08 05:52:16  lampret
// Added optional l.div/l.divu insns. By default they are disabled.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.3  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.2  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:38  igorm
// no message
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_mult_mac(
        // Clock and reset
        clk, rst,
 
        // Multiplier/MAC interface
        ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op, result, mac_stall_r,
 
        // SPR interface
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// Multiplier/MAC interface
//
input                           ex_freeze;
input                           id_macrc_op;
input                           macrc_op;
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [`OR1200_MACOP_WIDTH-1:0]        mac_op;
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
output  [width-1:0]              result;
output                          mac_stall_r;
 
//
// SPR interface
//
input                           spr_cs;
input                           spr_write;
input   [31:0]                   spr_addr;
input   [31:0]                   spr_dat_i;
output  [31:0]                   spr_dat_o;
 
//
// Internal wires and regs
//
`ifdef OR1200_MULT_IMPLEMENTED
reg     [width-1:0]              result;
reg     [2*width-1:0]            mul_prod_r;
`else
wire    [width-1:0]              result;
wire    [2*width-1:0]            mul_prod_r;
`endif
wire    [2*width-1:0]            mul_prod;
wire    [`OR1200_MACOP_WIDTH-1:0]        mac_op;
`ifdef OR1200_MAC_IMPLEMENTED
reg     [`OR1200_MACOP_WIDTH-1:0]        mac_op_r1;
reg     [`OR1200_MACOP_WIDTH-1:0]        mac_op_r2;
reg     [`OR1200_MACOP_WIDTH-1:0]        mac_op_r3;
reg                             mac_stall_r;
reg     [2*width-1:0]            mac_r;
`else
wire    [`OR1200_MACOP_WIDTH-1:0]        mac_op_r1;
wire    [`OR1200_MACOP_WIDTH-1:0]        mac_op_r2;
wire    [`OR1200_MACOP_WIDTH-1:0]        mac_op_r3;
wire                            mac_stall_r;
wire    [2*width-1:0]            mac_r;
`endif
wire    [width-1:0]              x;
wire    [width-1:0]              y;
wire                            spr_maclo_we;
wire                            spr_machi_we;
wire                            alu_op_div_divu;
wire                            alu_op_div;
reg                             div_free;
`ifdef OR1200_IMPL_DIV
wire    [width-1:0]              div_tmp;
reg     [5:0]                    div_cntr;
`endif
 
//
// Combinatorial logic
//
`ifdef OR1200_MAC_IMPLEMENTED
assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];
assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];
`else
assign spr_maclo_we = 1'b0;
assign spr_machi_we = 1'b0;
assign spr_dat_o = 32'h0000_0000;
`endif
`ifdef OR1200_LOWPWR_MULT
assign x = (alu_op_div & a[31]) ? ~a + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? a : 32'h0000_0000;
assign y = (alu_op_div & b[31]) ? ~b + 1'b1 : alu_op_div_divu | (alu_op == `OR1200_ALUOP_MUL) | (|mac_op) ? b : 32'h0000_0000;
`else
assign x = alu_op_div & a[31] ? ~a + 32'b1 : a;
assign y = alu_op_div & b[31] ? ~b + 32'b1 : b;
`endif
`ifdef OR1200_IMPL_DIV
assign alu_op_div = (alu_op == `OR1200_ALUOP_DIV);
assign alu_op_div_divu = alu_op_div | (alu_op == `OR1200_ALUOP_DIVU);
assign div_tmp = mul_prod_r[63:32] - y;
`else
assign alu_op_div = 1'b0;
assign alu_op_div_divu = 1'b0;
`endif
 
`ifdef OR1200_MULT_IMPLEMENTED
 
//
// Select result of current ALU operation to be forwarded
// to next instruction and to WB stage
//
always @(alu_op or mul_prod_r or mac_r or a or b)
        casex(alu_op)   // synopsys parallel_case
`ifdef OR1200_IMPL_DIV
                `OR1200_ALUOP_DIV:
                        result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 1'b1 : mul_prod_r[31:0];
                `OR1200_ALUOP_DIVU,
`endif
                `OR1200_ALUOP_MUL: begin
                        result = mul_prod_r[31:0];
                end
                default:
                        result = mac_r[59:28];
        endcase
 
//
// Instantiation of the multiplier
//
`ifdef OR1200_ASIC_MULTP2_32X32
or1200_amultp2_32x32 or1200_amultp2_32x32(
        .X(x),
        .Y(y),
        .RST(rst),
        .CLK(clk),
        .P(mul_prod)
);
`else // OR1200_ASIC_MULTP2_32X32
or1200_gmultp2_32x32 or1200_gmultp2_32x32(
        .X(x),
        .Y(y),
        .RST(rst),
        .CLK(clk),
        .P(mul_prod)
);
`endif // OR1200_ASIC_MULTP2_32X32
 
//
// Registered output from the multiplier and
// an optional divider
//
always @(posedge rst or posedge clk)
        if (rst) begin
                mul_prod_r <= #1 64'h0000_0000_0000_0000;
                div_free <= #1 1'b1;
`ifdef OR1200_IMPL_DIV
                div_cntr <= #1 6'b00_0000;
`endif
        end
`ifdef OR1200_IMPL_DIV
        else if (|div_cntr) begin
                if (div_tmp[31])
                        mul_prod_r <= #1 {mul_prod_r[62:0], 1'b0};
                else
                        mul_prod_r <= #1 {div_tmp[30:0], mul_prod_r[31:0], 1'b1};
                div_cntr <= #1 div_cntr - 1'b1;
        end
        else if (alu_op_div_divu && div_free) begin
                mul_prod_r <= #1 {31'b0, x[31:0], 1'b0};
                div_cntr <= #1 6'b10_0000;
                div_free <= #1 1'b0;
        end
`endif // OR1200_IMPL_DIV
        else if (div_free | !ex_freeze) begin
                mul_prod_r <= #1 mul_prod[63:0];
                div_free <= #1 1'b1;
        end
 
`else // OR1200_MULT_IMPLEMENTED
assign result = {width{1'b0}};
assign mul_prod = {2*width{1'b0}};
assign mul_prod_r = {2*width{1'b0}};
`endif // OR1200_MULT_IMPLEMENTED
 
`ifdef OR1200_MAC_IMPLEMENTED
 
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
        if (rst)
                mac_op_r1 <= #1 `OR1200_MACOP_WIDTH'b0;
        else
                mac_op_r1 <= #1 mac_op;
 
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
        if (rst)
                mac_op_r2 <= #1 `OR1200_MACOP_WIDTH'b0;
        else
                mac_op_r2 <= #1 mac_op_r1;
 
//
// Propagation of l.mac opcode
//
always @(posedge clk or posedge rst)
        if (rst)
                mac_op_r3 <= #1 `OR1200_MACOP_WIDTH'b0;
        else
                mac_op_r3 <= #1 mac_op_r2;
 
//
// Implementation of MAC
//
always @(posedge rst or posedge clk)
        if (rst)
                mac_r <= #1 64'h0000_0000_0000_0000;
`ifdef OR1200_MAC_SPR_WE
        else if (spr_maclo_we)
                mac_r[31:0] <= #1 spr_dat_i;
        else if (spr_machi_we)
                mac_r[63:32] <= #1 spr_dat_i;
`endif
        else if (mac_op_r3 == `OR1200_MACOP_MAC)
                mac_r <= #1 mac_r + mul_prod_r;
        else if (mac_op_r3 == `OR1200_MACOP_MSB)
                mac_r <= #1 mac_r - mul_prod_r;
        else if (macrc_op & !ex_freeze)
                mac_r <= #1 64'h0000_0000_0000_0000;
 
//
// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions
// in EX stage (e.g. inside multiplier)
// This stall signal is also used by the divider.
//
always @(posedge rst or posedge clk)
        if (rst)
                mac_stall_r <= #1 1'b0;
        else
                mac_stall_r <= #1 (|mac_op | (|mac_op_r1) | (|mac_op_r2)) & id_macrc_op
`ifdef OR1200_IMPL_DIV
                                | (|div_cntr)
`endif
                                ;
`else // OR1200_MAC_IMPLEMENTED
assign mac_stall_r = 1'b0;
assign mac_r = {2*width{1'b0}};
assign mac_op_r1 = `OR1200_MACOP_WIDTH'b0;
assign mac_op_r2 = `OR1200_MACOP_WIDTH'b0;
assign mac_op_r3 = `OR1200_MACOP_WIDTH'b0;
`endif // OR1200_MAC_IMPLEMENTED
 
endmodule

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[/] [or1k/] [trunk/] [rc203soc/] [rtl/] [verilog/] [or1200/] [rtl/] [verilog/] [or1200_mult_mac.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	1327	jcastillo	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Top level multiplier and MAC ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/cores/or1k/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Multiplier is 32x32 however multiply instructions only ////`
10			`//// use lower 32 bits of the result. MAC is 32x32=64+64. ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// - make signed division better, w/o negating the operands ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Damjan Lampret, lampret@opencores.org ////`
17			`//// ////`
18			`//////////////////////////////////////////////////////////////////////`
19			`//// ////`
20			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
21			`//// ////`
22			`//// This source file may be used and distributed without ////`
23			`//// restriction provided that this copyright statement is not ////`
24			`//// removed from the file and that any derivative work contains ////`
25			`//// the original copyright notice and the associated disclaimer. ////`
26			`//// ////`
27			`//// This source file is free software; you can redistribute it ////`
28			`//// and/or modify it under the terms of the GNU Lesser General ////`
29			`//// Public License as published by the Free Software Foundation; ////`
30			`//// either version 2.1 of the License, or (at your option) any ////`
31			`//// later version. ////`
32			`//// ////`
33			`//// This source is distributed in the hope that it will be ////`
34			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
35			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
36			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
37			`//// details. ////`
38			`//// ////`
39			`//// You should have received a copy of the GNU Lesser General ////`
40			`//// Public License along with this source; if not, download it ////`
41			`//// from http://www.opencores.org/lgpl.shtml ////`
42			`//// ////`
43			`//////////////////////////////////////////////////////////////////////`
44			`//`
45			`// CVS Revision History`
46			`//`
47			`// $Log: not supported by cvs2svn $`
48			`// Revision 1.4 2004/06/08 18:17:36 lampret`
49			`// Non-functional changes. Coding style fixes.`
50			`//`
51			`// Revision 1.3 2003/04/24 00:16:07 lampret`
52			`// No functional changes. Added defines to disable implementation of multiplier/MAC`
53			`//`
54			`// Revision 1.2 2002/09/08 05:52:16 lampret`
55			`// Added optional l.div/l.divu insns. By default they are disabled.`
56			`//`
57			`// Revision 1.1 2002/01/03 08:16:15 lampret`
58			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
59			`//`
60			`// Revision 1.3 2001/10/21 17:57:16 lampret`
61			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
62			`//`
63			`// Revision 1.2 2001/10/14 13:12:09 lampret`
64			`// MP3 version.`
65			`//`
66			`// Revision 1.1.1.1 2001/10/06 10:18:38 igorm`
67			`// no message`
68			`//`
69			`//`
70
71			`// synopsys translate_off`
72			`include "timescale.v"
73			`// synopsys translate_on`
74			`include "or1200_defines.v"
75
76			`module or1200_mult_mac(`
77			`// Clock and reset`
78			`clk, rst,`
79
80			`// Multiplier/MAC interface`
81			`ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op, result, mac_stall_r,`
82
83			`// SPR interface`
84			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o`
85			`);`
86
87			parameter width = `OR1200_OPERAND_WIDTH;
88
89			`//`
90			`// I/O`
91			`//`
92
93			`//`
94			`// Clock and reset`
95			`//`
96			`input clk;`
97			`input rst;`
98
99			`//`
100			`// Multiplier/MAC interface`
101			`//`
102			`input ex_freeze;`
103			`input id_macrc_op;`
104			`input macrc_op;`
105			`input [width-1:0] a;`
106			`input [width-1:0] b;`
107			input [`OR1200_MACOP_WIDTH-1:0] mac_op;
108			input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
109			`output [width-1:0] result;`
110			`output mac_stall_r;`
111
112			`//`
113			`// SPR interface`
114			`//`
115			`input spr_cs;`
116			`input spr_write;`
117			`input [31:0] spr_addr;`
118			`input [31:0] spr_dat_i;`
119			`output [31:0] spr_dat_o;`
120
121			`//`
122			`// Internal wires and regs`
123			`//`
124			`ifdef OR1200_MULT_IMPLEMENTED
125			`reg [width-1:0] result;`
126			`reg [2*width-1:0] mul_prod_r;`
127			`else
128			`wire [width-1:0] result;`
129			`wire [2*width-1:0] mul_prod_r;`
130			`endif
131			`wire [2*width-1:0] mul_prod;`
132			wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
133			`ifdef OR1200_MAC_IMPLEMENTED
134			reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
135			reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
136			reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
137			`reg mac_stall_r;`
138			`reg [2*width-1:0] mac_r;`
139			`else
140			wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
141			wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
142			wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
143			`wire mac_stall_r;`
144			`wire [2*width-1:0] mac_r;`
145			`endif
146			`wire [width-1:0] x;`
147			`wire [width-1:0] y;`
148			`wire spr_maclo_we;`
149			`wire spr_machi_we;`
150			`wire alu_op_div_divu;`
151			`wire alu_op_div;`
152			`reg div_free;`
153			`ifdef OR1200_IMPL_DIV
154			`wire [width-1:0] div_tmp;`
155			`reg [5:0] div_cntr;`
156			`endif
157
158			`//`
159			`// Combinatorial logic`
160			`//`
161			`ifdef OR1200_MAC_IMPLEMENTED
162			assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
163			assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];
164			assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];
165			`else
166			`assign spr_maclo_we = 1'b0;`
167			`assign spr_machi_we = 1'b0;`
168			`assign spr_dat_o = 32'h0000_0000;`
169			`endif
170			`ifdef OR1200_LOWPWR_MULT
171			assign x = (alu_op_div & a[31]) ? ~a + 1'b1 : alu_op_div_divu \| (alu_op == `OR1200_ALUOP_MUL) \| (\|mac_op) ? a : 32'h0000_0000;
172			assign y = (alu_op_div & b[31]) ? ~b + 1'b1 : alu_op_div_divu \| (alu_op == `OR1200_ALUOP_MUL) \| (\|mac_op) ? b : 32'h0000_0000;
173			`else
174			`assign x = alu_op_div & a[31] ? ~a + 32'b1 : a;`
175			`assign y = alu_op_div & b[31] ? ~b + 32'b1 : b;`
176			`endif
177			`ifdef OR1200_IMPL_DIV
178			assign alu_op_div = (alu_op == `OR1200_ALUOP_DIV);
179			assign alu_op_div_divu = alu_op_div \| (alu_op == `OR1200_ALUOP_DIVU);
180			`assign div_tmp = mul_prod_r[63:32] - y;`
181			`else
182			`assign alu_op_div = 1'b0;`
183			`assign alu_op_div_divu = 1'b0;`
184			`endif
185
186			`ifdef OR1200_MULT_IMPLEMENTED
187
188			`//`
189			`// Select result of current ALU operation to be forwarded`
190			`// to next instruction and to WB stage`
191			`//`
192			`always @(alu_op or mul_prod_r or mac_r or a or b)`
193			`casex(alu_op) // synopsys parallel_case`
194			`ifdef OR1200_IMPL_DIV
195			`OR1200_ALUOP_DIV:
196			`result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 1'b1 : mul_prod_r[31:0];`
197			`OR1200_ALUOP_DIVU,
198			`endif
199			`OR1200_ALUOP_MUL: begin
200			`result = mul_prod_r[31:0];`
201			`end`
202			`default:`
203			`result = mac_r[59:28];`
204			`endcase`
205
206			`//`
207			`// Instantiation of the multiplier`
208			`//`
209			`ifdef OR1200_ASIC_MULTP2_32X32
210			`or1200_amultp2_32x32 or1200_amultp2_32x32(`
211			`.X(x),`
212			`.Y(y),`
213			`.RST(rst),`
214			`.CLK(clk),`
215			`.P(mul_prod)`
216			`);`
217			`else // OR1200_ASIC_MULTP2_32X32
218			`or1200_gmultp2_32x32 or1200_gmultp2_32x32(`
219			`.X(x),`
220			`.Y(y),`
221			`.RST(rst),`
222			`.CLK(clk),`
223			`.P(mul_prod)`
224			`);`
225			`endif // OR1200_ASIC_MULTP2_32X32
226
227			`//`
228			`// Registered output from the multiplier and`
229			`// an optional divider`
230			`//`
231			`always @(posedge rst or posedge clk)`
232			`if (rst) begin`
233			`mul_prod_r <= #1 64'h0000_0000_0000_0000;`
234			`div_free <= #1 1'b1;`
235			`ifdef OR1200_IMPL_DIV
236			`div_cntr <= #1 6'b00_0000;`
237			`endif
238			`end`
239			`ifdef OR1200_IMPL_DIV
240			`else if (\|div_cntr) begin`
241			`if (div_tmp[31])`
242			`mul_prod_r <= #1 {mul_prod_r[62:0], 1'b0};`
243			`else`
244			`mul_prod_r <= #1 {div_tmp[30:0], mul_prod_r[31:0], 1'b1};`
245			`div_cntr <= #1 div_cntr - 1'b1;`
246			`end`
247			`else if (alu_op_div_divu && div_free) begin`
248			`mul_prod_r <= #1 {31'b0, x[31:0], 1'b0};`
249			`div_cntr <= #1 6'b10_0000;`
250			`div_free <= #1 1'b0;`
251			`end`
252			`endif // OR1200_IMPL_DIV
253			`else if (div_free \| !ex_freeze) begin`
254			`mul_prod_r <= #1 mul_prod[63:0];`
255			`div_free <= #1 1'b1;`
256			`end`
257
258			`else // OR1200_MULT_IMPLEMENTED
259			`assign result = {width{1'b0}};`
260			`assign mul_prod = {2*width{1'b0}};`
261			`assign mul_prod_r = {2*width{1'b0}};`
262			`endif // OR1200_MULT_IMPLEMENTED
263
264			`ifdef OR1200_MAC_IMPLEMENTED
265
266			`//`
267			`// Propagation of l.mac opcode`
268			`//`
269			`always @(posedge clk or posedge rst)`
270			`if (rst)`
271			mac_op_r1 <= #1 `OR1200_MACOP_WIDTH'b0;
272			`else`
273			`mac_op_r1 <= #1 mac_op;`
274
275			`//`
276			`// Propagation of l.mac opcode`
277			`//`
278			`always @(posedge clk or posedge rst)`
279			`if (rst)`
280			mac_op_r2 <= #1 `OR1200_MACOP_WIDTH'b0;
281			`else`
282			`mac_op_r2 <= #1 mac_op_r1;`
283
284			`//`
285			`// Propagation of l.mac opcode`
286			`//`
287			`always @(posedge clk or posedge rst)`
288			`if (rst)`
289			mac_op_r3 <= #1 `OR1200_MACOP_WIDTH'b0;
290			`else`
291			`mac_op_r3 <= #1 mac_op_r2;`
292
293			`//`
294			`// Implementation of MAC`
295			`//`
296			`always @(posedge rst or posedge clk)`
297			`if (rst)`
298			`mac_r <= #1 64'h0000_0000_0000_0000;`
299			`ifdef OR1200_MAC_SPR_WE
300			`else if (spr_maclo_we)`
301			`mac_r[31:0] <= #1 spr_dat_i;`
302			`else if (spr_machi_we)`
303			`mac_r[63:32] <= #1 spr_dat_i;`
304			`endif
305			else if (mac_op_r3 == `OR1200_MACOP_MAC)
306			`mac_r <= #1 mac_r + mul_prod_r;`
307			else if (mac_op_r3 == `OR1200_MACOP_MSB)
308			`mac_r <= #1 mac_r - mul_prod_r;`
309			`else if (macrc_op & !ex_freeze)`
310			`mac_r <= #1 64'h0000_0000_0000_0000;`
311
312			`//`
313			`// Stall CPU if l.macrc is in ID and MAC still has to process l.mac instructions`
314			`// in EX stage (e.g. inside multiplier)`
315			`// This stall signal is also used by the divider.`
316			`//`
317			`always @(posedge rst or posedge clk)`
318			`if (rst)`
319			`mac_stall_r <= #1 1'b0;`
320			`else`
321			`mac_stall_r <= #1 (\|mac_op \| (\|mac_op_r1) \| (\|mac_op_r2)) & id_macrc_op`
322			`ifdef OR1200_IMPL_DIV
323			`\| (\|div_cntr)`
324			`endif
325			`;`
326			`else // OR1200_MAC_IMPLEMENTED
327			`assign mac_stall_r = 1'b0;`
328			`assign mac_r = {2*width{1'b0}};`
329			assign mac_op_r1 = `OR1200_MACOP_WIDTH'b0;
330			assign mac_op_r2 = `OR1200_MACOP_WIDTH'b0;
331			assign mac_op_r3 = `OR1200_MACOP_WIDTH'b0;
332			`endif // OR1200_MAC_IMPLEMENTED
333
334			`endmodule`