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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////                                                              ////
////  To Do:                                                      ////
////   - add support for other RAM's                              ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
//
// Revision 1.1  2004/04/08 11:00:46  simont
// Add support for 512B instruction cache.
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_128x32(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
);
 
//
// Default address and data buses width
//
parameter aw = 7;
parameter dw = 32;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] doq;    // output data bus
 
//
// Internal wires and registers
//
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
`endif
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
`else
`ifdef OR1200_BIST
`else
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
`endif
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
        .CLK(clk),
        .RST(rst),
        .ADDR({1'b0, addr}),
        .DI(di[15:0]),
        .EN(ce),
        .WE(we),
        .DO(doq[15:0])
);
 
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
        .CLK(clk),
        .RST(rst),
        .ADDR({1'b0, addr}),
        .DI(di[31:16]),
        .EN(ce),
        .WE(we),
        .DO(doq[31:16])
);
 
`else
 
`ifdef OR1200_ALTERA_LPM
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
 
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [aw-1:0] addr_reg;               // RAM address register
 
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
 
//
// RAM address register
//
always @(posedge clk or posedge rst)
        if (rst)
                addr_reg <= #1 {aw{1'b0}};
        else if (ce)
                addr_reg <= #1 addr;
 
//
// RAM write
//
always @(posedge clk)
        if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB4_S16
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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[/] [or1k/] [trunk/] [rc203soc/] [rtl/] [verilog/] [or1200/] [rtl/] [verilog/] [or1200_spram_128x32.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	1327	jcastillo	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// ////`
20			`//// Supported FPGA RAMs are: ////`
21			`//// - Xilinx Virtex RAMB4_S16 ////`
22			`//// ////`
23			`//// To Do: ////`
24			`//// - add support for other RAM's ////`
25			`//// - xilinx rams need external tri-state logic ////`
26			`//// - fix avant! two-port ram ////`
27			`//// - add additional RAMs ////`
28			`//// ////`
29			`//// Author(s): ////`
30			`//// - Damjan Lampret, lampret@opencores.org ////`
31			`//// ////`
32			`//////////////////////////////////////////////////////////////////////`
33			`//// ////`
34			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
35			`//// ////`
36			`//// This source file may be used and distributed without ////`
37			`//// restriction provided that this copyright statement is not ////`
38			`//// removed from the file and that any derivative work contains ////`
39			`//// the original copyright notice and the associated disclaimer. ////`
40			`//// ////`
41			`//// This source file is free software; you can redistribute it ////`
42			`//// and/or modify it under the terms of the GNU Lesser General ////`
43			`//// Public License as published by the Free Software Foundation; ////`
44			`//// either version 2.1 of the License, or (at your option) any ////`
45			`//// later version. ////`
46			`//// ////`
47			`//// This source is distributed in the hope that it will be ////`
48			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
49			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
50			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
51			`//// details. ////`
52			`//// ////`
53			`//// You should have received a copy of the GNU Lesser General ////`
54			`//// Public License along with this source; if not, download it ////`
55			`//// from http://www.opencores.org/lgpl.shtml ////`
56			`//// ////`
57			`//////////////////////////////////////////////////////////////////////`
58			`//`
59			`// CVS Revision History`
60			`//`
61			`// $Log: not supported by cvs2svn $`
62			`// Revision 1.2 2004/06/08 18:15:32 lampret`
63			`// Changed behavior of the simulation generic models`
64			`//`
65			`// Revision 1.1 2004/04/08 11:00:46 simont`
66			`// Add support for 512B instruction cache.`
67			`//`
68			`//`
69			`//`
70
71			`// synopsys translate_off`
72			`include "timescale.v"
73			`// synopsys translate_on`
74			`include "or1200_defines.v"
75
76			`module or1200_spram_128x32(`
77			`ifdef OR1200_BIST
78			`// RAM BIST`
79			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
80			`endif
81			`// Generic synchronous single-port RAM interface`
82			`clk, rst, ce, we, oe, addr, di, doq`
83			`);`
84
85			`//`
86			`// Default address and data buses width`
87			`//`
88			`parameter aw = 7;`
89			`parameter dw = 32;`
90
91			`ifdef OR1200_BIST
92			`//`
93			`// RAM BIST`
94			`//`
95			`input mbist_si_i;`
96			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
97			`output mbist_so_o;`
98			`endif
99
100			`//`
101			`// Generic synchronous single-port RAM interface`
102			`//`
103			`input clk; // Clock`
104			`input rst; // Reset`
105			`input ce; // Chip enable input`
106			`input we; // Write enable input`
107			`input oe; // Output enable input`
108			`input [aw-1:0] addr; // address bus inputs`
109			`input [dw-1:0] di; // input data bus`
110			`output [dw-1:0] doq; // output data bus`
111
112			`//`
113			`// Internal wires and registers`
114			`//`
115
116			`ifdef OR1200_ARTISAN_SSP
117			`else
118			`ifdef OR1200_VIRTUALSILICON_SSP
119			`else
120			`ifdef OR1200_BIST
121			`endif
122			`endif
123			`endif
124
125			`ifdef OR1200_ARTISAN_SSP
126
127			`//`
128			`// Instantiation of ASIC memory:`
129			`//`
130			`// Artisan Synchronous Single-Port RAM (ra1sh)`
131			`//`
132			`ifdef UNUSED
133			`else
134			`ifdef OR1200_BIST
135			`else
136			`endif
137			`endif
138			`ifdef OR1200_BIST
139			`endif
140			`else
141
142			`ifdef OR1200_AVANT_ATP
143
144			`//`
145			`// Instantiation of ASIC memory:`
146			`//`
147			`// Avant! Asynchronous Two-Port RAM`
148			`//`
149
150			`else
151
152			`ifdef OR1200_VIRAGE_SSP
153
154			`//`
155			`// Instantiation of ASIC memory:`
156			`//`
157			`// Virage Synchronous 1-port R/W RAM`
158			`//`
159
160			`else
161
162			`ifdef OR1200_VIRTUALSILICON_SSP
163
164			`//`
165			`// Instantiation of ASIC memory:`
166			`//`
167			`// Virtual Silicon Single-Port Synchronous SRAM`
168			`//`
169			`ifdef UNUSED
170			`else
171			`ifdef OR1200_BIST
172			`else
173			`endif
174			`endif
175			`ifdef OR1200_BIST
176			`// RAM BIST`
177			`endif
178
179			`else
180
181			`ifdef OR1200_XILINX_RAMB4
182
183			`//`
184			`// Instantiation of FPGA memory:`
185			`//`
186			`// Virtex/Spartan2`
187			`//`
188
189			`//`
190			`// Block 0`
191			`//`
192			`RAMB4_S16 ramb4_s16_0(`
193			`.CLK(clk),`
194			`.RST(rst),`
195			`.ADDR({1'b0, addr}),`
196			`.DI(di[15:0]),`
197			`.EN(ce),`
198			`.WE(we),`
199			`.DO(doq[15:0])`
200			`);`
201
202			`//`
203			`// Block 1`
204			`//`
205			`RAMB4_S16 ramb4_s16_1(`
206			`.CLK(clk),`
207			`.RST(rst),`
208			`.ADDR({1'b0, addr}),`
209			`.DI(di[31:16]),`
210			`.EN(ce),`
211			`.WE(we),`
212			`.DO(doq[31:16])`
213			`);`
214
215			`else
216
217			`ifdef OR1200_ALTERA_LPM
218
219			`//`
220			`// Instantiation of FPGA memory:`
221			`//`
222			`// Altera LPM`
223			`//`
224			`// Added By Jamil Khatib`
225			`//`
226
227
228			`else
229
230			`//`
231			`// Generic single-port synchronous RAM model`
232			`//`
233
234			`//`
235			`// Generic RAM's registers and wires`
236			`//`
237			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
238			`reg [aw-1:0] addr_reg; // RAM address register`
239
240			`//`
241			`// Data output drivers`
242			`//`
243			`assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};`
244
245			`//`
246			`// RAM address register`
247			`//`
248			`always @(posedge clk or posedge rst)`
249			`if (rst)`
250			`addr_reg <= #1 {aw{1'b0}};`
251			`else if (ce)`
252			`addr_reg <= #1 addr;`
253
254			`//`
255			`// RAM write`
256			`//`
257			`always @(posedge clk)`
258			`if (ce && we)`
259			`mem[addr] <= #1 di;`
260
261			`endif // !OR1200_ALTERA_LPM
262			`endif // !OR1200_XILINX_RAMB4_S16
263			`endif // !OR1200_VIRTUALSILICON_SSP
264			`endif // !OR1200_VIRAGE_SSP
265			`endif // !OR1200_AVANT_ATP
266			`endif // !OR1200_ARTISAN_SSP
267
268			`endmodule`