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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.2  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3.4.1  2003/07/08 15:36:37  lampret
// Added embedded memory QMEM.
//
// Revision 1.3  2003/04/07 01:19:07  lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2  2002/10/17 20:04:40  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/27 21:24:04  lampret
// Changed instantiation name of VS RAMs.
//
// Revision 1.9  2001/11/27 19:45:04  lampret
// Fixed VS RAM instantiation - again.
//
// Revision 1.8  2001/11/23 21:42:31  simons
// Program counter divided to PPC and NPC.
//
// Revision 1.6  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_256x21(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
);
 
//
// Default address and data buses width
//
parameter aw = 8;
parameter dw = 21;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] doq;    // output data bus
 
//
// Internal wires and registers
//
wire    [10:0]           unconnected;
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_256x21 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_256x21_bist artisan_ssp(
`else
art_hssp_256x21 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(doq)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .doq(doq)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(doq)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_256x21 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_256x21_bist vs_ssp(
`else
vs_hdsp_256x21 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16 ramb4_s16_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:0]),
        .EN(ce),
        .WE(we),
        .DO(doq[15:0])
);
 
//
// Block 1
//
RAMB4_S16 ramb4_s16_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI({11'b00000000000, di[20:16]}),
        .EN(ce),
        .WE(we),
        .DO({unconnected, doq[20:16]})
);
 
`else
 
`ifdef OR1200_ALTERA_LPM
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
 
wire    wr;
 
assign  wr = ce & we;
 
initial $display("Using Altera LPM.");
 
lpm_ram_dq lpm_ram_dq_component (
        .address(addr),
        .inclock(clk),
        .outclock(clk),
        .data(di),
        .we(wr),
        .q(doq)
);
 
defparam lpm_ram_dq_component.lpm_width = dw,
        lpm_ram_dq_component.lpm_widthad = aw,
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [aw-1:0] addr_reg;               // RAM address register
 
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
 
//
// RAM adress register
//
always @(posedge clk or posedge rst)
        if (rst)
                addr_reg <= #1 {aw{1'b0}};
        else if (ce)
                addr_reg <= #1 addr;
 
//
// RAM write
//
always @(posedge clk)
        if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB4_S16
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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[/] [or1k/] [trunk/] [rc203soc/] [rtl/] [verilog/] [or1200/] [rtl/] [verilog/] [or1200_spram_256x21.v] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	1327	jcastillo	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB4_S16 ////`
26			`//// - Altera LPM ////`
27			`//// ////`
28			`//// To Do: ////`
29			`//// - xilinx rams need external tri-state logic ////`
30			`//// - fix avant! two-port ram ////`
31			`//// - add additional RAMs ////`
32			`//// ////`
33			`//// Author(s): ////`
34			`//// - Damjan Lampret, lampret@opencores.org ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: not supported by cvs2svn $`
66			`// Revision 1.8 2004/06/08 18:15:32 lampret`
67			`// Changed behavior of the simulation generic models`
68			`//`
69			`// Revision 1.7 2004/04/05 08:29:57 lampret`
70			`// Merged branch_qmem into main tree.`
71			`//`
72			`// Revision 1.3.4.2 2003/12/09 11:46:48 simons`
73			`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
74			`//`
75			`// Revision 1.3.4.1 2003/07/08 15:36:37 lampret`
76			`// Added embedded memory QMEM.`
77			`//`
78			`// Revision 1.3 2003/04/07 01:19:07 lampret`
79			`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
80			`//`
81			`// Revision 1.2 2002/10/17 20:04:40 lampret`
82			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
83			`//`
84			`// Revision 1.1 2002/01/03 08:16:15 lampret`
85			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
86			`//`
87			`// Revision 1.10 2001/11/27 21:24:04 lampret`
88			`// Changed instantiation name of VS RAMs.`
89			`//`
90			`// Revision 1.9 2001/11/27 19:45:04 lampret`
91			`// Fixed VS RAM instantiation - again.`
92			`//`
93			`// Revision 1.8 2001/11/23 21:42:31 simons`
94			`// Program counter divided to PPC and NPC.`
95			`//`
96			`// Revision 1.6 2001/10/21 17:57:16 lampret`
97			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
98			`//`
99			`// Revision 1.5 2001/10/14 13:12:09 lampret`
100			`// MP3 version.`
101			`//`
102			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
103			`// no message`
104			`//`
105			`// Revision 1.1 2001/08/09 13:39:33 lampret`
106			`// Major clean-up.`
107			`//`
108			`// Revision 1.2 2001/07/30 05:38:02 lampret`
109			`// Adding empty directories required by HDL coding guidelines`
110			`//`
111			`//`
112
113			`// synopsys translate_off`
114			`include "timescale.v"
115			`// synopsys translate_on`
116			`include "or1200_defines.v"
117
118			`module or1200_spram_256x21(`
119			`ifdef OR1200_BIST
120			`// RAM BIST`
121			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
122			`endif
123			`// Generic synchronous single-port RAM interface`
124			`clk, rst, ce, we, oe, addr, di, doq`
125			`);`
126
127			`//`
128			`// Default address and data buses width`
129			`//`
130			`parameter aw = 8;`
131			`parameter dw = 21;`
132
133			`ifdef OR1200_BIST
134			`//`
135			`// RAM BIST`
136			`//`
137			`input mbist_si_i;`
138			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
139			`output mbist_so_o;`
140			`endif
141
142			`//`
143			`// Generic synchronous single-port RAM interface`
144			`//`
145			`input clk; // Clock`
146			`input rst; // Reset`
147			`input ce; // Chip enable input`
148			`input we; // Write enable input`
149			`input oe; // Output enable input`
150			`input [aw-1:0] addr; // address bus inputs`
151			`input [dw-1:0] di; // input data bus`
152			`output [dw-1:0] doq; // output data bus`
153
154			`//`
155			`// Internal wires and registers`
156			`//`
157			`wire [10:0] unconnected;`
158
159			`ifdef OR1200_ARTISAN_SSP
160			`else
161			`ifdef OR1200_VIRTUALSILICON_SSP
162			`else
163			`ifdef OR1200_BIST
164			`assign mbist_so_o = mbist_si_i;`
165			`endif
166			`endif
167			`endif
168
169			`ifdef OR1200_ARTISAN_SSP
170
171			`//`
172			`// Instantiation of ASIC memory:`
173			`//`
174			`// Artisan Synchronous Single-Port RAM (ra1sh)`
175			`//`
176			`ifdef UNUSED
177			`art_hssp_256x21 #(dw, 1<<aw, aw) artisan_ssp(`
178			`else
179			`ifdef OR1200_BIST
180			`art_hssp_256x21_bist artisan_ssp(`
181			`else
182			`art_hssp_256x21 artisan_ssp(`
183			`endif
184			`endif
185			`ifdef OR1200_BIST
186			`// RAM BIST`
187			`.mbist_si_i(mbist_si_i),`
188			`.mbist_so_o(mbist_so_o),`
189			`.mbist_ctrl_i(mbist_ctrl_i),`
190			`endif
191			`.CLK(clk),`
192			`.CEN(~ce),`
193			`.WEN(~we),`
194			`.A(addr),`
195			`.D(di),`
196			`.OEN(~oe),`
197			`.Q(doq)`
198			`);`
199
200			`else
201
202			`ifdef OR1200_AVANT_ATP
203
204			`//`
205			`// Instantiation of ASIC memory:`
206			`//`
207			`// Avant! Asynchronous Two-Port RAM`
208			`//`
209			`avant_atp avant_atp(`
210			`.web(~we),`
211			`.reb(),`
212			`.oeb(~oe),`
213			`.rcsb(),`
214			`.wcsb(),`
215			`.ra(addr),`
216			`.wa(addr),`
217			`.di(di),`
218			`.doq(doq)`
219			`);`
220
221			`else
222
223			`ifdef OR1200_VIRAGE_SSP
224
225			`//`
226			`// Instantiation of ASIC memory:`
227			`//`
228			`// Virage Synchronous 1-port R/W RAM`
229			`//`
230			`virage_ssp virage_ssp(`
231			`.clk(clk),`
232			`.adr(addr),`
233			`.d(di),`
234			`.we(we),`
235			`.oe(oe),`
236			`.me(ce),`
237			`.q(doq)`
238			`);`
239
240			`else
241
242			`ifdef OR1200_VIRTUALSILICON_SSP
243
244			`//`
245			`// Instantiation of ASIC memory:`
246			`//`
247			`// Virtual Silicon Single-Port Synchronous SRAM`
248			`//`
249			`ifdef UNUSED
250			`vs_hdsp_256x21 #(1<<aw, aw-1, dw-1) vs_ssp(`
251			`else
252			`ifdef OR1200_BIST
253			`vs_hdsp_256x21_bist vs_ssp(`
254			`else
255			`vs_hdsp_256x21 vs_ssp(`
256			`endif
257			`endif
258			`ifdef OR1200_BIST
259			`// RAM BIST`
260			`.mbist_si_i(mbist_si_i),`
261			`.mbist_so_o(mbist_so_o),`
262			`.mbist_ctrl_i(mbist_ctrl_i),`
263			`endif
264			`.CK(clk),`
265			`.ADR(addr),`
266			`.DI(di),`
267			`.WEN(~we),`
268			`.CEN(~ce),`
269			`.OEN(~oe),`
270			`.DOUT(doq)`
271			`);`
272
273			`else
274
275			`ifdef OR1200_XILINX_RAMB4
276
277			`//`
278			`// Instantiation of FPGA memory:`
279			`//`
280			`// Virtex/Spartan2`
281			`//`
282
283			`//`
284			`// Block 0`
285			`//`
286			`RAMB4_S16 ramb4_s16_0(`
287			`.CLK(clk),`
288			`.RST(rst),`
289			`.ADDR(addr),`
290			`.DI(di[15:0]),`
291			`.EN(ce),`
292			`.WE(we),`
293			`.DO(doq[15:0])`
294			`);`
295
296			`//`
297			`// Block 1`
298			`//`
299			`RAMB4_S16 ramb4_s16_1(`
300			`.CLK(clk),`
301			`.RST(rst),`
302			`.ADDR(addr),`
303			`.DI({11'b00000000000, di[20:16]}),`
304			`.EN(ce),`
305			`.WE(we),`
306			`.DO({unconnected, doq[20:16]})`
307			`);`
308
309			`else
310
311			`ifdef OR1200_ALTERA_LPM
312
313			`//`
314			`// Instantiation of FPGA memory:`
315			`//`
316			`// Altera LPM`
317			`//`
318			`// Added By Jamil Khatib`
319			`//`
320
321			`wire wr;`
322
323			`assign wr = ce & we;`
324
325			`initial $display("Using Altera LPM.");`
326
327			`lpm_ram_dq lpm_ram_dq_component (`
328			`.address(addr),`
329			`.inclock(clk),`
330			`.outclock(clk),`
331			`.data(di),`
332			`.we(wr),`
333			`.q(doq)`
334			`);`
335
336			`defparam lpm_ram_dq_component.lpm_width = dw,`
337			`lpm_ram_dq_component.lpm_widthad = aw,`
338			`lpm_ram_dq_component.lpm_indata = "REGISTERED",`
339			`lpm_ram_dq_component.lpm_address_control = "REGISTERED",`
340			`lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",`
341			`lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";`
342			`// examplar attribute lpm_ram_dq_component NOOPT TRUE`
343
344			`else
345
346			`//`
347			`// Generic single-port synchronous RAM model`
348			`//`
349
350			`//`
351			`// Generic RAM's registers and wires`
352			`//`
353			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
354			`reg [aw-1:0] addr_reg; // RAM address register`
355
356			`//`
357			`// Data output drivers`
358			`//`
359			`assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};`
360
361			`//`
362			`// RAM adress register`
363			`//`
364			`always @(posedge clk or posedge rst)`
365			`if (rst)`
366			`addr_reg <= #1 {aw{1'b0}};`
367			`else if (ce)`
368			`addr_reg <= #1 addr;`
369
370			`//`
371			`// RAM write`
372			`//`
373			`always @(posedge clk)`
374			`if (ce && we)`
375			`mem[addr] <= #1 di;`
376
377			`endif // !OR1200_ALTERA_LPM
378			`endif // !OR1200_XILINX_RAMB4_S16
379			`endif // !OR1200_VIRTUALSILICON_SSP
380			`endif // !OR1200_VIRAGE_SSP
381			`endif // !OR1200_AVANT_ATP
382			`endif // !OR1200_ARTISAN_SSP
383
384			`endmodule`