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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Single-Port Synchronous RAM                         ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common single-port             ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  single-port synchronous RAM.                                ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Single-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage Single-Port Sync RAM                               ////
////  - Virtual Silicon Single-Port Sync RAM                      ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16                                   ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - xilinx rams need external tri-state logic                ////
////   - fix avant! two-port ram                                  ////
////   - add additional RAMs                                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.8  2004/06/08 18:15:32  lampret
// Changed behavior of the simulation generic models
//
// Revision 1.7  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.3.4.1  2003/12/09 11:46:48  simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.3  2003/04/07 01:19:07  lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.2  2002/10/17 20:04:40  lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.10  2001/11/27 21:24:04  lampret
// Changed instantiation name of VS RAMs.
//
// Revision 1.9  2001/11/27 19:45:04  lampret
// Fixed VS RAM instantiation - again.
//
// Revision 1.8  2001/11/23 21:42:31  simons
// Program counter divided to PPC and NPC.
//
// Revision 1.6  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.5  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_spram_512x20(
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
        // Generic synchronous single-port RAM interface
        clk, rst, ce, we, oe, addr, di, doq
);
 
//
// Default address and data buses width
//
parameter aw = 9;
parameter dw = 20;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// Generic synchronous single-port RAM interface
//
input                   clk;    // Clock
input                   rst;    // Reset
input                   ce;     // Chip enable input
input                   we;     // Write enable input
input                   oe;     // Output enable input
input   [aw-1:0] addr;   // address bus inputs
input   [dw-1:0] di;     // input data bus
output  [dw-1:0] doq;    // output data bus
 
//
// Internal wires and registers
//
wire    [3:0]            unconnected;
 
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
 
`ifdef OR1200_ARTISAN_SSP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_512x20_bist artisan_ssp(
`else
art_hssp_512x20 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CLK(clk),
        .CEN(~ce),
        .WEN(~we),
        .A(addr),
        .D(di),
        .OEN(~oe),
        .Q(doq)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .doq(doq)
);
 
`else
 
`ifdef OR1200_VIRAGE_SSP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
        .clk(clk),
        .adr(addr),
        .d(di),
        .we(we),
        .oe(oe),
        .me(ce),
        .q(doq)
);
 
`else
 
`ifdef OR1200_VIRTUALSILICON_SSP
 
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_512x20 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_512x20_bist vs_ssp(
`else
vs_hdsp_512x20 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
        .CK(clk),
        .ADR(addr),
        .DI(di),
        .WEN(~we),
        .CEN(~ce),
        .OEN(~oe),
        .DOUT(doq)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S8 ramb4_s8_0(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[7:0]),
        .EN(ce),
        .WE(we),
        .DO(doq[7:0])
);
 
//
// Block 1
//
RAMB4_S8 ramb4_s8_1(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI(di[15:8]),
        .EN(ce),
        .WE(we),
        .DO(doq[15:8])
);
 
//
// Block 2
//
RAMB4_S8 ramb4_s8_2(
        .CLK(clk),
        .RST(rst),
        .ADDR(addr),
        .DI({4'b0000, di[19:16]}),
        .EN(ce),
        .WE(we),
        .DO({unconnected, doq[19:16]})
);
 
`else
 
`ifdef OR1200_ALTERA_LPM
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
 
wire    wr;
 
assign  wr = ce & we;
 
initial $display("Using Altera LPM.");
 
lpm_ram_dq lpm_ram_dq_component (
        .address(addr),
        .inclock(clk),
        .outclock(clk),
        .data(di),
        .we(wr),
        .q(doq)
);
 
defparam lpm_ram_dq_component.lpm_width = dw,
        lpm_ram_dq_component.lpm_widthad = aw,
        lpm_ram_dq_component.lpm_indata = "REGISTERED",
        lpm_ram_dq_component.lpm_address_control = "REGISTERED",
        lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
        lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
        // examplar attribute lpm_ram_dq_component NOOPT TRUE
 
`else
 
//
// Generic single-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [aw-1:0] addr_reg;               // RAM address register
 
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
 
//
// RAM address register
//
always @(posedge clk or posedge rst)
        if (rst)
                addr_reg <= #1 {aw{1'b0}};
        else if (ce)
                addr_reg <= #1 addr;
 
//
// RAM write
//
always @(posedge clk)
        if (ce && we)
                mem[addr] <= #1 di;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB4_S16
`endif  // !OR1200_VIRTUALSILICON_SSP
`endif  // !OR1200_VIRAGE_SSP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SSP
 
endmodule

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[/] [or1k/] [trunk/] [rc203soc/] [rtl/] [verilog/] [or1200/] [rtl/] [verilog/] [or1200_spram_512x20.v] - Blame information for rev 1780

Line No.	Rev	Author	Line
1	1327	jcastillo	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Single-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common single-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// single-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Single-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage Single-Port Sync RAM ////`
22			`//// - Virtual Silicon Single-Port Sync RAM ////`
23			`//// ////`
24			`//// Supported FPGA RAMs are: ////`
25			`//// - Xilinx Virtex RAMB4_S16 ////`
26			`//// - Altera LPM ////`
27			`//// ////`
28			`//// To Do: ////`
29			`//// - xilinx rams need external tri-state logic ////`
30			`//// - fix avant! two-port ram ////`
31			`//// - add additional RAMs ////`
32			`//// ////`
33			`//// Author(s): ////`
34			`//// - Damjan Lampret, lampret@opencores.org ////`
35			`//// ////`
36			`//////////////////////////////////////////////////////////////////////`
37			`//// ////`
38			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
39			`//// ////`
40			`//// This source file may be used and distributed without ////`
41			`//// restriction provided that this copyright statement is not ////`
42			`//// removed from the file and that any derivative work contains ////`
43			`//// the original copyright notice and the associated disclaimer. ////`
44			`//// ////`
45			`//// This source file is free software; you can redistribute it ////`
46			`//// and/or modify it under the terms of the GNU Lesser General ////`
47			`//// Public License as published by the Free Software Foundation; ////`
48			`//// either version 2.1 of the License, or (at your option) any ////`
49			`//// later version. ////`
50			`//// ////`
51			`//// This source is distributed in the hope that it will be ////`
52			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
53			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
54			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
55			`//// details. ////`
56			`//// ////`
57			`//// You should have received a copy of the GNU Lesser General ////`
58			`//// Public License along with this source; if not, download it ////`
59			`//// from http://www.opencores.org/lgpl.shtml ////`
60			`//// ////`
61			`//////////////////////////////////////////////////////////////////////`
62			`//`
63			`// CVS Revision History`
64			`//`
65			`// $Log: not supported by cvs2svn $`
66			`// Revision 1.8 2004/06/08 18:15:32 lampret`
67			`// Changed behavior of the simulation generic models`
68			`//`
69			`// Revision 1.7 2004/04/05 08:29:57 lampret`
70			`// Merged branch_qmem into main tree.`
71			`//`
72			`// Revision 1.3.4.1 2003/12/09 11:46:48 simons`
73			`// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.`
74			`//`
75			`// Revision 1.3 2003/04/07 01:19:07 lampret`
76			`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
77			`//`
78			`// Revision 1.2 2002/10/17 20:04:40 lampret`
79			`// Added BIST scan. Special VS RAMs need to be used to implement BIST.`
80			`//`
81			`// Revision 1.1 2002/01/03 08:16:15 lampret`
82			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
83			`//`
84			`// Revision 1.10 2001/11/27 21:24:04 lampret`
85			`// Changed instantiation name of VS RAMs.`
86			`//`
87			`// Revision 1.9 2001/11/27 19:45:04 lampret`
88			`// Fixed VS RAM instantiation - again.`
89			`//`
90			`// Revision 1.8 2001/11/23 21:42:31 simons`
91			`// Program counter divided to PPC and NPC.`
92			`//`
93			`// Revision 1.6 2001/10/21 17:57:16 lampret`
94			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
95			`//`
96			`// Revision 1.5 2001/10/14 13:12:09 lampret`
97			`// MP3 version.`
98			`//`
99			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
100			`// no message`
101			`//`
102			`// Revision 1.1 2001/08/09 13:39:33 lampret`
103			`// Major clean-up.`
104			`//`
105			`// Revision 1.2 2001/07/30 05:38:02 lampret`
106			`// Adding empty directories required by HDL coding guidelines`
107			`//`
108			`//`
109
110			`// synopsys translate_off`
111			`include "timescale.v"
112			`// synopsys translate_on`
113			`include "or1200_defines.v"
114
115			`module or1200_spram_512x20(`
116			`ifdef OR1200_BIST
117			`// RAM BIST`
118			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
119			`endif
120			`// Generic synchronous single-port RAM interface`
121			`clk, rst, ce, we, oe, addr, di, doq`
122			`);`
123
124			`//`
125			`// Default address and data buses width`
126			`//`
127			`parameter aw = 9;`
128			`parameter dw = 20;`
129
130			`ifdef OR1200_BIST
131			`//`
132			`// RAM BIST`
133			`//`
134			`input mbist_si_i;`
135			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
136			`output mbist_so_o;`
137			`endif
138
139			`//`
140			`// Generic synchronous single-port RAM interface`
141			`//`
142			`input clk; // Clock`
143			`input rst; // Reset`
144			`input ce; // Chip enable input`
145			`input we; // Write enable input`
146			`input oe; // Output enable input`
147			`input [aw-1:0] addr; // address bus inputs`
148			`input [dw-1:0] di; // input data bus`
149			`output [dw-1:0] doq; // output data bus`
150
151			`//`
152			`// Internal wires and registers`
153			`//`
154			`wire [3:0] unconnected;`
155
156			`ifdef OR1200_ARTISAN_SSP
157			`else
158			`ifdef OR1200_VIRTUALSILICON_SSP
159			`else
160			`ifdef OR1200_BIST
161			`assign mbist_so_o = mbist_si_i;`
162			`endif
163			`endif
164			`endif
165
166			`ifdef OR1200_ARTISAN_SSP
167
168			`//`
169			`// Instantiation of ASIC memory:`
170			`//`
171			`// Artisan Synchronous Single-Port RAM (ra1sh)`
172			`//`
173			`ifdef UNUSED
174			`art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(`
175			`else
176			`ifdef OR1200_BIST
177			`art_hssp_512x20_bist artisan_ssp(`
178			`else
179			`art_hssp_512x20 artisan_ssp(`
180			`endif
181			`endif
182			`ifdef OR1200_BIST
183			`// RAM BIST`
184			`.mbist_si_i(mbist_si_i),`
185			`.mbist_so_o(mbist_so_o),`
186			`.mbist_ctrl_i(mbist_ctrl_i),`
187			`endif
188			`.CLK(clk),`
189			`.CEN(~ce),`
190			`.WEN(~we),`
191			`.A(addr),`
192			`.D(di),`
193			`.OEN(~oe),`
194			`.Q(doq)`
195			`);`
196
197			`else
198
199			`ifdef OR1200_AVANT_ATP
200
201			`//`
202			`// Instantiation of ASIC memory:`
203			`//`
204			`// Avant! Asynchronous Two-Port RAM`
205			`//`
206			`avant_atp avant_atp(`
207			`.web(~we),`
208			`.reb(),`
209			`.oeb(~oe),`
210			`.rcsb(),`
211			`.wcsb(),`
212			`.ra(addr),`
213			`.wa(addr),`
214			`.di(di),`
215			`.doq(doq)`
216			`);`
217
218			`else
219
220			`ifdef OR1200_VIRAGE_SSP
221
222			`//`
223			`// Instantiation of ASIC memory:`
224			`//`
225			`// Virage Synchronous 1-port R/W RAM`
226			`//`
227			`virage_ssp virage_ssp(`
228			`.clk(clk),`
229			`.adr(addr),`
230			`.d(di),`
231			`.we(we),`
232			`.oe(oe),`
233			`.me(ce),`
234			`.q(doq)`
235			`);`
236
237			`else
238
239			`ifdef OR1200_VIRTUALSILICON_SSP
240
241			`//`
242			`// Instantiation of ASIC memory:`
243			`//`
244			`// Virtual Silicon Single-Port Synchronous SRAM`
245			`//`
246			`ifdef UNUSED
247			`vs_hdsp_512x20 #(1<<aw, aw-1, dw-1) vs_ssp(`
248			`else
249			`ifdef OR1200_BIST
250			`vs_hdsp_512x20_bist vs_ssp(`
251			`else
252			`vs_hdsp_512x20 vs_ssp(`
253			`endif
254			`endif
255			`ifdef OR1200_BIST
256			`// RAM BIST`
257			`.mbist_si_i(mbist_si_i),`
258			`.mbist_so_o(mbist_so_o),`
259			`.mbist_ctrl_i(mbist_ctrl_i),`
260			`endif
261			`.CK(clk),`
262			`.ADR(addr),`
263			`.DI(di),`
264			`.WEN(~we),`
265			`.CEN(~ce),`
266			`.OEN(~oe),`
267			`.DOUT(doq)`
268			`);`
269
270			`else
271
272			`ifdef OR1200_XILINX_RAMB4
273
274			`//`
275			`// Instantiation of FPGA memory:`
276			`//`
277			`// Virtex/Spartan2`
278			`//`
279
280			`//`
281			`// Block 0`
282			`//`
283			`RAMB4_S8 ramb4_s8_0(`
284			`.CLK(clk),`
285			`.RST(rst),`
286			`.ADDR(addr),`
287			`.DI(di[7:0]),`
288			`.EN(ce),`
289			`.WE(we),`
290			`.DO(doq[7:0])`
291			`);`
292
293			`//`
294			`// Block 1`
295			`//`
296			`RAMB4_S8 ramb4_s8_1(`
297			`.CLK(clk),`
298			`.RST(rst),`
299			`.ADDR(addr),`
300			`.DI(di[15:8]),`
301			`.EN(ce),`
302			`.WE(we),`
303			`.DO(doq[15:8])`
304			`);`
305
306			`//`
307			`// Block 2`
308			`//`
309			`RAMB4_S8 ramb4_s8_2(`
310			`.CLK(clk),`
311			`.RST(rst),`
312			`.ADDR(addr),`
313			`.DI({4'b0000, di[19:16]}),`
314			`.EN(ce),`
315			`.WE(we),`
316			`.DO({unconnected, doq[19:16]})`
317			`);`
318
319			`else
320
321			`ifdef OR1200_ALTERA_LPM
322
323			`//`
324			`// Instantiation of FPGA memory:`
325			`//`
326			`// Altera LPM`
327			`//`
328			`// Added By Jamil Khatib`
329			`//`
330
331			`wire wr;`
332
333			`assign wr = ce & we;`
334
335			`initial $display("Using Altera LPM.");`
336
337			`lpm_ram_dq lpm_ram_dq_component (`
338			`.address(addr),`
339			`.inclock(clk),`
340			`.outclock(clk),`
341			`.data(di),`
342			`.we(wr),`
343			`.q(doq)`
344			`);`
345
346			`defparam lpm_ram_dq_component.lpm_width = dw,`
347			`lpm_ram_dq_component.lpm_widthad = aw,`
348			`lpm_ram_dq_component.lpm_indata = "REGISTERED",`
349			`lpm_ram_dq_component.lpm_address_control = "REGISTERED",`
350			`lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",`
351			`lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";`
352			`// examplar attribute lpm_ram_dq_component NOOPT TRUE`
353
354			`else
355
356			`//`
357			`// Generic single-port synchronous RAM model`
358			`//`
359
360			`//`
361			`// Generic RAM's registers and wires`
362			`//`
363			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
364			`reg [aw-1:0] addr_reg; // RAM address register`
365
366			`//`
367			`// Data output drivers`
368			`//`
369			`assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};`
370
371			`//`
372			`// RAM address register`
373			`//`
374			`always @(posedge clk or posedge rst)`
375			`if (rst)`
376			`addr_reg <= #1 {aw{1'b0}};`
377			`else if (ce)`
378			`addr_reg <= #1 addr;`
379
380			`//`
381			`// RAM write`
382			`//`
383			`always @(posedge clk)`
384			`if (ce && we)`
385			`mem[addr] <= #1 di;`
386
387			`endif // !OR1200_ALTERA_LPM
388			`endif // !OR1200_XILINX_RAMB4_S16
389			`endif // !OR1200_VIRTUALSILICON_SSP
390			`endif // !OR1200_VIRAGE_SSP
391			`endif // !OR1200_AVANT_ATP
392			`endif // !OR1200_ARTISAN_SSP
393
394			`endmodule`