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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  Generic Two-Port Synchronous RAM                            ////
////                                                              ////
////  This file is part of memory library available from          ////
////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
////                                                              ////
////  Description                                                 ////
////  This block is a wrapper with common two-port                ////
////  synchronous memory interface for different                  ////
////  types of ASIC and FPGA RAMs. Beside universal memory        ////
////  interface it also provides behavioral model of generic      ////
////  two-port synchronous RAM.                                   ////
////  It should be used in all OPENCORES designs that want to be  ////
////  portable accross different target technologies and          ////
////  independent of target memory.                               ////
////                                                              ////
////  Supported ASIC RAMs are:                                    ////
////  - Artisan Double-Port Sync RAM                              ////
////  - Avant! Two-Port Sync RAM (*)                              ////
////  - Virage 2-port Sync RAM                                    ////
////                                                              ////
////  Supported FPGA RAMs are:                                    ////
////  - Xilinx Virtex RAMB4_S16_S16                               ////
////  - Altera LPM                                                ////
////                                                              ////
////  To Do:                                                      ////
////   - fix Avant!                                               ////
////   - xilinx rams need external tri-state logic                ////
////   - add additional RAMs (VS etc)                             ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.4  2004/06/08 18:15:48  lampret
// Changed behavior of the simulation generic models
//
// Revision 1.3  2004/04/05 08:29:57  lampret
// Merged branch_qmem into main tree.
//
// Revision 1.2.4.1  2003/07/08 15:36:37  lampret
// Added embedded memory QMEM.
//
// Revision 1.2  2003/04/07 01:19:07  lampret
// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
//
// Revision 1.1  2002/01/03 08:16:15  lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.7  2001/10/21 17:57:16  lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.6  2001/10/14 13:12:09  lampret
// MP3 version.
//
// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
// no message
//
// Revision 1.1  2001/08/09 13:39:33  lampret
// Major clean-up.
//
// Revision 1.2  2001/07/30 05:38:02  lampret
// Adding empty directories required by HDL coding guidelines
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_tpram_32x32(
        // Generic synchronous two-port RAM interface
        clk_a, rst_a, ce_a, we_a, oe_a, addr_a, di_a, do_a,
        clk_b, rst_b, ce_b, we_b, oe_b, addr_b, di_b, do_b
);
 
//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 32;
 
//
// Generic synchronous two-port RAM interface
//
input                   clk_a;  // Clock
input                   rst_a;  // Reset
input                   ce_a;   // Chip enable input
input                   we_a;   // Write enable input
input                   oe_a;   // Output enable input
input   [aw-1:0] addr_a; // address bus inputs
input   [dw-1:0] di_a;   // input data bus
output  [dw-1:0] do_a;   // output data bus
input                   clk_b;  // Clock
input                   rst_b;  // Reset
input                   ce_b;   // Chip enable input
input                   we_b;   // Write enable input
input                   oe_b;   // Output enable input
input   [aw-1:0] addr_b; // address bus inputs
input   [dw-1:0] di_b;   // input data bus
output  [dw-1:0] do_b;   // output data bus
 
//
// Internal wires and registers
//
 
 
`ifdef OR1200_ARTISAN_SDP
 
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Double-Port RAM (ra2sh)
//
`ifdef UNUSED
art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(
`else
art_hsdp_32x32 artisan_sdp(
`endif
        .qa(do_a),
        .clka(clk_a),
        .cena(~ce_a),
        .wena(~we_a),
        .aa(addr_a),
        .da(di_a),
        .oena(~oe_a),
        .qb(do_b),
        .clkb(clk_b),
        .cenb(~ce_b),
        .wenb(~we_b),
        .ab(addr_b),
        .db(di_b),
        .oenb(~oe_b)
);
 
`else
 
`ifdef OR1200_AVANT_ATP
 
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
        .web(~we),
        .reb(),
        .oeb(~oe),
        .rcsb(),
        .wcsb(),
        .ra(addr),
        .wa(addr),
        .di(di),
        .doq(doq)
);
 
`else
 
`ifdef OR1200_VIRAGE_STP
 
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 2-port R/W RAM
//
virage_stp virage_stp(
        .QA(do_a),
        .QB(do_b),
 
        .ADRA(addr_a),
        .DA(di_a),
        .WEA(we_a),
        .OEA(oe_a),
        .MEA(ce_a),
        .CLKA(clk_a),
 
        .ADRB(adr_b),
        .DB(di_b),
        .WEB(we_b),
        .OEB(oe_b),
        .MEB(ce_b),
        .CLKB(clk_b)
);
 
`else
 
`ifdef OR1200_XILINX_RAMB4
 
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
 
//
// Block 0
//
RAMB4_S16_S16 ramb4_s16_s16_0(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA(addr_a),
        .DIA(di_a[15:0]),
        .ENA(ce_a),
        .WEA(we_a),
        .DOA(do_a[15:0]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB(addr_b),
        .DIB(di_b[15:0]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB(do_b[15:0])
);
 
//
// Block 1
//
RAMB4_S16_S16 ramb4_s16_s16_1(
        .CLKA(clk_a),
        .RSTA(rst_a),
        .ADDRA(addr_a),
        .DIA(di_a[31:16]),
        .ENA(ce_a),
        .WEA(we_a),
        .DOA(do_a[31:16]),
 
        .CLKB(clk_b),
        .RSTB(rst_b),
        .ADDRB(addr_b),
        .DIB(di_b[31:16]),
        .ENB(ce_b),
        .WEB(we_b),
        .DOB(do_b[31:16])
);
 
`else
 
`ifdef OR1200_ALTERA_LPM_XXX
 
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
altqpram altqpram_component (
        .wraddress_a (addr_a),
        .inclocken_a (ce_a),
        .wraddress_b (addr_b),
        .wren_a (we_a),
        .inclocken_b (ce_b),
        .wren_b (we_b),
        .inaclr_a (rst_a),
        .inaclr_b (rst_b),
        .inclock_a (clk_a),
        .inclock_b (clk_b),
        .data_a (di_a),
        .data_b (di_b),
        .q_a (do_a),
        .q_b (do_b)
);
 
defparam altqpram_component.operation_mode = "BIDIR_DUAL_PORT",
        altqpram_component.width_write_a = dw,
        altqpram_component.widthad_write_a = aw,
        altqpram_component.numwords_write_a = dw,
        altqpram_component.width_read_a = dw,
        altqpram_component.widthad_read_a = aw,
        altqpram_component.numwords_read_a = dw,
        altqpram_component.width_write_b = dw,
        altqpram_component.widthad_write_b = aw,
        altqpram_component.numwords_write_b = dw,
        altqpram_component.width_read_b = dw,
        altqpram_component.widthad_read_b = aw,
        altqpram_component.numwords_read_b = dw,
        altqpram_component.indata_reg_a = "INCLOCK_A",
        altqpram_component.wrcontrol_wraddress_reg_a = "INCLOCK_A",
        altqpram_component.outdata_reg_a = "INCLOCK_A",
        altqpram_component.indata_reg_b = "INCLOCK_B",
        altqpram_component.wrcontrol_wraddress_reg_b = "INCLOCK_B",
        altqpram_component.outdata_reg_b = "INCLOCK_B",
        altqpram_component.indata_aclr_a = "INACLR_A",
        altqpram_component.wraddress_aclr_a = "INACLR_A",
        altqpram_component.wrcontrol_aclr_a = "INACLR_A",
        altqpram_component.outdata_aclr_a = "INACLR_A",
        altqpram_component.indata_aclr_b = "NONE",
        altqpram_component.wraddress_aclr_b = "NONE",
        altqpram_component.wrcontrol_aclr_b = "NONE",
        altqpram_component.outdata_aclr_b = "INACLR_B",
        altqpram_component.lpm_hint = "USE_ESB=ON";
        //examplar attribute altqpram_component NOOPT TRUE
 
`else
 
//
// Generic two-port synchronous RAM model
//
 
//
// Generic RAM's registers and wires
//
reg     [dw-1:0] mem [(1<<aw)-1:0];       // RAM content
reg     [aw-1:0] addr_a_reg;             // RAM read address register
reg     [aw-1:0] addr_b_reg;             // RAM read address register
 
//
// Data output drivers
//
assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};
assign do_b = (oe_b) ? mem[addr_b_reg] : {dw{1'b0}};
 
//
// RAM write
//
always @(posedge clk_a)
        if (ce_a && we_a)
                mem[addr_a] <= #1 di_a;
 
//
// RAM write
//
always @(posedge clk_b)
        if (ce_b && we_b)
                mem[addr_b] <= #1 di_b;
 
//
// RAM read address register
//
always @(posedge clk_a or posedge rst_a)
        if (rst_a)
                addr_a_reg <= #1 {aw{1'b0}};
        else if (ce_a)
                addr_a_reg <= #1 addr_a;
 
//
// RAM read address register
//
always @(posedge clk_b or posedge rst_b)
        if (rst_b)
                addr_b_reg <= #1 {aw{1'b0}};
        else if (ce_b)
                addr_b_reg <= #1 addr_b;
 
`endif  // !OR1200_ALTERA_LPM
`endif  // !OR1200_XILINX_RAMB4_S16_S16
`endif  // !OR1200_VIRAGE_STP
`endif  // !OR1200_AVANT_ATP
`endif  // !OR1200_ARTISAN_SDP
 
endmodule

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[/] [or1k/] [trunk/] [rc203soc/] [rtl/] [verilog/] [or1200/] [rtl/] [verilog/] [or1200_tpram_32x32.v] - Blame information for rev 1327

Line No.	Rev	Author	Line
1	1327	jcastillo	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// Generic Two-Port Synchronous RAM ////`
4			`//// ////`
5			`//// This file is part of memory library available from ////`
6			`//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// This block is a wrapper with common two-port ////`
10			`//// synchronous memory interface for different ////`
11			`//// types of ASIC and FPGA RAMs. Beside universal memory ////`
12			`//// interface it also provides behavioral model of generic ////`
13			`//// two-port synchronous RAM. ////`
14			`//// It should be used in all OPENCORES designs that want to be ////`
15			`//// portable accross different target technologies and ////`
16			`//// independent of target memory. ////`
17			`//// ////`
18			`//// Supported ASIC RAMs are: ////`
19			`//// - Artisan Double-Port Sync RAM ////`
20			`//// - Avant! Two-Port Sync RAM (*) ////`
21			`//// - Virage 2-port Sync RAM ////`
22			`//// ////`
23			`//// Supported FPGA RAMs are: ////`
24			`//// - Xilinx Virtex RAMB4_S16_S16 ////`
25			`//// - Altera LPM ////`
26			`//// ////`
27			`//// To Do: ////`
28			`//// - fix Avant! ////`
29			`//// - xilinx rams need external tri-state logic ////`
30			`//// - add additional RAMs (VS etc) ////`
31			`//// ////`
32			`//// Author(s): ////`
33			`//// - Damjan Lampret, lampret@opencores.org ////`
34			`//// ////`
35			`//////////////////////////////////////////////////////////////////////`
36			`//// ////`
37			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
38			`//// ////`
39			`//// This source file may be used and distributed without ////`
40			`//// restriction provided that this copyright statement is not ////`
41			`//// removed from the file and that any derivative work contains ////`
42			`//// the original copyright notice and the associated disclaimer. ////`
43			`//// ////`
44			`//// This source file is free software; you can redistribute it ////`
45			`//// and/or modify it under the terms of the GNU Lesser General ////`
46			`//// Public License as published by the Free Software Foundation; ////`
47			`//// either version 2.1 of the License, or (at your option) any ////`
48			`//// later version. ////`
49			`//// ////`
50			`//// This source is distributed in the hope that it will be ////`
51			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
52			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
53			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
54			`//// details. ////`
55			`//// ////`
56			`//// You should have received a copy of the GNU Lesser General ////`
57			`//// Public License along with this source; if not, download it ////`
58			`//// from http://www.opencores.org/lgpl.shtml ////`
59			`//// ////`
60			`//////////////////////////////////////////////////////////////////////`
61			`//`
62			`// CVS Revision History`
63			`//`
64			`// $Log: not supported by cvs2svn $`
65			`// Revision 1.4 2004/06/08 18:15:48 lampret`
66			`// Changed behavior of the simulation generic models`
67			`//`
68			`// Revision 1.3 2004/04/05 08:29:57 lampret`
69			`// Merged branch_qmem into main tree.`
70			`//`
71			`// Revision 1.2.4.1 2003/07/08 15:36:37 lampret`
72			`// Added embedded memory QMEM.`
73			`//`
74			`// Revision 1.2 2003/04/07 01:19:07 lampret`
75			`// Added Altera LPM RAMs. Changed generic RAM output when OE inactive.`
76			`//`
77			`// Revision 1.1 2002/01/03 08:16:15 lampret`
78			`// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.`
79			`//`
80			`// Revision 1.7 2001/10/21 17:57:16 lampret`
81			`// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.`
82			`//`
83			`// Revision 1.6 2001/10/14 13:12:09 lampret`
84			`// MP3 version.`
85			`//`
86			`// Revision 1.1.1.1 2001/10/06 10:18:36 igorm`
87			`// no message`
88			`//`
89			`// Revision 1.1 2001/08/09 13:39:33 lampret`
90			`// Major clean-up.`
91			`//`
92			`// Revision 1.2 2001/07/30 05:38:02 lampret`
93			`// Adding empty directories required by HDL coding guidelines`
94			`//`
95			`//`
96
97			`// synopsys translate_off`
98			`include "timescale.v"
99			`// synopsys translate_on`
100			`include "or1200_defines.v"
101
102			`module or1200_tpram_32x32(`
103			`// Generic synchronous two-port RAM interface`
104			`clk_a, rst_a, ce_a, we_a, oe_a, addr_a, di_a, do_a,`
105			`clk_b, rst_b, ce_b, we_b, oe_b, addr_b, di_b, do_b`
106			`);`
107
108			`//`
109			`// Default address and data buses width`
110			`//`
111			`parameter aw = 5;`
112			`parameter dw = 32;`
113
114			`//`
115			`// Generic synchronous two-port RAM interface`
116			`//`
117			`input clk_a; // Clock`
118			`input rst_a; // Reset`
119			`input ce_a; // Chip enable input`
120			`input we_a; // Write enable input`
121			`input oe_a; // Output enable input`
122			`input [aw-1:0] addr_a; // address bus inputs`
123			`input [dw-1:0] di_a; // input data bus`
124			`output [dw-1:0] do_a; // output data bus`
125			`input clk_b; // Clock`
126			`input rst_b; // Reset`
127			`input ce_b; // Chip enable input`
128			`input we_b; // Write enable input`
129			`input oe_b; // Output enable input`
130			`input [aw-1:0] addr_b; // address bus inputs`
131			`input [dw-1:0] di_b; // input data bus`
132			`output [dw-1:0] do_b; // output data bus`
133
134			`//`
135			`// Internal wires and registers`
136			`//`
137
138
139			`ifdef OR1200_ARTISAN_SDP
140
141			`//`
142			`// Instantiation of ASIC memory:`
143			`//`
144			`// Artisan Synchronous Double-Port RAM (ra2sh)`
145			`//`
146			`ifdef UNUSED
147			`art_hsdp_32x32 #(dw, 1<<aw, aw) artisan_sdp(`
148			`else
149			`art_hsdp_32x32 artisan_sdp(`
150			`endif
151			`.qa(do_a),`
152			`.clka(clk_a),`
153			`.cena(~ce_a),`
154			`.wena(~we_a),`
155			`.aa(addr_a),`
156			`.da(di_a),`
157			`.oena(~oe_a),`
158			`.qb(do_b),`
159			`.clkb(clk_b),`
160			`.cenb(~ce_b),`
161			`.wenb(~we_b),`
162			`.ab(addr_b),`
163			`.db(di_b),`
164			`.oenb(~oe_b)`
165			`);`
166
167			`else
168
169			`ifdef OR1200_AVANT_ATP
170
171			`//`
172			`// Instantiation of ASIC memory:`
173			`//`
174			`// Avant! Asynchronous Two-Port RAM`
175			`//`
176			`avant_atp avant_atp(`
177			`.web(~we),`
178			`.reb(),`
179			`.oeb(~oe),`
180			`.rcsb(),`
181			`.wcsb(),`
182			`.ra(addr),`
183			`.wa(addr),`
184			`.di(di),`
185			`.doq(doq)`
186			`);`
187
188			`else
189
190			`ifdef OR1200_VIRAGE_STP
191
192			`//`
193			`// Instantiation of ASIC memory:`
194			`//`
195			`// Virage Synchronous 2-port R/W RAM`
196			`//`
197			`virage_stp virage_stp(`
198			`.QA(do_a),`
199			`.QB(do_b),`
200
201			`.ADRA(addr_a),`
202			`.DA(di_a),`
203			`.WEA(we_a),`
204			`.OEA(oe_a),`
205			`.MEA(ce_a),`
206			`.CLKA(clk_a),`
207
208			`.ADRB(adr_b),`
209			`.DB(di_b),`
210			`.WEB(we_b),`
211			`.OEB(oe_b),`
212			`.MEB(ce_b),`
213			`.CLKB(clk_b)`
214			`);`
215
216			`else
217
218			`ifdef OR1200_XILINX_RAMB4
219
220			`//`
221			`// Instantiation of FPGA memory:`
222			`//`
223			`// Virtex/Spartan2`
224			`//`
225
226			`//`
227			`// Block 0`
228			`//`
229			`RAMB4_S16_S16 ramb4_s16_s16_0(`
230			`.CLKA(clk_a),`
231			`.RSTA(rst_a),`
232			`.ADDRA(addr_a),`
233			`.DIA(di_a[15:0]),`
234			`.ENA(ce_a),`
235			`.WEA(we_a),`
236			`.DOA(do_a[15:0]),`
237
238			`.CLKB(clk_b),`
239			`.RSTB(rst_b),`
240			`.ADDRB(addr_b),`
241			`.DIB(di_b[15:0]),`
242			`.ENB(ce_b),`
243			`.WEB(we_b),`
244			`.DOB(do_b[15:0])`
245			`);`
246
247			`//`
248			`// Block 1`
249			`//`
250			`RAMB4_S16_S16 ramb4_s16_s16_1(`
251			`.CLKA(clk_a),`
252			`.RSTA(rst_a),`
253			`.ADDRA(addr_a),`
254			`.DIA(di_a[31:16]),`
255			`.ENA(ce_a),`
256			`.WEA(we_a),`
257			`.DOA(do_a[31:16]),`
258
259			`.CLKB(clk_b),`
260			`.RSTB(rst_b),`
261			`.ADDRB(addr_b),`
262			`.DIB(di_b[31:16]),`
263			`.ENB(ce_b),`
264			`.WEB(we_b),`
265			`.DOB(do_b[31:16])`
266			`);`
267
268			`else
269
270			`ifdef OR1200_ALTERA_LPM_XXX
271
272			`//`
273			`// Instantiation of FPGA memory:`
274			`//`
275			`// Altera LPM`
276			`//`
277			`// Added By Jamil Khatib`
278			`//`
279			`altqpram altqpram_component (`
280			`.wraddress_a (addr_a),`
281			`.inclocken_a (ce_a),`
282			`.wraddress_b (addr_b),`
283			`.wren_a (we_a),`
284			`.inclocken_b (ce_b),`
285			`.wren_b (we_b),`
286			`.inaclr_a (rst_a),`
287			`.inaclr_b (rst_b),`
288			`.inclock_a (clk_a),`
289			`.inclock_b (clk_b),`
290			`.data_a (di_a),`
291			`.data_b (di_b),`
292			`.q_a (do_a),`
293			`.q_b (do_b)`
294			`);`
295
296			`defparam altqpram_component.operation_mode = "BIDIR_DUAL_PORT",`
297			`altqpram_component.width_write_a = dw,`
298			`altqpram_component.widthad_write_a = aw,`
299			`altqpram_component.numwords_write_a = dw,`
300			`altqpram_component.width_read_a = dw,`
301			`altqpram_component.widthad_read_a = aw,`
302			`altqpram_component.numwords_read_a = dw,`
303			`altqpram_component.width_write_b = dw,`
304			`altqpram_component.widthad_write_b = aw,`
305			`altqpram_component.numwords_write_b = dw,`
306			`altqpram_component.width_read_b = dw,`
307			`altqpram_component.widthad_read_b = aw,`
308			`altqpram_component.numwords_read_b = dw,`
309			`altqpram_component.indata_reg_a = "INCLOCK_A",`
310			`altqpram_component.wrcontrol_wraddress_reg_a = "INCLOCK_A",`
311			`altqpram_component.outdata_reg_a = "INCLOCK_A",`
312			`altqpram_component.indata_reg_b = "INCLOCK_B",`
313			`altqpram_component.wrcontrol_wraddress_reg_b = "INCLOCK_B",`
314			`altqpram_component.outdata_reg_b = "INCLOCK_B",`
315			`altqpram_component.indata_aclr_a = "INACLR_A",`
316			`altqpram_component.wraddress_aclr_a = "INACLR_A",`
317			`altqpram_component.wrcontrol_aclr_a = "INACLR_A",`
318			`altqpram_component.outdata_aclr_a = "INACLR_A",`
319			`altqpram_component.indata_aclr_b = "NONE",`
320			`altqpram_component.wraddress_aclr_b = "NONE",`
321			`altqpram_component.wrcontrol_aclr_b = "NONE",`
322			`altqpram_component.outdata_aclr_b = "INACLR_B",`
323			`altqpram_component.lpm_hint = "USE_ESB=ON";`
324			`//examplar attribute altqpram_component NOOPT TRUE`
325
326			`else
327
328			`//`
329			`// Generic two-port synchronous RAM model`
330			`//`
331
332			`//`
333			`// Generic RAM's registers and wires`
334			`//`
335			`reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content`
336			`reg [aw-1:0] addr_a_reg; // RAM read address register`
337			`reg [aw-1:0] addr_b_reg; // RAM read address register`
338
339			`//`
340			`// Data output drivers`
341			`//`
342			`assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};`
343			`assign do_b = (oe_b) ? mem[addr_b_reg] : {dw{1'b0}};`
344
345			`//`
346			`// RAM write`
347			`//`
348			`always @(posedge clk_a)`
349			`if (ce_a && we_a)`
350			`mem[addr_a] <= #1 di_a;`
351
352			`//`
353			`// RAM write`
354			`//`
355			`always @(posedge clk_b)`
356			`if (ce_b && we_b)`
357			`mem[addr_b] <= #1 di_b;`
358
359			`//`
360			`// RAM read address register`
361			`//`
362			`always @(posedge clk_a or posedge rst_a)`
363			`if (rst_a)`
364			`addr_a_reg <= #1 {aw{1'b0}};`
365			`else if (ce_a)`
366			`addr_a_reg <= #1 addr_a;`
367
368			`//`
369			`// RAM read address register`
370			`//`
371			`always @(posedge clk_b or posedge rst_b)`
372			`if (rst_b)`
373			`addr_b_reg <= #1 {aw{1'b0}};`
374			`else if (ce_b)`
375			`addr_b_reg <= #1 addr_b;`
376
377			`endif // !OR1200_ALTERA_LPM
378			`endif // !OR1200_XILINX_RAMB4_S16_S16
379			`endif // !OR1200_VIRAGE_STP
380			`endif // !OR1200_AVANT_ATP
381			`endif // !OR1200_ARTISAN_SDP
382
383			`endmodule`