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[/] [or1k/] [trunk/] [rc203soc/] [rtl/] [verilog/] [or1200/] [syn/] [synopsys/] [bin/] [README] - Blame information for rev 1765

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1 1327 jcastillo
This directory contains Synopsys Design Compiler synthesis script.
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 top.scr - main synthesis script
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 read_design.inc - used by top.scr to read design files
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 run_syn - shell script to invoke design compiler
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To run synthesis, go to ../run/

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